Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2817173	1			T26	57		T27	1		T28	1
all_pins[1]	2817173	1			T26	57		T27	1		T28	1
all_pins[2]	2817173	1			T26	57		T27	1		T28	1
all_pins[3]	2817173	1			T26	57		T27	1		T28	1
all_pins[4]	2817173	1			T26	57		T27	1		T28	1
all_pins[5]	2817173	1			T26	57		T27	1		T28	1
all_pins[6]	2817173	1			T26	57		T27	1		T28	1
all_pins[7]	2817173	1			T26	57		T27	1		T28	1
all_pins[8]	2817173	1			T26	57		T27	1		T28	1
all_pins[9]	2817173	1			T26	57		T27	1		T28	1
all_pins[10]	2817173	1			T26	57		T27	1		T28	1
all_pins[11]	2817173	1			T26	57		T27	1		T28	1
all_pins[12]	2817173	1			T26	57		T27	1		T28	1
all_pins[13]	2817173	1			T26	57		T27	1		T28	1
all_pins[14]	2817173	1			T26	57		T27	1		T28	1
all_pins[15]	2817173	1			T26	57		T27	1		T28	1
all_pins[16]	2817173	1			T26	57		T27	1		T28	1
all_pins[17]	2817173	1			T26	57		T27	1		T28	1
all_pins[18]	2817173	1			T26	57		T27	1		T28	1
all_pins[19]	2817173	1			T26	57		T27	1		T28	1
all_pins[20]	2817173	1			T26	57		T27	1		T28	1
all_pins[21]	2817173	1			T26	57		T27	1		T28	1
all_pins[22]	2817173	1			T26	57		T27	1		T28	1
all_pins[23]	2817173	1			T26	57		T27	1		T28	1
all_pins[24]	2817173	1			T26	57		T27	1		T28	1
all_pins[25]	2817173	1			T26	57		T27	1		T28	1
all_pins[26]	2817173	1			T26	57		T27	1		T28	1
all_pins[27]	2817173	1			T26	57		T27	1		T28	1
all_pins[28]	2817173	1			T26	57		T27	1		T28	1
all_pins[29]	2817173	1			T26	57		T27	1		T28	1
all_pins[30]	2817173	1			T26	57		T27	1		T28	1
all_pins[31]	2817173	1			T26	57		T27	1		T28	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	55983898	1			T26	969		T27	32		T28	32
values[0x1]	34165638	1			T26	855		T31	8554		T32	461076
transitions[0x0=>0x1]	20457783	1			T26	443		T31	4938		T32	275354
transitions[0x1=>0x0]	20457653	1			T26	442		T31	4938		T32	275353

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1752696	1			T26	27		T27	1		T28	1
all_pins[0]	values[0x1]	1064477	1			T26	30		T31	267		T32	14059
all_pins[0]	transitions[0x0=>0x1]	659216	1			T26	25		T31	176		T32	8521
all_pins[0]	transitions[0x1=>0x0]	661910	1			T26	13		T31	146		T32	9163
all_pins[1]	values[0x0]	1751241	1			T26	28		T27	1		T28	1
all_pins[1]	values[0x1]	1065932	1			T26	29		T31	257		T32	14542
all_pins[1]	transitions[0x0=>0x1]	638173	1			T26	12		T31	137		T32	8904
all_pins[1]	transitions[0x1=>0x0]	636718	1			T26	13		T31	147		T32	8421
all_pins[2]	values[0x0]	1750211	1			T26	26		T27	1		T28	1
all_pins[2]	values[0x1]	1066962	1			T26	31		T31	251		T32	14323
all_pins[2]	transitions[0x0=>0x1]	639981	1			T26	14		T31	125		T32	8483
all_pins[2]	transitions[0x1=>0x0]	638951	1			T26	12		T31	131		T32	8702
all_pins[3]	values[0x0]	1747370	1			T26	33		T27	1		T28	1
all_pins[3]	values[0x1]	1069803	1			T26	24		T31	273		T32	14426
all_pins[3]	transitions[0x0=>0x1]	639175	1			T26	10		T31	176		T32	8686
all_pins[3]	transitions[0x1=>0x0]	636334	1			T26	17		T31	154		T32	8583
all_pins[4]	values[0x0]	1751483	1			T26	28		T27	1		T28	1
all_pins[4]	values[0x1]	1065690	1			T26	29		T31	235		T32	14610
all_pins[4]	transitions[0x0=>0x1]	636238	1			T26	15		T31	139		T32	8611
all_pins[4]	transitions[0x1=>0x0]	640351	1			T26	10		T31	177		T32	8427
all_pins[5]	values[0x0]	1746946	1			T26	31		T27	1		T28	1
all_pins[5]	values[0x1]	1070227	1			T26	26		T31	270		T32	14707
all_pins[5]	transitions[0x0=>0x1]	640945	1			T26	13		T31	170		T32	8605
all_pins[5]	transitions[0x1=>0x0]	636408	1			T26	16		T31	135		T32	8508
all_pins[6]	values[0x0]	1746909	1			T26	35		T27	1		T28	1
all_pins[6]	values[0x1]	1070264	1			T26	22		T31	274		T32	14448
all_pins[6]	transitions[0x0=>0x1]	639204	1			T26	9		T31	160		T32	8540
all_pins[6]	transitions[0x1=>0x0]	639167	1			T26	13		T31	156		T32	8799
all_pins[7]	values[0x0]	1751811	1			T26	36		T27	1		T28	1
all_pins[7]	values[0x1]	1065362	1			T26	21		T31	274		T32	14190
all_pins[7]	transitions[0x0=>0x1]	635696	1			T26	12		T31	159		T32	8511
all_pins[7]	transitions[0x1=>0x0]	640598	1			T26	13		T31	159		T32	8769
all_pins[8]	values[0x0]	1749053	1			T26	29		T27	1		T28	1
all_pins[8]	values[0x1]	1068120	1			T26	28		T31	283		T32	14834
all_pins[8]	transitions[0x0=>0x1]	641393	1			T26	15		T31	177		T32	9176
all_pins[8]	transitions[0x1=>0x0]	638635	1			T26	8		T31	168		T32	8532
all_pins[9]	values[0x0]	1748997	1			T26	33		T27	1		T28	1
all_pins[9]	values[0x1]	1068176	1			T26	24		T31	284		T32	14383
all_pins[9]	transitions[0x0=>0x1]	638951	1			T26	12		T31	166		T32	8438
all_pins[9]	transitions[0x1=>0x0]	638895	1			T26	16		T31	165		T32	8889
all_pins[10]	values[0x0]	1756220	1			T26	26		T27	1		T28	1
all_pins[10]	values[0x1]	1060953	1			T26	31		T31	298		T32	14404
all_pins[10]	transitions[0x0=>0x1]	635688	1			T26	19		T31	169		T32	8722
all_pins[10]	transitions[0x1=>0x0]	642911	1			T26	12		T31	155		T32	8701
all_pins[11]	values[0x0]	1746739	1			T26	29		T27	1		T28	1
all_pins[11]	values[0x1]	1070434	1			T26	28		T31	310		T32	14223
all_pins[11]	transitions[0x0=>0x1]	643844	1			T26	17		T31	167		T32	8457
all_pins[11]	transitions[0x1=>0x0]	634363	1			T26	20		T31	155		T32	8638
all_pins[12]	values[0x0]	1751081	1			T26	31		T27	1		T28	1
all_pins[12]	values[0x1]	1066092	1			T26	26		T31	253		T32	14360
all_pins[12]	transitions[0x0=>0x1]	636062	1			T26	11		T31	121		T32	8689
all_pins[12]	transitions[0x1=>0x0]	640404	1			T26	13		T31	178		T32	8552
all_pins[13]	values[0x0]	1749931	1			T26	29		T27	1		T28	1
all_pins[13]	values[0x1]	1067242	1			T26	28		T31	258		T32	13886
all_pins[13]	transitions[0x0=>0x1]	637685	1			T26	11		T31	132		T32	8109
all_pins[13]	transitions[0x1=>0x0]	636535	1			T26	9		T31	127		T32	8583
all_pins[14]	values[0x0]	1749796	1			T26	33		T27	1		T28	1
all_pins[14]	values[0x1]	1067377	1			T26	24		T31	270		T32	14475
all_pins[14]	transitions[0x0=>0x1]	636434	1			T26	14		T31	163		T32	8846
all_pins[14]	transitions[0x1=>0x0]	636299	1			T26	18		T31	151		T32	8257
all_pins[15]	values[0x0]	1751358	1			T26	36		T27	1		T28	1
all_pins[15]	values[0x1]	1065815	1			T26	21		T31	243		T32	14760
all_pins[15]	transitions[0x0=>0x1]	638944	1			T26	10		T31	145		T32	8740
all_pins[15]	transitions[0x1=>0x0]	640506	1			T26	13		T31	172		T32	8455
all_pins[16]	values[0x0]	1749555	1			T26	34		T27	1		T28	1
all_pins[16]	values[0x1]	1067618	1			T26	23		T31	302		T32	14176
all_pins[16]	transitions[0x0=>0x1]	638133	1			T26	17		T31	182		T32	8144
all_pins[16]	transitions[0x1=>0x0]	636330	1			T26	15		T31	123		T32	8728
all_pins[17]	values[0x0]	1744593	1			T26	25		T27	1		T28	1
all_pins[17]	values[0x1]	1072580	1			T26	32		T31	272		T32	13898
all_pins[17]	transitions[0x0=>0x1]	640515	1			T26	22		T31	163		T32	8385
all_pins[17]	transitions[0x1=>0x0]	635553	1			T26	13		T31	193		T32	8663
all_pins[18]	values[0x0]	1750500	1			T26	27		T27	1		T28	1
all_pins[18]	values[0x1]	1066673	1			T26	30		T31	238		T32	14115
all_pins[18]	transitions[0x0=>0x1]	637329	1			T26	17		T31	135		T32	8492
all_pins[18]	transitions[0x1=>0x0]	643236	1			T26	19		T31	169		T32	8275
all_pins[19]	values[0x0]	1743208	1			T26	21		T27	1		T28	1
all_pins[19]	values[0x1]	1073965	1			T26	36		T31	260		T32	13849
all_pins[19]	transitions[0x0=>0x1]	642135	1			T26	17		T31	152		T32	8551
all_pins[19]	transitions[0x1=>0x0]	634843	1			T26	11		T31	130		T32	8817
all_pins[20]	values[0x0]	1748124	1			T26	27		T27	1		T28	1
all_pins[20]	values[0x1]	1069049	1			T26	30		T31	224		T32	14697
all_pins[20]	transitions[0x0=>0x1]	636678	1			T26	9		T31	136		T32	9091
all_pins[20]	transitions[0x1=>0x0]	641594	1			T26	15		T31	172		T32	8243
all_pins[21]	values[0x0]	1749938	1			T26	21		T27	1		T28	1
all_pins[21]	values[0x1]	1067235	1			T26	36		T31	268		T32	14361
all_pins[21]	transitions[0x0=>0x1]	636954	1			T26	15		T31	163		T32	8515
all_pins[21]	transitions[0x1=>0x0]	638768	1			T26	9		T31	119		T32	8851
all_pins[22]	values[0x0]	1751204	1			T26	34		T27	1		T28	1
all_pins[22]	values[0x1]	1065969	1			T26	23		T31	289		T32	14678
all_pins[22]	transitions[0x0=>0x1]	637257	1			T26	3		T31	143		T32	8765
all_pins[22]	transitions[0x1=>0x0]	638523	1			T26	16		T31	122		T32	8448
all_pins[23]	values[0x0]	1749866	1			T26	38		T27	1		T28	1
all_pins[23]	values[0x1]	1067307	1			T26	19		T31	310		T32	14853
all_pins[23]	transitions[0x0=>0x1]	638843	1			T26	10		T31	185		T32	8667
all_pins[23]	transitions[0x1=>0x0]	637505	1			T26	14		T31	164		T32	8492
all_pins[24]	values[0x0]	1750022	1			T26	41		T27	1		T28	1
all_pins[24]	values[0x1]	1067151	1			T26	16		T31	272		T32	14544
all_pins[24]	transitions[0x0=>0x1]	637809	1			T26	10		T31	117		T32	8454
all_pins[24]	transitions[0x1=>0x0]	637965	1			T26	13		T31	155		T32	8763
all_pins[25]	values[0x0]	1749431	1			T26	30		T27	1		T28	1
all_pins[25]	values[0x1]	1067742	1			T26	27		T31	210		T32	14522
all_pins[25]	transitions[0x0=>0x1]	641350	1			T26	21		T31	110		T32	8524
all_pins[25]	transitions[0x1=>0x0]	640759	1			T26	10		T31	172		T32	8546
all_pins[26]	values[0x0]	1749913	1			T26	33		T27	1		T28	1
all_pins[26]	values[0x1]	1067260	1			T26	24		T31	257		T32	14042
all_pins[26]	transitions[0x0=>0x1]	636836	1			T26	15		T31	177		T32	8049
all_pins[26]	transitions[0x1=>0x0]	637318	1			T26	18		T31	130		T32	8529
all_pins[27]	values[0x0]	1750731	1			T26	32		T27	1		T28	1
all_pins[27]	values[0x1]	1066442	1			T26	25		T31	195		T32	14280
all_pins[27]	transitions[0x0=>0x1]	638704	1			T26	14		T31	107		T32	8775
all_pins[27]	transitions[0x1=>0x0]	639522	1			T26	13		T31	169		T32	8537
all_pins[28]	values[0x0]	1744315	1			T26	24		T27	1		T28	1
all_pins[28]	values[0x1]	1072858	1			T26	33		T31	332		T32	14460
all_pins[28]	transitions[0x0=>0x1]	642532	1			T26	17		T31	224		T32	8745
all_pins[28]	transitions[0x1=>0x0]	636116	1			T26	9		T31	87		T32	8565
all_pins[29]	values[0x0]	1750373	1			T26	30		T27	1		T28	1
all_pins[29]	values[0x1]	1066800	1			T26	27		T31	297		T32	14246
all_pins[29]	transitions[0x0=>0x1]	637973	1			T26	14		T31	162		T32	8442
all_pins[29]	transitions[0x1=>0x0]	644031	1			T26	20		T31	197		T32	8656
all_pins[30]	values[0x0]	1750411	1			T26	24		T27	1		T28	1
all_pins[30]	values[0x1]	1066762	1			T26	33		T31	291		T32	15023
all_pins[30]	transitions[0x0=>0x1]	637059	1			T26	14		T31	148		T32	9081
all_pins[30]	transitions[0x1=>0x0]	637097	1			T26	8		T31	154		T32	8304
all_pins[31]	values[0x0]	1749872	1			T26	38		T27	1		T28	1
all_pins[31]	values[0x1]	1067301	1			T26	19		T31	237		T32	14702
all_pins[31]	transitions[0x0=>0x1]	640047	1			T26	9		T31	152		T32	8636
all_pins[31]	transitions[0x1=>0x0]	639508	1			T26	23		T31	206		T32	8957