Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	10181415	1			T26	828		T27	283		T28	1
all_values[1]	10181415	1			T26	828		T27	283		T28	1
all_values[2]	10181415	1			T26	828		T27	283		T28	1
all_values[3]	10181415	1			T26	828		T27	283		T28	1
all_values[4]	10181415	1			T26	828		T27	283		T28	1
all_values[5]	10181415	1			T26	828		T27	283		T28	1
all_values[6]	10181415	1			T26	828		T27	283		T28	1
all_values[7]	10181415	1			T26	828		T27	283		T28	1
all_values[8]	10181415	1			T26	828		T27	283		T28	1
all_values[9]	10181415	1			T26	828		T27	283		T28	1
all_values[10]	10181415	1			T26	828		T27	283		T28	1
all_values[11]	10181415	1			T26	828		T27	283		T28	1
all_values[12]	10181415	1			T26	828		T27	283		T28	1
all_values[13]	10181415	1			T26	828		T27	283		T28	1
all_values[14]	10181415	1			T26	828		T27	283		T28	1
all_values[15]	10181415	1			T26	828		T27	283		T28	1
all_values[16]	10181415	1			T26	828		T27	283		T28	1
all_values[17]	10181415	1			T26	828		T27	283		T28	1
all_values[18]	10181415	1			T26	828		T27	283		T28	1
all_values[19]	10181415	1			T26	828		T27	283		T28	1
all_values[20]	10181415	1			T26	828		T27	283		T28	1
all_values[21]	10181415	1			T26	828		T27	283		T28	1
all_values[22]	10181415	1			T26	828		T27	283		T28	1
all_values[23]	10181415	1			T26	828		T27	283		T28	1
all_values[24]	10181415	1			T26	828		T27	283		T28	1
all_values[25]	10181415	1			T26	828		T27	283		T28	1
all_values[26]	10181415	1			T26	828		T27	283		T28	1
all_values[27]	10181415	1			T26	828		T27	283		T28	1
all_values[28]	10181415	1			T26	828		T27	283		T28	1
all_values[29]	10181415	1			T26	828		T27	283		T28	1
all_values[30]	10181415	1			T26	828		T27	283		T28	1
all_values[31]	10181415	1			T26	828		T27	283		T28	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

198291493

1

T26

26496

T27

9056

T28

32

auto[1]

127513787

1

T31

30773

T32

166669

T33

15978

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95253751

1

T26

26496

T27

9056

T28

32

auto[1]

230551529

1

T31

53924

T32

300664

T33

26988

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

322441189

1

T26

26496

T27

9056

T28

32

auto[1]

3364091

1

T31

2708

T32

51930

T33

1119

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2593481	1			T26	828		T27	283		T28	1
all_values[0]	auto[0]	auto[0]	auto[1]	3558366	1			T31	741		T32	46980		T33	360
all_values[0]	auto[0]	auto[1]	auto[0]	392695	1			T31	140		T32	5289		T33	69
all_values[0]	auto[0]	auto[1]	auto[1]	3531350	1			T31	864		T32	44794		T33	432
all_values[0]	auto[1]	auto[0]	auto[1]	52766	1			T31	38		T32	841		T33	20
all_values[0]	auto[1]	auto[1]	auto[1]	52757	1			T31	45		T32	887		T33	14
all_values[1]	auto[0]	auto[0]	auto[0]	2585054	1			T26	828		T27	283		T28	1
all_values[1]	auto[0]	auto[0]	auto[1]	3559291	1			T31	892		T32	45934		T33	356
all_values[1]	auto[0]	auto[1]	auto[0]	386617	1			T31	103		T32	5586		T33	63
all_values[1]	auto[0]	auto[1]	auto[1]	3545174	1			T31	678		T32	46464		T33	488
all_values[1]	auto[1]	auto[0]	auto[1]	53026	1			T31	51		T32	810		T33	16
all_values[1]	auto[1]	auto[1]	auto[1]	52253	1			T31	36		T32	804		T33	17
all_values[2]	auto[0]	auto[0]	auto[0]	2593983	1			T26	828		T27	283		T28	1
all_values[2]	auto[0]	auto[0]	auto[1]	3542930	1			T31	842		T32	48051		T33	488
all_values[2]	auto[0]	auto[1]	auto[0]	387448	1			T31	87		T32	5077		T33	54
all_values[2]	auto[0]	auto[1]	auto[1]	3551803	1			T31	806		T32	44850		T33	354
all_values[2]	auto[1]	auto[0]	auto[1]	52751	1			T31	51		T32	810		T33	16
all_values[2]	auto[1]	auto[1]	auto[1]	52500	1			T31	29		T32	825		T33	15
all_values[3]	auto[0]	auto[0]	auto[0]	2585886	1			T26	828		T27	283		T28	1
all_values[3]	auto[0]	auto[0]	auto[1]	3570097	1			T31	761		T32	47147		T33	326
all_values[3]	auto[0]	auto[1]	auto[0]	382544	1			T31	86		T32	5341		T33	89
all_values[3]	auto[0]	auto[1]	auto[1]	3537897	1			T31	815		T32	44605		T33	372
all_values[3]	auto[1]	auto[0]	auto[1]	53067	1			T31	39		T32	841		T33	17
all_values[3]	auto[1]	auto[1]	auto[1]	51924	1			T31	55		T32	763		T33	18
all_values[4]	auto[0]	auto[0]	auto[0]	2600034	1			T26	828		T27	283		T28	1
all_values[4]	auto[0]	auto[0]	auto[1]	3555581	1			T31	831		T32	45058		T33	362
all_values[4]	auto[0]	auto[1]	auto[0]	389970	1			T31	108		T32	5193		T33	46
all_values[4]	auto[0]	auto[1]	auto[1]	3530527	1			T31	707		T32	47976		T33	455
all_values[4]	auto[1]	auto[0]	auto[1]	52925	1			T31	47		T32	806		T33	20
all_values[4]	auto[1]	auto[1]	auto[1]	52378	1			T31	41		T32	848		T33	20
all_values[5]	auto[0]	auto[0]	auto[0]	2590508	1			T26	828		T27	283		T28	1
all_values[5]	auto[0]	auto[0]	auto[1]	3550954	1			T31	820		T32	45819		T33	504
all_values[5]	auto[0]	auto[1]	auto[0]	388046	1			T31	77		T32	5161		T33	59
all_values[5]	auto[0]	auto[1]	auto[1]	3546534	1			T31	825		T32	47109		T33	312
all_values[5]	auto[1]	auto[0]	auto[1]	52793	1			T31	44		T32	799		T33	19
all_values[5]	auto[1]	auto[1]	auto[1]	52580	1			T31	40		T32	793		T33	10
all_values[6]	auto[0]	auto[0]	auto[0]	2591107	1			T26	828		T27	283		T28	1
all_values[6]	auto[0]	auto[0]	auto[1]	3523075	1			T31	825		T32	47418		T33	377
all_values[6]	auto[0]	auto[1]	auto[0]	382524	1			T31	104		T32	5435		T33	29
all_values[6]	auto[0]	auto[1]	auto[1]	3579716	1			T31	800		T32	45138		T33	504
all_values[6]	auto[1]	auto[0]	auto[1]	52722	1			T31	38		T32	820		T33	15
all_values[6]	auto[1]	auto[1]	auto[1]	52271	1			T31	39		T32	763		T33	16
all_values[7]	auto[0]	auto[0]	auto[0]	2587446	1			T26	828		T27	283		T28	1
all_values[7]	auto[0]	auto[0]	auto[1]	3534869	1			T31	680		T32	46966		T33	444
all_values[7]	auto[0]	auto[1]	auto[0]	392296	1			T31	139		T32	5202		T33	49
all_values[7]	auto[0]	auto[1]	auto[1]	3561762	1			T31	873		T32	45646		T33	396
all_values[7]	auto[1]	auto[0]	auto[1]	52656	1			T31	38		T32	873		T33	14
all_values[7]	auto[1]	auto[1]	auto[1]	52386	1			T31	53		T32	765		T33	21
all_values[8]	auto[0]	auto[0]	auto[0]	2592690	1			T26	828		T27	283		T28	1
all_values[8]	auto[0]	auto[0]	auto[1]	3542822	1			T31	772		T32	44990		T33	499
all_values[8]	auto[0]	auto[1]	auto[0]	385378	1			T31	76		T32	5311		T33	75
all_values[8]	auto[0]	auto[1]	auto[1]	3555577	1			T31	843		T32	47797		T33	319
all_values[8]	auto[1]	auto[0]	auto[1]	52631	1			T31	34		T32	758		T33	20
all_values[8]	auto[1]	auto[1]	auto[1]	52317	1			T31	45		T32	848		T33	16
all_values[9]	auto[0]	auto[0]	auto[0]	2583899	1			T26	828		T27	283		T28	1
all_values[9]	auto[0]	auto[0]	auto[1]	3529619	1			T31	592		T32	45617		T33	445
all_values[9]	auto[0]	auto[1]	auto[0]	396301	1			T31	153		T32	6141		T33	82
all_values[9]	auto[0]	auto[1]	auto[1]	3566246	1			T31	925		T32	46033		T33	309
all_values[9]	auto[1]	auto[0]	auto[1]	52920	1			T31	34		T32	794		T33	25
all_values[9]	auto[1]	auto[1]	auto[1]	52430	1			T31	59		T32	767		T33	12
all_values[10]	auto[0]	auto[0]	auto[0]	2594259	1			T26	828		T27	283		T28	1
all_values[10]	auto[0]	auto[0]	auto[1]	3576380	1			T31	705		T32	45292		T33	395
all_values[10]	auto[0]	auto[1]	auto[0]	386245	1			T31	182		T32	5405		T33	52
all_values[10]	auto[0]	auto[1]	auto[1]	3519163	1			T31	837		T32	47006		T33	429
all_values[10]	auto[1]	auto[0]	auto[1]	52761	1			T31	41		T32	831		T33	28
all_values[10]	auto[1]	auto[1]	auto[1]	52607	1			T31	50		T32	820		T33	11
all_values[11]	auto[0]	auto[0]	auto[0]	2590827	1			T26	828		T27	283		T28	1
all_values[11]	auto[0]	auto[0]	auto[1]	3539325	1			T31	692		T32	47742		T33	491
all_values[11]	auto[0]	auto[1]	auto[0]	385308	1			T31	107		T32	5096		T33	82
all_values[11]	auto[0]	auto[1]	auto[1]	3560804	1			T31	936		T32	44197		T33	279
all_values[11]	auto[1]	auto[0]	auto[1]	52674	1			T31	32		T32	855		T33	22
all_values[11]	auto[1]	auto[1]	auto[1]	52477	1			T31	52		T32	790		T33	17
all_values[12]	auto[0]	auto[0]	auto[0]	2588797	1			T26	828		T27	283		T28	1
all_values[12]	auto[0]	auto[0]	auto[1]	3552494	1			T31	791		T32	45251		T33	318
all_values[12]	auto[0]	auto[1]	auto[0]	386732	1			T31	102		T32	5500		T33	106
all_values[12]	auto[0]	auto[1]	auto[1]	3548392	1			T31	777		T32	46740		T33	399
all_values[12]	auto[1]	auto[0]	auto[1]	52847	1			T31	46		T32	844		T33	22
all_values[12]	auto[1]	auto[1]	auto[1]	52153	1			T31	35		T32	797		T33	15
all_values[13]	auto[0]	auto[0]	auto[0]	2595483	1			T26	828		T27	283		T28	1
all_values[13]	auto[0]	auto[0]	auto[1]	3590217	1			T31	897		T32	48325		T33	456
all_values[13]	auto[0]	auto[1]	auto[0]	392446	1			T31	133		T32	5173		T33	52
all_values[13]	auto[0]	auto[1]	auto[1]	3498273	1			T31	715		T32	44262		T33	378
all_values[13]	auto[1]	auto[0]	auto[1]	52793	1			T31	49		T32	844		T33	18
all_values[13]	auto[1]	auto[1]	auto[1]	52203	1			T31	40		T32	761		T33	14
all_values[14]	auto[0]	auto[0]	auto[0]	2585814	1			T26	828		T27	283		T28	1
all_values[14]	auto[0]	auto[0]	auto[1]	3552875	1			T31	882		T32	45744		T33	331
all_values[14]	auto[0]	auto[1]	auto[0]	387922	1			T31	83		T32	5425		T33	57
all_values[14]	auto[0]	auto[1]	auto[1]	3550017	1			T31	765		T32	46950		T33	501
all_values[14]	auto[1]	auto[0]	auto[1]	52217	1			T31	37		T32	864		T33	12
all_values[14]	auto[1]	auto[1]	auto[1]	52570	1			T31	38		T32	787		T33	15
all_values[15]	auto[0]	auto[0]	auto[0]	2597215	1			T26	828		T27	283		T28	1
all_values[15]	auto[0]	auto[0]	auto[1]	3546703	1			T31	986		T32	44867		T33	394
all_values[15]	auto[0]	auto[1]	auto[0]	382941	1			T31	106		T32	5354		T33	63
all_values[15]	auto[0]	auto[1]	auto[1]	3549258	1			T31	689		T32	47183		T33	414
all_values[15]	auto[1]	auto[0]	auto[1]	52950	1			T31	53		T32	792		T33	17
all_values[15]	auto[1]	auto[1]	auto[1]	52348	1			T31	33		T32	813		T33	20
all_values[16]	auto[0]	auto[0]	auto[0]	2586968	1			T26	828		T27	283		T28	1
all_values[16]	auto[0]	auto[0]	auto[1]	3556207	1			T31	770		T32	48215		T33	267
all_values[16]	auto[0]	auto[1]	auto[0]	384054	1			T31	134		T32	4978		T33	101
all_values[16]	auto[0]	auto[1]	auto[1]	3549011	1			T31	853		T32	44626		T33	483
all_values[16]	auto[1]	auto[0]	auto[1]	52803	1			T31	39		T32	896		T33	15
all_values[16]	auto[1]	auto[1]	auto[1]	52372	1			T31	41		T32	729		T33	18
all_values[17]	auto[0]	auto[0]	auto[0]	2584220	1			T26	828		T27	283		T28	1
all_values[17]	auto[0]	auto[0]	auto[1]	3539774	1			T31	806		T32	48422		T33	381
all_values[17]	auto[0]	auto[1]	auto[0]	387957	1			T31	74		T32	4994		T33	41
all_values[17]	auto[0]	auto[1]	auto[1]	3564366	1			T31	824		T32	44300		T33	485
all_values[17]	auto[1]	auto[0]	auto[1]	52603	1			T31	41		T32	834		T33	19
all_values[17]	auto[1]	auto[1]	auto[1]	52495	1			T31	45		T32	786		T33	18
all_values[18]	auto[0]	auto[0]	auto[0]	2588820	1			T26	828		T27	283		T28	1
all_values[18]	auto[0]	auto[0]	auto[1]	3548537	1			T31	839		T32	47351		T33	327
all_values[18]	auto[0]	auto[1]	auto[0]	384159	1			T31	129		T32	5152		T33	125
all_values[18]	auto[0]	auto[1]	auto[1]	3554880	1			T31	722		T32	45103		T33	391
all_values[18]	auto[1]	auto[0]	auto[1]	52880	1			T31	49		T32	841		T33	15
all_values[18]	auto[1]	auto[1]	auto[1]	52139	1			T31	34		T32	770		T33	14
all_values[19]	auto[0]	auto[0]	auto[0]	2585278	1			T26	828		T27	283		T28	1
all_values[19]	auto[0]	auto[0]	auto[1]	3533578	1			T31	884		T32	48363		T33	410
all_values[19]	auto[0]	auto[1]	auto[0]	381469	1			T31	59		T32	5042		T33	32
all_values[19]	auto[0]	auto[1]	auto[1]	3575960	1			T31	800		T32	44021		T33	413
all_values[19]	auto[1]	auto[0]	auto[1]	53107	1			T31	43		T32	857		T33	18
all_values[19]	auto[1]	auto[1]	auto[1]	52023	1			T31	42		T32	779		T33	17
all_values[20]	auto[0]	auto[0]	auto[0]	2582920	1			T26	828		T27	283		T28	1
all_values[20]	auto[0]	auto[0]	auto[1]	3551161	1			T31	846		T32	44230		T33	194
all_values[20]	auto[0]	auto[1]	auto[0]	386679	1			T31	89		T32	5358		T33	108
all_values[20]	auto[0]	auto[1]	auto[1]	3555375	1			T31	707		T32	48149		T33	612
all_values[20]	auto[1]	auto[0]	auto[1]	53069	1			T31	46		T32	802		T33	10
all_values[20]	auto[1]	auto[1]	auto[1]	52211	1			T31	45		T32	828		T33	30
all_values[21]	auto[0]	auto[0]	auto[0]	2585282	1			T26	828		T27	283		T28	1
all_values[21]	auto[0]	auto[0]	auto[1]	3552041	1			T31	803		T32	47373		T33	400
all_values[21]	auto[0]	auto[1]	auto[0]	385580	1			T31	83		T32	5009		T33	56
all_values[21]	auto[0]	auto[1]	auto[1]	3553715	1			T31	813		T32	45113		T33	479
all_values[21]	auto[1]	auto[0]	auto[1]	52747	1			T31	38		T32	792		T33	15
all_values[21]	auto[1]	auto[1]	auto[1]	52050	1			T31	39		T32	807		T33	12
all_values[22]	auto[0]	auto[0]	auto[0]	2583412	1			T26	828		T27	283		T28	1
all_values[22]	auto[0]	auto[0]	auto[1]	3557294	1			T31	737		T32	44996		T33	470
all_values[22]	auto[0]	auto[1]	auto[0]	391119	1			T31	205		T32	6380		T33	34
all_values[22]	auto[0]	auto[1]	auto[1]	3544744	1			T31	799		T32	46488		T33	349
all_values[22]	auto[1]	auto[0]	auto[1]	52860	1			T31	35		T32	771		T33	18
all_values[22]	auto[1]	auto[1]	auto[1]	51986	1			T31	42		T32	826		T33	22
all_values[23]	auto[0]	auto[0]	auto[0]	2589661	1			T26	828		T27	283		T28	1
all_values[23]	auto[0]	auto[0]	auto[1]	3561568	1			T31	722		T32	43853		T33	416
all_values[23]	auto[0]	auto[1]	auto[0]	387989	1			T31	120		T32	5402		T33	39
all_values[23]	auto[0]	auto[1]	auto[1]	3536763	1			T31	910		T32	48535		T33	439
all_values[23]	auto[1]	auto[0]	auto[1]	52909	1			T31	38		T32	821		T33	20
all_values[23]	auto[1]	auto[1]	auto[1]	52525	1			T31	44		T32	798		T33	19
all_values[24]	auto[0]	auto[0]	auto[0]	2591361	1			T26	828		T27	283		T28	1
all_values[24]	auto[0]	auto[0]	auto[1]	3571664	1			T31	747		T32	46480		T33	492
all_values[24]	auto[0]	auto[1]	auto[0]	384508	1			T31	88		T32	5289		T33	67
all_values[24]	auto[0]	auto[1]	auto[1]	3528771	1			T31	886		T32	46021		T33	289
all_values[24]	auto[1]	auto[0]	auto[1]	52787	1			T31	35		T32	803		T33	25
all_values[24]	auto[1]	auto[1]	auto[1]	52324	1			T31	48		T32	799		T33	18
all_values[25]	auto[0]	auto[0]	auto[0]	2590612	1			T26	828		T27	283		T28	1
all_values[25]	auto[0]	auto[0]	auto[1]	3560188	1			T31	922		T32	47077		T33	443
all_values[25]	auto[0]	auto[1]	auto[0]	390114	1			T31	104		T32	5720		T33	33
all_values[25]	auto[0]	auto[1]	auto[1]	3535589	1			T31	662		T32	45158		T33	441
all_values[25]	auto[1]	auto[0]	auto[1]	52829	1			T31	51		T32	829		T33	16
all_values[25]	auto[1]	auto[1]	auto[1]	52083	1			T31	32		T32	809		T33	13
all_values[26]	auto[0]	auto[0]	auto[0]	2592286	1			T26	828		T27	283		T28	1
all_values[26]	auto[0]	auto[0]	auto[1]	3545307	1			T31	821		T32	48115		T33	464
all_values[26]	auto[0]	auto[1]	auto[0]	384501	1			T31	109		T32	4952		T33	35
all_values[26]	auto[0]	auto[1]	auto[1]	3554222	1			T31	765		T32	44666		T33	411
all_values[26]	auto[1]	auto[0]	auto[1]	52624	1			T31	42		T32	781		T33	16
all_values[26]	auto[1]	auto[1]	auto[1]	52475	1			T31	42		T32	769		T33	22
all_values[27]	auto[0]	auto[0]	auto[0]	2584972	1			T26	828		T27	283		T28	1
all_values[27]	auto[0]	auto[0]	auto[1]	3615148	1			T31	964		T32	47169		T33	274
all_values[27]	auto[0]	auto[1]	auto[0]	394124	1			T31	144		T32	5374		T33	139
all_values[27]	auto[0]	auto[1]	auto[1]	3481805	1			T31	571		T32	45203		T33	474
all_values[27]	auto[1]	auto[0]	auto[1]	52900	1			T31	48		T32	844		T33	13
all_values[27]	auto[1]	auto[1]	auto[1]	52466	1			T31	38		T32	806		T33	16
all_values[28]	auto[0]	auto[0]	auto[0]	2590838	1			T26	828		T27	283		T28	1
all_values[28]	auto[0]	auto[0]	auto[1]	3534151	1			T31	597		T32	44833		T33	415
all_values[28]	auto[0]	auto[1]	auto[0]	393824	1			T31	113		T32	5675		T33	42
all_values[28]	auto[0]	auto[1]	auto[1]	3557326	1			T31	1028		T32	47407		T33	425
all_values[28]	auto[1]	auto[0]	auto[1]	52441	1			T31	36		T32	767		T33	25
all_values[28]	auto[1]	auto[1]	auto[1]	52835	1			T31	56		T32	833		T33	14
all_values[29]	auto[0]	auto[0]	auto[0]	2585613	1			T26	828		T27	283		T28	1
all_values[29]	auto[0]	auto[0]	auto[1]	3565591	1			T31	652		T32	45955		T33	298
all_values[29]	auto[0]	auto[1]	auto[0]	381325	1			T31	160		T32	5218		T33	149
all_values[29]	auto[0]	auto[1]	auto[1]	3543697	1			T31	915		T32	45353		T33	446
all_values[29]	auto[1]	auto[0]	auto[1]	52849	1			T31	34		T32	815		T33	10
all_values[29]	auto[1]	auto[1]	auto[1]	52340	1			T31	54		T32	808		T33	25
all_values[30]	auto[0]	auto[0]	auto[0]	2585928	1			T26	828		T27	283		T28	1
all_values[30]	auto[0]	auto[0]	auto[1]	3574229	1			T31	682		T32	44868		T33	438
all_values[30]	auto[0]	auto[1]	auto[0]	385899	1			T31	115		T32	5495		T33	47
all_values[30]	auto[0]	auto[1]	auto[1]	3530742	1			T31	974		T32	47483		T33	368
all_values[30]	auto[1]	auto[0]	auto[1]	52517	1			T31	40		T32	846		T33	17
all_values[30]	auto[1]	auto[1]	auto[1]	52100	1			T31	44		T32	783		T33	19
all_values[31]	auto[0]	auto[0]	auto[0]	2595692	1			T26	828		T27	283		T28	1
all_values[31]	auto[0]	auto[0]	auto[1]	3549986	1			T31	894		T32	46706		T33	343
all_values[31]	auto[0]	auto[1]	auto[0]	384691	1			T31	67		T32	5865		T33	58
all_values[31]	auto[0]	auto[1]	auto[1]	3545957	1			T31	737		T32	45135		T33	445
all_values[31]	auto[1]	auto[0]	auto[1]	52701	1			T31	48		T32	862		T33	12
all_values[31]	auto[1]	auto[1]	auto[1]	52388	1			T31	37		T32	826		T33	26

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal