Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[1]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[2]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[3]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[4]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[5]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[6]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[7]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[8]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[9]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[10]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[11]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[12]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[13]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[14]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[15]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[16]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[17]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[18]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[19]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[20]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[21]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[22]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[23]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[24]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[25]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[26]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[27]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[28]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[29]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[30]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[31]	10097501	1			T26	828		T27	537		T28	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

185467393

1

T26

13251

T27

13512

T28

32

auto[1]

137652639

1

T26

13245

T27

3672

T30

18689

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

262248981

1

T26

26496

T27

12623

T28

32

auto[1]

60871051

1

T27

4561

T30

10668

T31

24518

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244371524

1

T26

26496

T27

8586

T28

32

auto[1]

78748508

1

T27

8598

T30

10609

T31

28985

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	3707565	1			T26	433		T27	206		T28	1
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2973146	1			T26	395		T27	25		T30	276
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	957170	1			T27	54		T30	158		T31	375
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1116683	1			T27	149		T31	494		T32	1444
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	390198	1			T27	22		T30	188		T31	21
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	952739	1			T27	81		T30	127		T31	401
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	3699622	1			T26	420		T27	156		T28	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2975170	1			T26	408		T27	13		T30	201
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	959827	1			T27	55		T30	159		T31	468
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1124783	1			T27	203		T31	410		T32	1463
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	390147	1			T27	29		T30	174		T31	38
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	947952	1			T27	81		T30	206		T31	392
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	3712338	1			T26	377		T27	128		T28	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2967145	1			T26	451		T27	17		T30	285
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	956708	1			T27	91		T30	141		T31	371
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1122410	1			T27	198		T31	555		T32	1403
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	388997	1			T27	24		T30	168		T31	28
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	949903	1			T27	79		T30	152		T31	396
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	3718665	1			T26	391		T27	238		T28	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2953318	1			T26	437		T27	29		T30	261
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	956045	1			T27	65		T30	142		T31	435
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1126012	1			T27	156		T31	511		T32	1527
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	391111	1			T27	14		T30	165		T31	20
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	952350	1			T27	35		T30	178		T31	299
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	3717098	1			T26	404		T27	142		T28	1
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2958308	1			T26	424		T27	12		T30	228
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	955821	1			T27	39		T30	185		T31	342
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1125655	1			T27	208		T31	487		T32	1462
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	388395	1			T27	36		T30	132		T31	29
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	952224	1			T27	100		T30	200		T31	408
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	3706461	1			T26	364		T27	147		T28	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2975350	1			T26	464		T27	15		T30	265
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	958941	1			T27	73		T30	164		T31	336
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1121769	1			T27	208		T31	553		T32	1558
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	388090	1			T27	33		T30	158		T31	33
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	946890	1			T27	61		T30	169		T31	425
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	3712939	1			T26	477		T27	170		T28	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2967767	1			T26	351		T27	32		T30	253
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	959176	1			T27	81		T30	166		T31	456
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1120139	1			T27	160		T31	454		T32	1549
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	388101	1			T27	17		T30	152		T31	20
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	949379	1			T27	77		T30	179		T31	401
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	3725631	1			T26	409		T27	183		T28	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2954497	1			T26	419		T27	27		T30	238
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	954192	1			T27	80		T30	203		T31	406
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1120590	1			T27	188		T31	311		T32	1497
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	389841	1			T27	12		T30	150		T31	10
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	952750	1			T27	47		T30	154		T31	411
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	3713775	1			T26	336		T27	175		T28	1
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2966143	1			T26	492		T27	12		T30	238
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	956038	1			T27	57		T30	195		T31	396
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1124414	1			T27	203		T31	421		T32	1535
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	387751	1			T27	31		T30	158		T31	30
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	949380	1			T27	59		T30	162		T31	417
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	3712405	1			T26	367		T27	112		T28	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2967486	1			T26	461		T27	8		T30	246
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	955266	1			T27	40		T30	201		T31	394
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1122858	1			T27	227		T31	416		T32	1428
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	391584	1			T27	34		T30	128		T31	16
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	947902	1			T27	116		T30	180		T31	339
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	3714500	1			T26	420		T27	168		T28	1
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2965869	1			T26	408		T27	22		T30	286
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	957558	1			T27	66		T30	195		T31	391
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1119247	1			T27	173		T31	537		T32	1518
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	388977	1			T27	30		T30	154		T31	22
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	951350	1			T27	78		T30	126		T31	351
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	3712579	1			T26	416		T27	158		T28	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2971120	1			T26	412		T27	25		T30	252
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	953056	1			T27	51		T30	156		T31	414
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1122382	1			T27	227		T31	442		T32	1523
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	391141	1			T27	22		T30	152		T31	22
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	947223	1			T27	54		T30	184		T31	417
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	3711823	1			T26	424		T27	254		T28	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2969964	1			T26	404		T27	29		T30	277
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	953063	1			T27	102		T30	166		T31	362
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1124210	1			T27	107		T31	471		T32	1543
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	388294	1			T27	12		T30	136		T31	11
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	950147	1			T27	33		T30	167		T31	471
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	3710155	1			T26	429		T27	131		T28	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2972592	1			T26	399		T27	8		T30	215
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	959857	1			T27	73		T30	152		T31	445
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1121792	1			T27	182		T31	469		T32	1497
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	388149	1			T27	29		T30	198		T31	26
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	944956	1			T27	114		T30	181		T31	324
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	3717041	1			T26	432		T27	178		T28	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2956071	1			T26	396		T27	22		T30	261
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	955722	1			T27	73		T30	191		T31	364
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1123708	1			T27	166		T31	502		T32	1598
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	389889	1			T27	30		T30	146		T31	20
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	955070	1			T27	68		T30	150		T31	332
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	3715254	1			T26	433		T27	113		T28	1
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2961853	1			T26	395		T27	16		T30	274
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	957183	1			T27	46		T30	164		T31	353
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1121993	1			T27	228		T31	508		T32	1507
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	390688	1			T27	30		T30	143		T31	38
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	950530	1			T27	104		T30	160		T31	536
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	3717839	1			T26	381		T27	182		T28	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2963824	1			T26	447		T27	27		T30	228
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	951543	1			T27	67		T30	182		T31	406
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1126374	1			T27	187		T31	505		T32	1520
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	391750	1			T27	20		T30	178		T31	27
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	946171	1			T27	54		T30	162		T31	383
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	3726744	1			T26	447		T27	184		T28	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2960084	1			T26	381		T27	19		T30	209
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	948551	1			T27	83		T30	192		T31	351
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1127864	1			T27	157		T31	552		T32	1427
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	388095	1			T27	15		T30	171		T31	26
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	946163	1			T27	79		T30	172		T31	439
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	3736482	1			T26	371		T27	182		T28	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2952067	1			T26	457		T27	32		T30	274
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	952461	1			T27	86		T30	124		T31	383
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1124409	1			T27	158		T31	495		T32	1508
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	390882	1			T27	15		T30	195		T31	19
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	941200	1			T27	64		T30	152		T31	279
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	3724114	1			T26	421		T27	209		T28	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2960234	1			T26	407		T27	27		T30	291
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	951146	1			T27	54		T30	136		T31	423
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1128226	1			T27	161		T31	443		T32	1411
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	391205	1			T27	15		T30	170		T31	18
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	942576	1			T27	71		T30	165		T31	343
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	3717529	1			T26	383		T27	221		T28	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2963139	1			T26	445		T27	36		T30	255
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	951269	1			T27	98		T30	165		T31	362
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1127313	1			T27	130		T31	619		T32	1510
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	392452	1			T27	10		T30	144		T31	25
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	945799	1			T27	42		T30	188		T31	351
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	3723125	1			T26	441		T27	184		T28	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2959619	1			T26	387		T27	22		T30	229
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	953539	1			T27	61		T30	152		T31	346
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1124532	1			T27	177		T31	589		T32	1467
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	389739	1			T27	24		T30	162		T31	41
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	946947	1			T27	69		T30	201		T31	391
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	3709444	1			T26	473		T27	136		T28	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2973474	1			T26	355		T27	18		T30	231
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	957189	1			T27	32		T30	153		T31	357
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1123737	1			T27	242		T31	533		T32	1486
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	390749	1			T27	21		T30	208		T31	13
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	942908	1			T27	88		T30	160		T31	358
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	3714132	1			T26	364		T27	264		T28	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2967694	1			T26	464		T27	37		T30	250
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	959657	1			T27	52		T30	174		T31	459
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1123321	1			T27	117		T31	487		T32	1473
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	390003	1			T27	11		T30	165		T31	35
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	942694	1			T27	56		T30	162		T31	379
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	3726241	1			T26	425		T27	195		T28	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2964870	1			T26	403		T27	14		T30	277
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	953193	1			T27	65		T30	158		T31	276
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1120789	1			T27	160		T31	588		T32	1701
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	391516	1			T27	30		T30	149		T31	9
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	940892	1			T27	73		T30	182		T31	451
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	3725874	1			T26	467		T27	199		T28	1
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2961342	1			T26	361		T27	15		T30	246
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	955260	1			T27	60		T30	180		T31	366
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1121669	1			T27	147		T31	483		T32	1438
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	390604	1			T27	22		T30	172		T31	21
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	942752	1			T27	94		T30	156		T31	379
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	3713945	1			T26	391		T27	118		T28	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2969378	1			T26	437		T27	12		T30	232
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	952974	1			T27	75		T30	152		T31	392
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1120948	1			T27	241		T31	491		T32	1463
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	393107	1			T27	32		T30	192		T31	33
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	947149	1			T27	59		T30	180		T31	308
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	3725379	1			T26	407		T27	195		T28	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2954373	1			T26	421		T27	21		T30	271
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	950025	1			T27	105		T30	157		T31	442
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1131370	1			T27	122		T31	496		T32	1563
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	392331	1			T27	24		T30	164		T31	44
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	944023	1			T27	70		T30	172		T31	429
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	3719461	1			T26	447		T27	174		T28	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2962629	1			T26	381		T27	10		T30	272
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	956280	1			T27	95		T30	180		T31	389
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1122094	1			T27	147		T31	484		T32	1447
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	389850	1			T27	39		T30	148		T31	18
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	947187	1			T27	72		T30	148		T31	353
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	3719776	1			T26	465		T27	144		T28	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2964474	1			T26	363		T27	17		T30	247
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	949156	1			T27	76		T30	172		T31	384
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1130752	1			T27	175		T31	580		T32	1521
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	390626	1			T27	22		T30	162		T31	26
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	942717	1			T27	103		T30	165		T31	388
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	3718753	1			T26	396		T27	192		T28	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2963615	1			T26	432		T27	10		T30	250
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	955592	1			T27	105		T30	150		T31	302
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1122962	1			T27	161		T31	458		T32	1497
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	390675	1			T27	17		T30	186		T31	35
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	945904	1			T27	52		T30	162		T31	429
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	3724710	1			T26	440		T27	211		T28	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2961843	1			T26	388		T27	30		T30	262
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	958209	1			T27	118		T30	146		T31	318
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1119322	1			T27	120		T31	586		T32	1533
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	389860	1			T27	8		T30	184		T31	27
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	943557	1			T27	50		T30	155		T31	274

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal