Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[1]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[2]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[3]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[4]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[5]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[6]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[7]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[8]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[9]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[10]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[11]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[12]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[13]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[14]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[15]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[16]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[17]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[18]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[19]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[20]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[21]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[22]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[23]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[24]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[25]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[26]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[27]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[28]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[29]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[30]	10097501	1			T26	828		T27	537		T28	1
bins_for_gpio_bits[31]	10097501	1			T26	828		T27	537		T28	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

185467393

1

T26

13251

T27

13512

T28

32

auto[1]

137652639

1

T26

13245

T27

3672

T30

18689

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

185461522

1

T26

13251

T27

13502

T28

32

auto[1]

137658510

1

T26

13245

T27

3682

T30

18678

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	5609528	1			T26	433		T27	397		T28	1
bins_for_gpio_bits[0]	auto[0]	auto[1]	171711	1			T27	12		T30	41		T31	55
bins_for_gpio_bits[0]	auto[1]	auto[0]	171890	1			T27	12		T30	41		T31	55
bins_for_gpio_bits[0]	auto[1]	auto[1]	4144372	1			T26	395		T27	116		T30	550
bins_for_gpio_bits[1]	auto[0]	auto[0]	5613126	1			T26	420		T27	398		T28	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	170896	1			T27	15		T30	44		T31	60
bins_for_gpio_bits[1]	auto[1]	auto[0]	171106	1			T27	16		T30	43		T31	60
bins_for_gpio_bits[1]	auto[1]	auto[1]	4142373	1			T26	408		T27	108		T30	537
bins_for_gpio_bits[2]	auto[0]	auto[0]	5620420	1			T26	377		T27	402		T28	1
bins_for_gpio_bits[2]	auto[0]	auto[1]	170890	1			T27	15		T30	40		T31	60
bins_for_gpio_bits[2]	auto[1]	auto[0]	171036	1			T27	15		T30	39		T31	60
bins_for_gpio_bits[2]	auto[1]	auto[1]	4135155	1			T26	451		T27	105		T30	565
bins_for_gpio_bits[3]	auto[0]	auto[0]	5629398	1			T26	391		T27	451		T28	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	171155	1			T27	8		T30	38		T31	51
bins_for_gpio_bits[3]	auto[1]	auto[0]	171324	1			T27	8		T30	38		T31	51
bins_for_gpio_bits[3]	auto[1]	auto[1]	4125624	1			T26	437		T27	70		T30	566
bins_for_gpio_bits[4]	auto[0]	auto[0]	5626936	1			T26	404		T27	373		T28	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	171497	1			T27	15		T30	46		T31	54
bins_for_gpio_bits[4]	auto[1]	auto[0]	171638	1			T27	16		T30	45		T31	54
bins_for_gpio_bits[4]	auto[1]	auto[1]	4127430	1			T26	424		T27	133		T30	514
bins_for_gpio_bits[5]	auto[0]	auto[0]	5615890	1			T26	364		T27	417		T28	1
bins_for_gpio_bits[5]	auto[0]	auto[1]	171076	1			T27	11		T30	36		T31	64
bins_for_gpio_bits[5]	auto[1]	auto[0]	171281	1			T27	11		T30	36		T31	64
bins_for_gpio_bits[5]	auto[1]	auto[1]	4139254	1			T26	464		T27	98		T30	556
bins_for_gpio_bits[6]	auto[0]	auto[0]	5621032	1			T26	477		T27	400		T28	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	171006	1			T27	11		T30	45		T31	56
bins_for_gpio_bits[6]	auto[1]	auto[0]	171222	1			T27	11		T30	45		T31	56
bins_for_gpio_bits[6]	auto[1]	auto[1]	4134241	1			T26	351		T27	115		T30	539
bins_for_gpio_bits[7]	auto[0]	auto[0]	5629744	1			T26	409		T27	442		T28	1
bins_for_gpio_bits[7]	auto[0]	auto[1]	170494	1			T27	9		T30	45		T31	58
bins_for_gpio_bits[7]	auto[1]	auto[0]	170669	1			T27	9		T30	44		T31	58
bins_for_gpio_bits[7]	auto[1]	auto[1]	4126594	1			T26	419		T27	77		T30	497
bins_for_gpio_bits[8]	auto[0]	auto[0]	5623497	1			T26	336		T27	423		T28	1
bins_for_gpio_bits[8]	auto[0]	auto[1]	170569	1			T27	11		T30	40		T31	62
bins_for_gpio_bits[8]	auto[1]	auto[0]	170730	1			T27	12		T30	39		T31	62
bins_for_gpio_bits[8]	auto[1]	auto[1]	4132705	1			T26	492		T27	91		T30	518
bins_for_gpio_bits[9]	auto[0]	auto[0]	5619222	1			T26	367		T27	357		T28	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	171155	1			T27	21		T30	48		T31	53
bins_for_gpio_bits[9]	auto[1]	auto[0]	171307	1			T27	22		T30	47		T31	53
bins_for_gpio_bits[9]	auto[1]	auto[1]	4135817	1			T26	461		T27	137		T30	506
bins_for_gpio_bits[10]	auto[0]	auto[0]	5620796	1			T26	420		T27	392		T28	1
bins_for_gpio_bits[10]	auto[0]	auto[1]	170309	1			T27	15		T30	46		T31	56
bins_for_gpio_bits[10]	auto[1]	auto[0]	170509	1			T27	15		T30	45		T31	56
bins_for_gpio_bits[10]	auto[1]	auto[1]	4135887	1			T26	408		T27	115		T30	520
bins_for_gpio_bits[11]	auto[0]	auto[0]	5617194	1			T26	416		T27	422		T28	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	170700	1			T27	14		T30	50		T31	57
bins_for_gpio_bits[11]	auto[1]	auto[0]	170823	1			T27	14		T30	50		T31	57
bins_for_gpio_bits[11]	auto[1]	auto[1]	4138784	1			T26	412		T27	87		T30	538
bins_for_gpio_bits[12]	auto[0]	auto[0]	5617903	1			T26	424		T27	455		T28	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	171016	1			T27	8		T30	41		T31	68
bins_for_gpio_bits[12]	auto[1]	auto[0]	171193	1			T27	8		T30	41		T31	68
bins_for_gpio_bits[12]	auto[1]	auto[1]	4137389	1			T26	404		T27	66		T30	539
bins_for_gpio_bits[13]	auto[0]	auto[0]	5620953	1			T26	429		T27	369		T28	1
bins_for_gpio_bits[13]	auto[0]	auto[1]	170662	1			T27	17		T30	43		T31	52
bins_for_gpio_bits[13]	auto[1]	auto[0]	170851	1			T27	17		T30	43		T31	52
bins_for_gpio_bits[13]	auto[1]	auto[1]	4135035	1			T26	399		T27	134		T30	551
bins_for_gpio_bits[14]	auto[0]	auto[0]	5625246	1			T26	432		T27	403		T28	1
bins_for_gpio_bits[14]	auto[0]	auto[1]	171064	1			T27	13		T30	48		T31	48
bins_for_gpio_bits[14]	auto[1]	auto[0]	171225	1			T27	14		T30	47		T31	48
bins_for_gpio_bits[14]	auto[1]	auto[1]	4129966	1			T26	396		T27	107		T30	509
bins_for_gpio_bits[15]	auto[0]	auto[0]	5622814	1			T26	433		T27	371		T28	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	171424	1			T27	16		T30	43		T31	67
bins_for_gpio_bits[15]	auto[1]	auto[0]	171616	1			T27	16		T30	43		T31	67
bins_for_gpio_bits[15]	auto[1]	auto[1]	4131647	1			T26	395		T27	134		T30	534
bins_for_gpio_bits[16]	auto[0]	auto[0]	5624849	1			T26	381		T27	428		T28	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	170711	1			T27	7		T30	41		T31	53
bins_for_gpio_bits[16]	auto[1]	auto[0]	170907	1			T27	8		T30	41		T31	53
bins_for_gpio_bits[16]	auto[1]	auto[1]	4131034	1			T26	447		T27	94		T30	527
bins_for_gpio_bits[17]	auto[0]	auto[0]	5631829	1			T26	447		T27	409		T28	1
bins_for_gpio_bits[17]	auto[0]	auto[1]	171149	1			T27	15		T30	37		T31	65
bins_for_gpio_bits[17]	auto[1]	auto[0]	171330	1			T27	15		T30	37		T31	65
bins_for_gpio_bits[17]	auto[1]	auto[1]	4123193	1			T26	381		T27	98		T30	515
bins_for_gpio_bits[18]	auto[0]	auto[0]	5643210	1			T26	371		T27	414		T28	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	169955	1			T27	11		T30	32		T31	48
bins_for_gpio_bits[18]	auto[1]	auto[0]	170142	1			T27	12		T30	32		T31	48
bins_for_gpio_bits[18]	auto[1]	auto[1]	4114194	1			T26	457		T27	100		T30	589
bins_for_gpio_bits[19]	auto[0]	auto[0]	5632542	1			T26	421		T27	410		T28	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	170751	1			T27	14		T30	34		T31	53
bins_for_gpio_bits[19]	auto[1]	auto[0]	170944	1			T27	14		T30	34		T31	53
bins_for_gpio_bits[19]	auto[1]	auto[1]	4123264	1			T26	407		T27	99		T30	592
bins_for_gpio_bits[20]	auto[0]	auto[0]	5625135	1			T26	383		T27	440		T28	1
bins_for_gpio_bits[20]	auto[0]	auto[1]	170775	1			T27	8		T30	44		T31	50
bins_for_gpio_bits[20]	auto[1]	auto[0]	170976	1			T27	9		T30	43		T31	50
bins_for_gpio_bits[20]	auto[1]	auto[1]	4130615	1			T26	445		T27	80		T30	543
bins_for_gpio_bits[21]	auto[0]	auto[0]	5630403	1			T26	441		T27	414		T28	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	170629	1			T27	8		T30	35		T31	64
bins_for_gpio_bits[21]	auto[1]	auto[0]	170793	1			T27	8		T30	35		T31	64
bins_for_gpio_bits[21]	auto[1]	auto[1]	4125676	1			T26	387		T27	107		T30	557
bins_for_gpio_bits[22]	auto[0]	auto[0]	5619311	1			T26	473		T27	393		T28	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	170850	1			T27	16		T30	38		T31	50
bins_for_gpio_bits[22]	auto[1]	auto[0]	171059	1			T27	17		T30	37		T31	50
bins_for_gpio_bits[22]	auto[1]	auto[1]	4136281	1			T26	355		T27	111		T30	561
bins_for_gpio_bits[23]	auto[0]	auto[0]	5626135	1			T26	364		T27	422		T28	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	170780	1			T27	11		T30	39		T31	55
bins_for_gpio_bits[23]	auto[1]	auto[0]	170975	1			T27	11		T30	39		T31	55
bins_for_gpio_bits[23]	auto[1]	auto[1]	4129611	1			T26	464		T27	93		T30	538
bins_for_gpio_bits[24]	auto[0]	auto[0]	5629775	1			T26	425		T27	410		T28	1
bins_for_gpio_bits[24]	auto[0]	auto[1]	170257	1			T27	10		T30	46		T31	56
bins_for_gpio_bits[24]	auto[1]	auto[0]	170448	1			T27	10		T30	46		T31	56
bins_for_gpio_bits[24]	auto[1]	auto[1]	4127021	1			T26	403		T27	107		T30	562
bins_for_gpio_bits[25]	auto[0]	auto[0]	5632140	1			T26	467		T27	392		T28	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	170436	1			T27	14		T30	42		T31	55
bins_for_gpio_bits[25]	auto[1]	auto[0]	170663	1			T27	14		T30	42		T31	55
bins_for_gpio_bits[25]	auto[1]	auto[1]	4124262	1			T26	361		T27	117		T30	532
bins_for_gpio_bits[26]	auto[0]	auto[0]	5616845	1			T26	391		T27	419		T28	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	170864	1			T27	15		T30	41		T31	43
bins_for_gpio_bits[26]	auto[1]	auto[0]	171022	1			T27	15		T30	41		T31	43
bins_for_gpio_bits[26]	auto[1]	auto[1]	4138770	1			T26	437		T27	88		T30	563
bins_for_gpio_bits[27]	auto[0]	auto[0]	5635867	1			T26	407		T27	409		T28	1
bins_for_gpio_bits[27]	auto[0]	auto[1]	170681	1			T27	13		T30	46		T31	59
bins_for_gpio_bits[27]	auto[1]	auto[0]	170907	1			T27	13		T30	45		T31	59
bins_for_gpio_bits[27]	auto[1]	auto[1]	4120046	1			T26	421		T27	102		T30	561
bins_for_gpio_bits[28]	auto[0]	auto[0]	5626665	1			T26	447		T27	398		T28	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	170994	1			T27	18		T30	48		T31	56
bins_for_gpio_bits[28]	auto[1]	auto[0]	171170	1			T27	18		T30	48		T31	56
bins_for_gpio_bits[28]	auto[1]	auto[1]	4128672	1			T26	381		T27	103		T30	520
bins_for_gpio_bits[29]	auto[0]	auto[0]	5628970	1			T26	465		T27	379		T28	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	170534	1			T27	15		T30	49		T31	54
bins_for_gpio_bits[29]	auto[1]	auto[0]	170714	1			T27	16		T30	49		T31	54
bins_for_gpio_bits[29]	auto[1]	auto[1]	4127283	1			T26	363		T27	127		T30	525
bins_for_gpio_bits[30]	auto[0]	auto[0]	5625953	1			T26	396		T27	448		T28	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	171167	1			T27	10		T30	39		T31	57
bins_for_gpio_bits[30]	auto[1]	auto[0]	171354	1			T27	10		T30	39		T31	57
bins_for_gpio_bits[30]	auto[1]	auto[1]	4129027	1			T26	432		T27	69		T30	559
bins_for_gpio_bits[31]	auto[0]	auto[0]	5631412	1			T26	440		T27	439		T28	1
bins_for_gpio_bits[31]	auto[0]	auto[1]	170625	1			T27	10		T30	42		T31	44
bins_for_gpio_bits[31]	auto[1]	auto[0]	170829	1			T27	10		T30	42		T31	44
bins_for_gpio_bits[31]	auto[1]	auto[1]	4124635	1			T26	388		T27	78		T30	559