Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6166438 |
1 |
|
|
T26 |
828 |
|
T27 |
283 |
|
T28 |
1 |
| auto[1] |
4014977 |
1 |
|
|
T31 |
1137 |
|
T32 |
52941 |
|
T33 |
403 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9675069 |
1 |
|
|
T26 |
828 |
|
T27 |
283 |
|
T28 |
1 |
| auto[1] |
506346 |
1 |
|
|
T31 |
29 |
|
T32 |
6359 |
|
T33 |
20 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6209589 |
1 |
|
|
T26 |
828 |
|
T27 |
283 |
|
T28 |
1 |
| auto[1] |
3971826 |
1 |
|
|
T31 |
752 |
|
T32 |
51641 |
|
T33 |
431 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1737201 |
1 |
|
|
T31 |
217 |
|
T32 |
22689 |
|
T33 |
182 |
| auto[1] |
auto[0] |
auto[1] |
253875 |
1 |
|
|
T31 |
9 |
|
T32 |
3195 |
|
T33 |
8 |
| auto[1] |
auto[1] |
auto[0] |
1728279 |
1 |
|
|
T31 |
506 |
|
T32 |
22593 |
|
T33 |
229 |
| auto[1] |
auto[1] |
auto[1] |
252471 |
1 |
|
|
T31 |
20 |
|
T32 |
3164 |
|
T33 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |