Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6223400 |
1 |
|
|
T26 |
828 |
|
T27 |
283 |
|
T28 |
1 |
| auto[1] |
3958015 |
1 |
|
|
T31 |
1069 |
|
T32 |
53231 |
|
T33 |
492 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8477773 |
1 |
|
|
T26 |
828 |
|
T27 |
283 |
|
T28 |
1 |
| auto[1] |
1703642 |
1 |
|
|
T31 |
212 |
|
T32 |
32304 |
|
T33 |
408 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6188238 |
1 |
|
|
T26 |
828 |
|
T27 |
283 |
|
T28 |
1 |
| auto[1] |
3993177 |
1 |
|
|
T31 |
1125 |
|
T32 |
52347 |
|
T33 |
583 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1155217 |
1 |
|
|
T31 |
405 |
|
T32 |
9408 |
|
T33 |
91 |
| auto[1] |
auto[0] |
auto[1] |
861745 |
1 |
|
|
T31 |
85 |
|
T32 |
15707 |
|
T33 |
219 |
| auto[1] |
auto[1] |
auto[0] |
1134318 |
1 |
|
|
T31 |
508 |
|
T32 |
10635 |
|
T33 |
84 |
| auto[1] |
auto[1] |
auto[1] |
841897 |
1 |
|
|
T31 |
127 |
|
T32 |
16597 |
|
T33 |
189 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |