Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6194138 |
1 |
|
|
T26 |
828 |
|
T27 |
283 |
|
T28 |
1 |
| auto[1] |
3987277 |
1 |
|
|
T31 |
914 |
|
T32 |
53037 |
|
T33 |
520 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8485443 |
1 |
|
|
T26 |
828 |
|
T27 |
283 |
|
T28 |
1 |
| auto[1] |
1695972 |
1 |
|
|
T31 |
269 |
|
T32 |
31378 |
|
T33 |
301 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6207644 |
1 |
|
|
T26 |
828 |
|
T27 |
283 |
|
T28 |
1 |
| auto[1] |
3973771 |
1 |
|
|
T31 |
925 |
|
T32 |
50447 |
|
T33 |
373 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1139422 |
1 |
|
|
T31 |
389 |
|
T32 |
9457 |
|
T33 |
41 |
| auto[1] |
auto[0] |
auto[1] |
850555 |
1 |
|
|
T31 |
113 |
|
T32 |
14897 |
|
T33 |
114 |
| auto[1] |
auto[1] |
auto[0] |
1138377 |
1 |
|
|
T31 |
267 |
|
T32 |
9612 |
|
T33 |
31 |
| auto[1] |
auto[1] |
auto[1] |
845417 |
1 |
|
|
T31 |
156 |
|
T32 |
16481 |
|
T33 |
187 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |