Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6204053 |
1 |
|
|
T26 |
828 |
|
T27 |
283 |
|
T28 |
1 |
| auto[1] |
3977362 |
1 |
|
|
T31 |
1129 |
|
T32 |
51379 |
|
T33 |
620 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9671966 |
1 |
|
|
T26 |
828 |
|
T27 |
283 |
|
T28 |
1 |
| auto[1] |
509449 |
1 |
|
|
T31 |
49 |
|
T32 |
6391 |
|
T33 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6184671 |
1 |
|
|
T26 |
828 |
|
T27 |
283 |
|
T28 |
1 |
| auto[1] |
3996744 |
1 |
|
|
T31 |
1090 |
|
T32 |
52949 |
|
T33 |
488 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1746473 |
1 |
|
|
T31 |
445 |
|
T32 |
23412 |
|
T33 |
181 |
| auto[1] |
auto[0] |
auto[1] |
255006 |
1 |
|
|
T31 |
20 |
|
T32 |
3303 |
|
T33 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1740822 |
1 |
|
|
T31 |
596 |
|
T32 |
23146 |
|
T33 |
295 |
| auto[1] |
auto[1] |
auto[1] |
254443 |
1 |
|
|
T31 |
29 |
|
T32 |
3088 |
|
T33 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |