Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 934
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T107 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.552870131 Mar 21 02:34:21 PM PDT 24 Mar 21 02:34:22 PM PDT 24 34405208 ps
T764 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3182801250 Mar 21 02:34:50 PM PDT 24 Mar 21 02:34:51 PM PDT 24 15776270 ps
T108 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3412488133 Mar 21 02:33:53 PM PDT 24 Mar 21 02:33:54 PM PDT 24 61891106 ps
T765 /workspace/coverage/cover_reg_top/12.gpio_intr_test.3012509588 Mar 21 02:34:19 PM PDT 24 Mar 21 02:34:20 PM PDT 24 18629023 ps
T766 /workspace/coverage/cover_reg_top/41.gpio_intr_test.340754973 Mar 21 02:34:51 PM PDT 24 Mar 21 02:34:52 PM PDT 24 15776291 ps
T767 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3594899454 Mar 21 02:34:05 PM PDT 24 Mar 21 02:34:07 PM PDT 24 211943970 ps
T768 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1803423121 Mar 21 02:33:52 PM PDT 24 Mar 21 02:33:53 PM PDT 24 29694644 ps
T53 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1811917786 Mar 21 02:34:07 PM PDT 24 Mar 21 02:34:10 PM PDT 24 41746469 ps
T769 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1419362192 Mar 21 02:34:06 PM PDT 24 Mar 21 02:34:10 PM PDT 24 327101613 ps
T770 /workspace/coverage/cover_reg_top/43.gpio_intr_test.487893265 Mar 21 02:34:49 PM PDT 24 Mar 21 02:34:50 PM PDT 24 11382099 ps
T771 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3952545732 Mar 21 02:34:05 PM PDT 24 Mar 21 02:34:06 PM PDT 24 54371527 ps
T772 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2290274012 Mar 21 02:33:52 PM PDT 24 Mar 21 02:33:54 PM PDT 24 52588933 ps
T773 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1015840700 Mar 21 02:34:03 PM PDT 24 Mar 21 02:34:03 PM PDT 24 105132046 ps
T774 /workspace/coverage/cover_reg_top/26.gpio_intr_test.941530632 Mar 21 02:34:41 PM PDT 24 Mar 21 02:34:45 PM PDT 24 46827568 ps
T775 /workspace/coverage/cover_reg_top/33.gpio_intr_test.846335694 Mar 21 02:34:35 PM PDT 24 Mar 21 02:34:36 PM PDT 24 56896558 ps
T776 /workspace/coverage/cover_reg_top/21.gpio_intr_test.2035959971 Mar 21 02:34:41 PM PDT 24 Mar 21 02:34:46 PM PDT 24 14073293 ps
T777 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.763231312 Mar 21 02:34:20 PM PDT 24 Mar 21 02:34:21 PM PDT 24 137841519 ps
T778 /workspace/coverage/cover_reg_top/44.gpio_intr_test.3662003844 Mar 21 02:34:48 PM PDT 24 Mar 21 02:34:49 PM PDT 24 40106991 ps
T779 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2886336271 Mar 21 02:33:57 PM PDT 24 Mar 21 02:33:57 PM PDT 24 19124915 ps
T780 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1196434324 Mar 21 02:34:20 PM PDT 24 Mar 21 02:34:21 PM PDT 24 28494880 ps
T781 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2575886935 Mar 21 02:34:05 PM PDT 24 Mar 21 02:34:07 PM PDT 24 68673405 ps
T111 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3595426180 Mar 21 02:34:18 PM PDT 24 Mar 21 02:34:19 PM PDT 24 50383184 ps
T782 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1420000686 Mar 21 02:34:41 PM PDT 24 Mar 21 02:34:45 PM PDT 24 148631892 ps
T783 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3056528761 Mar 21 02:34:35 PM PDT 24 Mar 21 02:34:35 PM PDT 24 29481100 ps
T99 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.456988920 Mar 21 02:33:54 PM PDT 24 Mar 21 02:33:55 PM PDT 24 580930459 ps
T784 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1087270121 Mar 21 02:34:50 PM PDT 24 Mar 21 02:34:51 PM PDT 24 46237228 ps
T785 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1819769234 Mar 21 02:34:21 PM PDT 24 Mar 21 02:34:23 PM PDT 24 94212919 ps
T786 /workspace/coverage/cover_reg_top/16.gpio_intr_test.4291172002 Mar 21 02:34:37 PM PDT 24 Mar 21 02:34:38 PM PDT 24 12246855 ps
T93 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.4153931125 Mar 21 02:34:07 PM PDT 24 Mar 21 02:34:10 PM PDT 24 27266511 ps
T787 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1191861886 Mar 21 02:34:19 PM PDT 24 Mar 21 02:34:20 PM PDT 24 43453609 ps
T788 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.819389250 Mar 21 02:34:19 PM PDT 24 Mar 21 02:34:20 PM PDT 24 67974112 ps
T789 /workspace/coverage/cover_reg_top/2.gpio_intr_test.1975079194 Mar 21 02:34:06 PM PDT 24 Mar 21 02:34:08 PM PDT 24 16684000 ps
T790 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.4158422552 Mar 21 02:34:04 PM PDT 24 Mar 21 02:34:05 PM PDT 24 32236619 ps
T791 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.739278301 Mar 21 02:33:54 PM PDT 24 Mar 21 02:33:55 PM PDT 24 16947151 ps
T792 /workspace/coverage/cover_reg_top/37.gpio_intr_test.45905700 Mar 21 02:34:49 PM PDT 24 Mar 21 02:34:50 PM PDT 24 21374744 ps
T52 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1813297651 Mar 21 02:34:19 PM PDT 24 Mar 21 02:34:20 PM PDT 24 234576837 ps
T793 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4149105926 Mar 21 02:34:08 PM PDT 24 Mar 21 02:34:11 PM PDT 24 578957396 ps
T794 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1480193212 Mar 21 02:34:20 PM PDT 24 Mar 21 02:34:22 PM PDT 24 344911407 ps
T795 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.4216334374 Mar 21 02:33:53 PM PDT 24 Mar 21 02:33:54 PM PDT 24 27624366 ps
T796 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2821055446 Mar 21 02:34:05 PM PDT 24 Mar 21 02:34:06 PM PDT 24 27176929 ps
T797 /workspace/coverage/cover_reg_top/48.gpio_intr_test.116662542 Mar 21 02:34:50 PM PDT 24 Mar 21 02:34:50 PM PDT 24 13774049 ps
T798 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.4172810745 Mar 21 02:34:19 PM PDT 24 Mar 21 02:34:20 PM PDT 24 112533519 ps
T799 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2152549399 Mar 21 02:34:18 PM PDT 24 Mar 21 02:34:19 PM PDT 24 11939432 ps
T800 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1435751856 Mar 21 02:34:23 PM PDT 24 Mar 21 02:34:25 PM PDT 24 34364037 ps
T801 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2080687801 Mar 21 02:34:19 PM PDT 24 Mar 21 02:34:20 PM PDT 24 57848667 ps
T802 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2644175659 Mar 21 02:34:34 PM PDT 24 Mar 21 02:34:35 PM PDT 24 24935626 ps
T50 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3912035465 Mar 21 02:33:55 PM PDT 24 Mar 21 02:33:56 PM PDT 24 83666046 ps
T803 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.210391293 Mar 21 02:34:05 PM PDT 24 Mar 21 02:34:08 PM PDT 24 166047067 ps
T804 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3777704285 Mar 21 02:34:34 PM PDT 24 Mar 21 02:34:35 PM PDT 24 51135858 ps
T805 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3983595488 Mar 21 02:34:06 PM PDT 24 Mar 21 02:34:08 PM PDT 24 110754256 ps
T806 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3958696817 Mar 21 02:34:34 PM PDT 24 Mar 21 02:34:35 PM PDT 24 278458474 ps
T807 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2273878403 Mar 21 02:34:50 PM PDT 24 Mar 21 02:34:51 PM PDT 24 15134854 ps
T808 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.854293820 Mar 21 02:34:21 PM PDT 24 Mar 21 02:34:25 PM PDT 24 631908286 ps
T809 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2960995761 Mar 21 02:34:37 PM PDT 24 Mar 21 02:34:38 PM PDT 24 19206180 ps
T810 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2122116608 Mar 21 02:34:20 PM PDT 24 Mar 21 02:34:21 PM PDT 24 20315608 ps
T811 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3772632258 Mar 21 02:34:40 PM PDT 24 Mar 21 02:34:41 PM PDT 24 29521951 ps
T812 /workspace/coverage/cover_reg_top/19.gpio_intr_test.2151465351 Mar 21 02:34:35 PM PDT 24 Mar 21 02:34:36 PM PDT 24 29718400 ps
T813 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1951689123 Mar 21 02:34:19 PM PDT 24 Mar 21 02:34:20 PM PDT 24 59673011 ps
T814 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3136191204 Mar 21 02:34:36 PM PDT 24 Mar 21 02:34:37 PM PDT 24 44228486 ps
T815 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2319660104 Mar 21 02:34:19 PM PDT 24 Mar 21 02:34:20 PM PDT 24 156895171 ps
T816 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1160817184 Mar 21 02:34:08 PM PDT 24 Mar 21 02:34:11 PM PDT 24 50138950 ps
T94 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2975569865 Mar 21 02:34:19 PM PDT 24 Mar 21 02:34:20 PM PDT 24 32832720 ps
T817 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1632748847 Mar 21 02:34:23 PM PDT 24 Mar 21 02:34:25 PM PDT 24 361722309 ps
T95 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.833712722 Mar 21 02:34:06 PM PDT 24 Mar 21 02:34:08 PM PDT 24 114631153 ps
T96 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3512776353 Mar 21 02:33:55 PM PDT 24 Mar 21 02:33:56 PM PDT 24 88926379 ps
T818 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.477530370 Mar 21 02:34:37 PM PDT 24 Mar 21 02:34:39 PM PDT 24 167345277 ps
T98 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3844174737 Mar 21 02:33:56 PM PDT 24 Mar 21 02:33:59 PM PDT 24 1490013069 ps
T819 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.601806306 Mar 21 02:34:34 PM PDT 24 Mar 21 02:34:35 PM PDT 24 53179090 ps
T820 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2898461862 Mar 21 02:34:19 PM PDT 24 Mar 21 02:34:20 PM PDT 24 45018355 ps
T821 /workspace/coverage/cover_reg_top/23.gpio_intr_test.3214262831 Mar 21 02:34:37 PM PDT 24 Mar 21 02:34:37 PM PDT 24 13429002 ps
T822 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1666868596 Mar 21 02:34:18 PM PDT 24 Mar 21 02:34:19 PM PDT 24 17236849 ps
T823 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1971038420 Mar 21 02:34:20 PM PDT 24 Mar 21 02:34:21 PM PDT 24 43483983 ps
T824 /workspace/coverage/cover_reg_top/17.gpio_intr_test.1599231557 Mar 21 02:34:34 PM PDT 24 Mar 21 02:34:35 PM PDT 24 23047914 ps
T825 /workspace/coverage/cover_reg_top/8.gpio_intr_test.43908760 Mar 21 02:34:18 PM PDT 24 Mar 21 02:34:19 PM PDT 24 59698823 ps
T826 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1764037184 Mar 21 02:34:39 PM PDT 24 Mar 21 02:34:41 PM PDT 24 15764400 ps
T827 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.227390993 Mar 21 02:34:40 PM PDT 24 Mar 21 02:34:41 PM PDT 24 130453532 ps
T828 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.4199641734 Mar 21 02:34:21 PM PDT 24 Mar 21 02:34:22 PM PDT 24 17429454 ps
T829 /workspace/coverage/cover_reg_top/34.gpio_intr_test.2543557633 Mar 21 02:34:40 PM PDT 24 Mar 21 02:34:41 PM PDT 24 20535358 ps
T830 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.60514570 Mar 21 02:34:37 PM PDT 24 Mar 21 02:34:38 PM PDT 24 249090194 ps
T100 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.642323730 Mar 21 02:34:32 PM PDT 24 Mar 21 02:34:33 PM PDT 24 33644105 ps
T831 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3567068481 Mar 21 02:34:40 PM PDT 24 Mar 21 02:34:41 PM PDT 24 42763004 ps
T832 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2653335313 Mar 21 02:34:19 PM PDT 24 Mar 21 02:34:19 PM PDT 24 20723951 ps
T833 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.213281566 Mar 21 02:34:37 PM PDT 24 Mar 21 02:34:38 PM PDT 24 14196392 ps
T834 /workspace/coverage/cover_reg_top/9.gpio_intr_test.2469812886 Mar 21 02:34:24 PM PDT 24 Mar 21 02:34:24 PM PDT 24 88866603 ps
T835 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1193072072 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:57 PM PDT 24 93796638 ps
T836 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1064349595 Mar 21 02:35:58 PM PDT 24 Mar 21 02:35:59 PM PDT 24 165776949 ps
T837 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4294356219 Mar 21 02:35:55 PM PDT 24 Mar 21 02:35:57 PM PDT 24 34949822 ps
T838 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2735918225 Mar 21 02:35:41 PM PDT 24 Mar 21 02:35:42 PM PDT 24 197691225 ps
T839 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3272355590 Mar 21 02:35:43 PM PDT 24 Mar 21 02:35:44 PM PDT 24 77544418 ps
T840 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.248226213 Mar 21 02:36:07 PM PDT 24 Mar 21 02:36:09 PM PDT 24 181314525 ps
T841 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.4117892442 Mar 21 02:35:43 PM PDT 24 Mar 21 02:35:44 PM PDT 24 151908289 ps
T842 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3359438868 Mar 21 02:35:44 PM PDT 24 Mar 21 02:35:46 PM PDT 24 59460649 ps
T843 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1554375317 Mar 21 02:35:59 PM PDT 24 Mar 21 02:36:01 PM PDT 24 58381769 ps
T844 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1265980473 Mar 21 02:35:43 PM PDT 24 Mar 21 02:35:44 PM PDT 24 38685170 ps
T845 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4007784236 Mar 21 02:36:01 PM PDT 24 Mar 21 02:36:02 PM PDT 24 48117447 ps
T846 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.538657309 Mar 21 02:35:44 PM PDT 24 Mar 21 02:35:45 PM PDT 24 49398013 ps
T847 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.886356091 Mar 21 02:35:45 PM PDT 24 Mar 21 02:35:46 PM PDT 24 112376211 ps
T848 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3640439509 Mar 21 02:36:00 PM PDT 24 Mar 21 02:36:01 PM PDT 24 51275213 ps
T849 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4060190319 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:58 PM PDT 24 46893215 ps
T850 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.849009045 Mar 21 02:35:59 PM PDT 24 Mar 21 02:36:00 PM PDT 24 76479964 ps
T851 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3201551488 Mar 21 02:35:54 PM PDT 24 Mar 21 02:35:55 PM PDT 24 411777223 ps
T852 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.229591808 Mar 21 02:36:01 PM PDT 24 Mar 21 02:36:03 PM PDT 24 37435716 ps
T853 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4192403109 Mar 21 02:35:45 PM PDT 24 Mar 21 02:35:46 PM PDT 24 76568635 ps
T854 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.4178103226 Mar 21 02:35:55 PM PDT 24 Mar 21 02:35:56 PM PDT 24 67821556 ps
T855 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2712495363 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:57 PM PDT 24 75117043 ps
T856 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3248237817 Mar 21 02:35:41 PM PDT 24 Mar 21 02:35:42 PM PDT 24 51363870 ps
T857 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4182375443 Mar 21 02:35:55 PM PDT 24 Mar 21 02:35:57 PM PDT 24 148998507 ps
T858 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.260776879 Mar 21 02:35:55 PM PDT 24 Mar 21 02:35:57 PM PDT 24 68691306 ps
T859 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1436644654 Mar 21 02:35:57 PM PDT 24 Mar 21 02:35:58 PM PDT 24 237292433 ps
T860 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2058211301 Mar 21 02:35:42 PM PDT 24 Mar 21 02:35:43 PM PDT 24 128824457 ps
T861 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2909624061 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:57 PM PDT 24 62046461 ps
T862 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3951734986 Mar 21 02:35:57 PM PDT 24 Mar 21 02:35:58 PM PDT 24 88922276 ps
T863 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3370509126 Mar 21 02:36:00 PM PDT 24 Mar 21 02:36:01 PM PDT 24 75471698 ps
T864 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3467862821 Mar 21 02:36:00 PM PDT 24 Mar 21 02:36:02 PM PDT 24 320821418 ps
T865 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.14850769 Mar 21 02:35:59 PM PDT 24 Mar 21 02:36:00 PM PDT 24 53214861 ps
T866 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1420769649 Mar 21 02:35:54 PM PDT 24 Mar 21 02:35:56 PM PDT 24 50083671 ps
T867 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1453887529 Mar 21 02:35:58 PM PDT 24 Mar 21 02:35:59 PM PDT 24 66649337 ps
T868 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1491593819 Mar 21 02:35:43 PM PDT 24 Mar 21 02:35:44 PM PDT 24 532219718 ps
T869 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1186966168 Mar 21 02:35:41 PM PDT 24 Mar 21 02:35:42 PM PDT 24 40175785 ps
T870 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2927535749 Mar 21 02:35:49 PM PDT 24 Mar 21 02:35:51 PM PDT 24 70649307 ps
T871 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4117411051 Mar 21 02:35:41 PM PDT 24 Mar 21 02:35:42 PM PDT 24 191042416 ps
T872 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1272441338 Mar 21 02:36:01 PM PDT 24 Mar 21 02:36:03 PM PDT 24 53252156 ps
T873 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3773737154 Mar 21 02:35:43 PM PDT 24 Mar 21 02:35:44 PM PDT 24 38356204 ps
T874 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4272987785 Mar 21 02:35:45 PM PDT 24 Mar 21 02:35:46 PM PDT 24 225596226 ps
T875 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1561816826 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:57 PM PDT 24 64270896 ps
T876 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3409922006 Mar 21 02:35:41 PM PDT 24 Mar 21 02:35:43 PM PDT 24 42414105 ps
T877 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.444706233 Mar 21 02:35:44 PM PDT 24 Mar 21 02:35:45 PM PDT 24 246031841 ps
T878 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.591942937 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:57 PM PDT 24 287472561 ps
T879 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3287141495 Mar 21 02:35:54 PM PDT 24 Mar 21 02:35:55 PM PDT 24 190739579 ps
T880 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2836062836 Mar 21 02:35:54 PM PDT 24 Mar 21 02:35:56 PM PDT 24 210207498 ps
T881 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.513793313 Mar 21 02:35:44 PM PDT 24 Mar 21 02:35:46 PM PDT 24 457052223 ps
T882 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2120134388 Mar 21 02:35:57 PM PDT 24 Mar 21 02:35:59 PM PDT 24 125385281 ps
T883 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4261845140 Mar 21 02:36:06 PM PDT 24 Mar 21 02:36:09 PM PDT 24 54969770 ps
T884 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.856396715 Mar 21 02:35:57 PM PDT 24 Mar 21 02:35:58 PM PDT 24 120508383 ps
T885 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3352560977 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:57 PM PDT 24 100362116 ps
T886 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2850068580 Mar 21 02:35:44 PM PDT 24 Mar 21 02:35:45 PM PDT 24 68470868 ps
T887 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1487827950 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:57 PM PDT 24 231994327 ps
T888 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1943595026 Mar 21 02:35:57 PM PDT 24 Mar 21 02:35:58 PM PDT 24 118600158 ps
T889 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.4062061426 Mar 21 02:35:43 PM PDT 24 Mar 21 02:35:43 PM PDT 24 37938207 ps
T890 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2924450838 Mar 21 02:35:57 PM PDT 24 Mar 21 02:35:58 PM PDT 24 61216065 ps
T891 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.730488838 Mar 21 02:35:45 PM PDT 24 Mar 21 02:35:46 PM PDT 24 86458491 ps
T892 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1878974128 Mar 21 02:35:57 PM PDT 24 Mar 21 02:35:58 PM PDT 24 157299107 ps
T893 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1929217643 Mar 21 02:35:30 PM PDT 24 Mar 21 02:35:31 PM PDT 24 404338173 ps
T894 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.4178582663 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:57 PM PDT 24 45693697 ps
T895 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4274339363 Mar 21 02:35:49 PM PDT 24 Mar 21 02:35:51 PM PDT 24 67423162 ps
T896 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.333564157 Mar 21 02:36:00 PM PDT 24 Mar 21 02:36:02 PM PDT 24 357891801 ps
T897 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1382766843 Mar 21 02:35:43 PM PDT 24 Mar 21 02:35:44 PM PDT 24 441977997 ps
T898 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3928099069 Mar 21 02:36:00 PM PDT 24 Mar 21 02:36:01 PM PDT 24 94479071 ps
T899 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3268697705 Mar 21 02:36:07 PM PDT 24 Mar 21 02:36:09 PM PDT 24 173636964 ps
T900 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2946331347 Mar 21 02:36:04 PM PDT 24 Mar 21 02:36:05 PM PDT 24 94578762 ps
T901 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.67824874 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:57 PM PDT 24 212368754 ps
T902 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1140114542 Mar 21 02:35:44 PM PDT 24 Mar 21 02:35:45 PM PDT 24 225322210 ps
T903 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2329117019 Mar 21 02:35:45 PM PDT 24 Mar 21 02:35:46 PM PDT 24 762763081 ps
T904 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2111319342 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:57 PM PDT 24 284284743 ps
T905 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3678850297 Mar 21 02:35:44 PM PDT 24 Mar 21 02:35:45 PM PDT 24 310330659 ps
T906 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.179449976 Mar 21 02:35:42 PM PDT 24 Mar 21 02:35:44 PM PDT 24 270589746 ps
T907 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.492940781 Mar 21 02:35:43 PM PDT 24 Mar 21 02:35:44 PM PDT 24 74779942 ps
T908 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.983472582 Mar 21 02:35:42 PM PDT 24 Mar 21 02:35:43 PM PDT 24 55376130 ps
T909 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3813121079 Mar 21 02:35:59 PM PDT 24 Mar 21 02:36:01 PM PDT 24 200120863 ps
T910 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1255859240 Mar 21 02:36:06 PM PDT 24 Mar 21 02:36:07 PM PDT 24 56356613 ps
T911 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.948286814 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:57 PM PDT 24 165040961 ps
T912 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2032973342 Mar 21 02:35:44 PM PDT 24 Mar 21 02:35:45 PM PDT 24 40947973 ps
T913 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1924156039 Mar 21 02:35:57 PM PDT 24 Mar 21 02:35:59 PM PDT 24 102269067 ps
T914 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3419842784 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:58 PM PDT 24 80884008 ps
T915 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.465974016 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:58 PM PDT 24 226344911 ps
T916 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3349548633 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:57 PM PDT 24 189848017 ps
T917 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1451683085 Mar 21 02:36:00 PM PDT 24 Mar 21 02:36:01 PM PDT 24 186755471 ps
T918 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1457916973 Mar 21 02:35:42 PM PDT 24 Mar 21 02:35:43 PM PDT 24 194957569 ps
T919 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2264452878 Mar 21 02:36:01 PM PDT 24 Mar 21 02:36:02 PM PDT 24 75715486 ps
T920 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1102233381 Mar 21 02:36:00 PM PDT 24 Mar 21 02:36:01 PM PDT 24 27943155 ps
T921 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3162288053 Mar 21 02:35:45 PM PDT 24 Mar 21 02:35:46 PM PDT 24 129852745 ps
T922 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2034553267 Mar 21 02:36:13 PM PDT 24 Mar 21 02:36:14 PM PDT 24 44951866 ps
T923 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3741434036 Mar 21 02:35:55 PM PDT 24 Mar 21 02:35:57 PM PDT 24 99371580 ps
T924 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1848831503 Mar 21 02:36:00 PM PDT 24 Mar 21 02:36:02 PM PDT 24 36943814 ps
T925 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2788896552 Mar 21 02:35:45 PM PDT 24 Mar 21 02:35:46 PM PDT 24 187763186 ps
T926 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3747426727 Mar 21 02:35:42 PM PDT 24 Mar 21 02:35:44 PM PDT 24 381195982 ps
T927 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3196861478 Mar 21 02:35:56 PM PDT 24 Mar 21 02:35:58 PM PDT 24 328731390 ps
T928 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.567403958 Mar 21 02:36:00 PM PDT 24 Mar 21 02:36:01 PM PDT 24 58289271 ps
T929 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3237096622 Mar 21 02:35:57 PM PDT 24 Mar 21 02:35:59 PM PDT 24 61922261 ps
T930 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1502295788 Mar 21 02:35:41 PM PDT 24 Mar 21 02:35:42 PM PDT 24 177289285 ps
T931 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2696363629 Mar 21 02:35:57 PM PDT 24 Mar 21 02:35:59 PM PDT 24 97022160 ps
T932 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3966699929 Mar 21 02:36:10 PM PDT 24 Mar 21 02:36:11 PM PDT 24 45106403 ps
T933 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2553222175 Mar 21 02:35:49 PM PDT 24 Mar 21 02:35:51 PM PDT 24 35051063 ps
T934 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2103352087 Mar 21 02:36:06 PM PDT 24 Mar 21 02:36:09 PM PDT 24 55968620 ps

Test location /workspace/coverage/default/26.gpio_stress_all.1056611948
Short name T32
Test name
Test status
Simulation time 57724392909 ps
CPU time 204.93 seconds
Started Mar 21 12:39:45 PM PDT 24
Finished Mar 21 12:43:13 PM PDT 24
Peak memory 198028 kb
Host smart-00dd07cc-05d2-4b7f-ae7f-8fea7794636e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056611948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1056611948
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2235970612
Short name T26
Test name
Test status
Simulation time 51243419 ps
CPU time 2.24 seconds
Started Mar 21 12:39:14 PM PDT 24
Finished Mar 21 12:39:17 PM PDT 24
Peak memory 198044 kb
Host smart-d2bce516-7670-46c4-96c4-b2b93250f920
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235970612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2235970612
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.3172780793
Short name T2
Test name
Test status
Simulation time 155916032740 ps
CPU time 396.94 seconds
Started Mar 21 12:39:41 PM PDT 24
Finished Mar 21 12:46:18 PM PDT 24
Peak memory 198108 kb
Host smart-5ccc2f01-a0f6-45c3-babb-310569eed9bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3172780793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.3172780793
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1882291870
Short name T44
Test name
Test status
Simulation time 33877437 ps
CPU time 0.79 seconds
Started Mar 21 12:38:42 PM PDT 24
Finished Mar 21 12:38:43 PM PDT 24
Peak memory 213664 kb
Host smart-f8672639-c9cd-41b3-a46f-d6e149fa7401
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882291870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1882291870
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1875206978
Short name T79
Test name
Test status
Simulation time 16157672 ps
CPU time 0.57 seconds
Started Mar 21 02:33:55 PM PDT 24
Finished Mar 21 02:33:55 PM PDT 24
Peak memory 194424 kb
Host smart-9d5a7cc0-8f01-424a-ac24-62978d94fa61
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875206978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1875206978
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1211368612
Short name T41
Test name
Test status
Simulation time 134679382 ps
CPU time 1.51 seconds
Started Mar 21 02:33:53 PM PDT 24
Finished Mar 21 02:33:55 PM PDT 24
Peak memory 198128 kb
Host smart-9fb626d4-c57b-4704-a9ce-84cc3c1ddcde
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211368612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1211368612
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2124162765
Short name T28
Test name
Test status
Simulation time 14895481 ps
CPU time 0.59 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:38:41 PM PDT 24
Peak memory 193924 kb
Host smart-4719d85e-11f5-4605-80d1-5bfca5cb173d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124162765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2124162765
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3412488133
Short name T108
Test name
Test status
Simulation time 61891106 ps
CPU time 0.65 seconds
Started Mar 21 02:33:53 PM PDT 24
Finished Mar 21 02:33:54 PM PDT 24
Peak memory 195144 kb
Host smart-e7f4b896-72aa-40d3-a337-940ee2eca1f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412488133 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3412488133
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1360760855
Short name T48
Test name
Test status
Simulation time 44553232 ps
CPU time 0.9 seconds
Started Mar 21 02:34:36 PM PDT 24
Finished Mar 21 02:34:37 PM PDT 24
Peak memory 197336 kb
Host smart-40823e57-74cd-462d-91cf-759fc5b35f5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360760855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1360760855
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1813297651
Short name T52
Test name
Test status
Simulation time 234576837 ps
CPU time 0.91 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 197880 kb
Host smart-3a02b4aa-8d93-4329-8b3a-418d603121c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813297651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1813297651
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3281242940
Short name T92
Test name
Test status
Simulation time 60340597 ps
CPU time 0.76 seconds
Started Mar 21 02:33:53 PM PDT 24
Finished Mar 21 02:33:53 PM PDT 24
Peak memory 196228 kb
Host smart-5e04cbfd-3fd5-4069-bb52-57620e8926b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281242940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3281242940
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3844174737
Short name T98
Test name
Test status
Simulation time 1490013069 ps
CPU time 3.61 seconds
Started Mar 21 02:33:56 PM PDT 24
Finished Mar 21 02:33:59 PM PDT 24
Peak memory 197056 kb
Host smart-98a1fd98-999e-4bcf-8f07-ece4cc174169
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844174737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3844174737
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.4157686786
Short name T84
Test name
Test status
Simulation time 88388416 ps
CPU time 0.69 seconds
Started Mar 21 02:33:52 PM PDT 24
Finished Mar 21 02:33:53 PM PDT 24
Peak memory 194628 kb
Host smart-747dcbb0-b760-4b7b-85ae-7bd0707b9d98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157686786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.4157686786
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.180760510
Short name T726
Test name
Test status
Simulation time 24139127 ps
CPU time 1.11 seconds
Started Mar 21 02:33:53 PM PDT 24
Finished Mar 21 02:33:54 PM PDT 24
Peak memory 198032 kb
Host smart-16287433-2236-4d00-80b4-432d372e1d70
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180760510 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.180760510
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1051039048
Short name T90
Test name
Test status
Simulation time 14627507 ps
CPU time 0.58 seconds
Started Mar 21 02:33:52 PM PDT 24
Finished Mar 21 02:33:53 PM PDT 24
Peak memory 194024 kb
Host smart-d5811ffa-15a7-4ba8-9a5e-c26a42cdbe43
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051039048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1051039048
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2886336271
Short name T779
Test name
Test status
Simulation time 19124915 ps
CPU time 0.63 seconds
Started Mar 21 02:33:57 PM PDT 24
Finished Mar 21 02:33:57 PM PDT 24
Peak memory 193680 kb
Host smart-7bcd52b6-ec77-4629-9cbd-6eaa8dd2d3ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886336271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2886336271
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2290274012
Short name T772
Test name
Test status
Simulation time 52588933 ps
CPU time 1.3 seconds
Started Mar 21 02:33:52 PM PDT 24
Finished Mar 21 02:33:54 PM PDT 24
Peak memory 198016 kb
Host smart-71f0f654-ddac-4402-994d-da5ead3f87d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290274012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2290274012
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3912035465
Short name T50
Test name
Test status
Simulation time 83666046 ps
CPU time 0.89 seconds
Started Mar 21 02:33:55 PM PDT 24
Finished Mar 21 02:33:56 PM PDT 24
Peak memory 197296 kb
Host smart-52eb8c30-e375-4726-b627-404afa8f1972
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912035465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3912035465
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1803423121
Short name T768
Test name
Test status
Simulation time 29694644 ps
CPU time 0.78 seconds
Started Mar 21 02:33:52 PM PDT 24
Finished Mar 21 02:33:53 PM PDT 24
Peak memory 196428 kb
Host smart-a2f29081-2bcd-4152-9d4d-9bd46a937bd1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803423121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1803423121
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.456988920
Short name T99
Test name
Test status
Simulation time 580930459 ps
CPU time 1.54 seconds
Started Mar 21 02:33:54 PM PDT 24
Finished Mar 21 02:33:55 PM PDT 24
Peak memory 197860 kb
Host smart-0b304dba-e9d0-42c1-93ac-e41298494ed6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456988920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.456988920
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.806809087
Short name T747
Test name
Test status
Simulation time 44362721 ps
CPU time 0.64 seconds
Started Mar 21 02:33:50 PM PDT 24
Finished Mar 21 02:33:52 PM PDT 24
Peak memory 194948 kb
Host smart-da616e5d-1eee-4773-b37a-ce13d33d1cbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806809087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.806809087
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3515209866
Short name T718
Test name
Test status
Simulation time 130390935 ps
CPU time 0.96 seconds
Started Mar 21 02:33:57 PM PDT 24
Finished Mar 21 02:33:58 PM PDT 24
Peak memory 198016 kb
Host smart-d7971535-8744-40c8-ab82-3f5fceb8368c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515209866 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3515209866
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2700652146
Short name T744
Test name
Test status
Simulation time 14868641 ps
CPU time 0.63 seconds
Started Mar 21 02:33:53 PM PDT 24
Finished Mar 21 02:33:53 PM PDT 24
Peak memory 193724 kb
Host smart-2c3f65a9-5de7-4d10-a008-1ec9f6e823a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700652146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2700652146
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.739278301
Short name T791
Test name
Test status
Simulation time 16947151 ps
CPU time 0.79 seconds
Started Mar 21 02:33:54 PM PDT 24
Finished Mar 21 02:33:55 PM PDT 24
Peak memory 196180 kb
Host smart-ea32dde1-1730-4603-ba1c-a613042ac0ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739278301 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.739278301
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1923408567
Short name T746
Test name
Test status
Simulation time 52804301 ps
CPU time 1.34 seconds
Started Mar 21 02:33:57 PM PDT 24
Finished Mar 21 02:33:58 PM PDT 24
Peak memory 198004 kb
Host smart-916c7ebd-0d7b-421b-bb81-82beebc6a161
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923408567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1923408567
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2080687801
Short name T801
Test name
Test status
Simulation time 57848667 ps
CPU time 0.81 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 198072 kb
Host smart-6ae9e8c3-af28-4590-94a2-23d2b09dfe12
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080687801 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2080687801
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2388394585
Short name T756
Test name
Test status
Simulation time 36985198 ps
CPU time 0.59 seconds
Started Mar 21 02:34:24 PM PDT 24
Finished Mar 21 02:34:24 PM PDT 24
Peak memory 193952 kb
Host smart-70126b5f-bd6f-44e0-b0a3-26de5f4a9dc0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388394585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2388394585
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.637614521
Short name T759
Test name
Test status
Simulation time 16978367 ps
CPU time 0.62 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:19 PM PDT 24
Peak memory 193684 kb
Host smart-0e4cd0de-60ac-4f62-8dad-7132629ae323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637614521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.637614521
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1666868596
Short name T822
Test name
Test status
Simulation time 17236849 ps
CPU time 0.7 seconds
Started Mar 21 02:34:18 PM PDT 24
Finished Mar 21 02:34:19 PM PDT 24
Peak memory 194948 kb
Host smart-adeb703d-3d98-4cd6-a826-3a5deaf5becc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666868596 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1666868596
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1632748847
Short name T817
Test name
Test status
Simulation time 361722309 ps
CPU time 2.04 seconds
Started Mar 21 02:34:23 PM PDT 24
Finished Mar 21 02:34:25 PM PDT 24
Peak memory 198080 kb
Host smart-4dc19138-b675-41ca-bb56-9abd976d7d86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632748847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1632748847
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1590752642
Short name T748
Test name
Test status
Simulation time 93675637 ps
CPU time 1.16 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 198024 kb
Host smart-3a2ec5d6-3957-498e-91e9-2e8f1ff7d73b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590752642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1590752642
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.4199641734
Short name T828
Test name
Test status
Simulation time 17429454 ps
CPU time 0.8 seconds
Started Mar 21 02:34:21 PM PDT 24
Finished Mar 21 02:34:22 PM PDT 24
Peak memory 197972 kb
Host smart-750b24fc-5909-431b-b385-f6913fec297e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199641734 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.4199641734
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2812814184
Short name T87
Test name
Test status
Simulation time 14905274 ps
CPU time 0.58 seconds
Started Mar 21 02:34:17 PM PDT 24
Finished Mar 21 02:34:19 PM PDT 24
Peak memory 193704 kb
Host smart-ba77864e-9774-4ef6-957c-e21d7c8b1715
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812814184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2812814184
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2152549399
Short name T799
Test name
Test status
Simulation time 11939432 ps
CPU time 0.6 seconds
Started Mar 21 02:34:18 PM PDT 24
Finished Mar 21 02:34:19 PM PDT 24
Peak memory 194340 kb
Host smart-5f43940f-3ebf-4811-a62e-6112139d8f1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152549399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2152549399
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1196434324
Short name T780
Test name
Test status
Simulation time 28494880 ps
CPU time 0.76 seconds
Started Mar 21 02:34:20 PM PDT 24
Finished Mar 21 02:34:21 PM PDT 24
Peak memory 196140 kb
Host smart-407ad736-d97c-4c8c-bf8a-01a25da39c46
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196434324 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1196434324
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1819769234
Short name T785
Test name
Test status
Simulation time 94212919 ps
CPU time 2.1 seconds
Started Mar 21 02:34:21 PM PDT 24
Finished Mar 21 02:34:23 PM PDT 24
Peak memory 198096 kb
Host smart-673ab36d-59b1-4ecd-9573-768de4edc49a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819769234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1819769234
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.372832386
Short name T40
Test name
Test status
Simulation time 141667377 ps
CPU time 0.86 seconds
Started Mar 21 02:34:20 PM PDT 24
Finished Mar 21 02:34:21 PM PDT 24
Peak memory 197032 kb
Host smart-c57cf494-cfa2-42f2-8f67-91b6c5d5dd16
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372832386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.372832386
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2319660104
Short name T815
Test name
Test status
Simulation time 156895171 ps
CPU time 1.1 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 198004 kb
Host smart-4b7ff52f-39d9-466b-b0d5-cc190553ff0e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319660104 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2319660104
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1085335396
Short name T80
Test name
Test status
Simulation time 13883085 ps
CPU time 0.6 seconds
Started Mar 21 02:34:20 PM PDT 24
Finished Mar 21 02:34:21 PM PDT 24
Peak memory 194392 kb
Host smart-88ca2591-18bc-42eb-93ab-75086d3acaad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085335396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1085335396
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3012509588
Short name T765
Test name
Test status
Simulation time 18629023 ps
CPU time 0.6 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 193740 kb
Host smart-784619b8-b6c8-433f-8004-b74caa39de6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012509588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3012509588
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.105875114
Short name T103
Test name
Test status
Simulation time 43696595 ps
CPU time 0.84 seconds
Started Mar 21 02:34:21 PM PDT 24
Finished Mar 21 02:34:22 PM PDT 24
Peak memory 196344 kb
Host smart-0483eab2-db0b-4aa4-8e30-01d4cb9f5e0f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105875114 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 12.gpio_same_csr_outstanding.105875114
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.854293820
Short name T808
Test name
Test status
Simulation time 631908286 ps
CPU time 2.9 seconds
Started Mar 21 02:34:21 PM PDT 24
Finished Mar 21 02:34:25 PM PDT 24
Peak memory 198044 kb
Host smart-6bede0a2-7f2b-4afe-a9ba-22cb1b869967
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854293820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.854293820
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1435751856
Short name T800
Test name
Test status
Simulation time 34364037 ps
CPU time 1.54 seconds
Started Mar 21 02:34:23 PM PDT 24
Finished Mar 21 02:34:25 PM PDT 24
Peak memory 198140 kb
Host smart-fd91145f-e794-4f8f-8c26-d0f96750aedd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435751856 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1435751856
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2735786807
Short name T97
Test name
Test status
Simulation time 53821383 ps
CPU time 0.61 seconds
Started Mar 21 02:34:17 PM PDT 24
Finished Mar 21 02:34:19 PM PDT 24
Peak memory 194684 kb
Host smart-16747aab-1345-4394-8fd2-dd35f30a1422
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735786807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2735786807
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1199919065
Short name T730
Test name
Test status
Simulation time 63468832 ps
CPU time 0.62 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 193684 kb
Host smart-721b9194-2424-453c-bb45-5536beb7026e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199919065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1199919065
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.552870131
Short name T107
Test name
Test status
Simulation time 34405208 ps
CPU time 0.88 seconds
Started Mar 21 02:34:21 PM PDT 24
Finished Mar 21 02:34:22 PM PDT 24
Peak memory 196908 kb
Host smart-297690c6-deed-4167-8b46-31c4f7c4643c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552870131 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.552870131
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2883676456
Short name T719
Test name
Test status
Simulation time 177108940 ps
CPU time 3.12 seconds
Started Mar 21 02:34:20 PM PDT 24
Finished Mar 21 02:34:23 PM PDT 24
Peak memory 198016 kb
Host smart-0bc7397a-a451-468e-89fc-550726d3f748
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883676456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2883676456
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2898461862
Short name T820
Test name
Test status
Simulation time 45018355 ps
CPU time 0.87 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 197268 kb
Host smart-bb112057-c1c5-471c-83d7-49c868df639e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898461862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2898461862
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.79567267
Short name T713
Test name
Test status
Simulation time 44319664 ps
CPU time 1.31 seconds
Started Mar 21 02:34:39 PM PDT 24
Finished Mar 21 02:34:40 PM PDT 24
Peak memory 198032 kb
Host smart-6d780e9e-b055-48aa-8162-ef2d05a23237
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79567267 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.79567267
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.213281566
Short name T833
Test name
Test status
Simulation time 14196392 ps
CPU time 0.63 seconds
Started Mar 21 02:34:37 PM PDT 24
Finished Mar 21 02:34:38 PM PDT 24
Peak memory 193704 kb
Host smart-337174b0-51a6-4199-8729-96f8bbcbb92e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213281566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.213281566
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1188132298
Short name T720
Test name
Test status
Simulation time 58974126 ps
CPU time 0.65 seconds
Started Mar 21 02:34:32 PM PDT 24
Finished Mar 21 02:34:33 PM PDT 24
Peak memory 193776 kb
Host smart-56d1c106-f308-4dc8-a044-fd2343d7748a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188132298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1188132298
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1583387230
Short name T106
Test name
Test status
Simulation time 58981285 ps
CPU time 0.75 seconds
Started Mar 21 02:34:37 PM PDT 24
Finished Mar 21 02:34:38 PM PDT 24
Peak memory 196240 kb
Host smart-f5726299-12be-4f5c-ae1f-3d498ea0776c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583387230 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1583387230
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3695514098
Short name T755
Test name
Test status
Simulation time 86705712 ps
CPU time 1.58 seconds
Started Mar 21 02:34:33 PM PDT 24
Finished Mar 21 02:34:35 PM PDT 24
Peak memory 197992 kb
Host smart-d6b002f7-798c-42af-b797-1c30aade5859
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695514098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3695514098
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.60514570
Short name T830
Test name
Test status
Simulation time 249090194 ps
CPU time 0.93 seconds
Started Mar 21 02:34:37 PM PDT 24
Finished Mar 21 02:34:38 PM PDT 24
Peak memory 198044 kb
Host smart-f7b4aeda-1869-49bd-bc4b-905d347f858d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60514570 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.60514570
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1181291312
Short name T110
Test name
Test status
Simulation time 45372795 ps
CPU time 0.64 seconds
Started Mar 21 02:34:39 PM PDT 24
Finished Mar 21 02:34:39 PM PDT 24
Peak memory 194956 kb
Host smart-8d47032d-4d95-437b-9090-40c6e3949490
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181291312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1181291312
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3777704285
Short name T804
Test name
Test status
Simulation time 51135858 ps
CPU time 0.62 seconds
Started Mar 21 02:34:34 PM PDT 24
Finished Mar 21 02:34:35 PM PDT 24
Peak memory 194444 kb
Host smart-eaead0ae-013c-42ba-b156-822ed72cd3c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777704285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3777704285
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2960995761
Short name T809
Test name
Test status
Simulation time 19206180 ps
CPU time 0.65 seconds
Started Mar 21 02:34:37 PM PDT 24
Finished Mar 21 02:34:38 PM PDT 24
Peak memory 194880 kb
Host smart-c0737c69-ddcb-493c-a722-964fb8bef477
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960995761 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2960995761
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2558484876
Short name T725
Test name
Test status
Simulation time 199755236 ps
CPU time 1.7 seconds
Started Mar 21 02:34:35 PM PDT 24
Finished Mar 21 02:34:37 PM PDT 24
Peak memory 198048 kb
Host smart-4bbe161b-3239-4553-9a60-157e4a6e041f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558484876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2558484876
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2097097280
Short name T39
Test name
Test status
Simulation time 330076353 ps
CPU time 1.12 seconds
Started Mar 21 02:34:35 PM PDT 24
Finished Mar 21 02:34:36 PM PDT 24
Peak memory 197720 kb
Host smart-752e2377-3b1d-497a-8eab-2f0d6800eaa9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097097280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2097097280
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3772632258
Short name T811
Test name
Test status
Simulation time 29521951 ps
CPU time 0.86 seconds
Started Mar 21 02:34:40 PM PDT 24
Finished Mar 21 02:34:41 PM PDT 24
Peak memory 198016 kb
Host smart-576d606b-223c-460f-b0c3-55120398f102
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772632258 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3772632258
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3136191204
Short name T814
Test name
Test status
Simulation time 44228486 ps
CPU time 0.64 seconds
Started Mar 21 02:34:36 PM PDT 24
Finished Mar 21 02:34:37 PM PDT 24
Peak memory 194844 kb
Host smart-4d388674-73d5-40dd-a75d-a06adacf6dda
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136191204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3136191204
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.4291172002
Short name T786
Test name
Test status
Simulation time 12246855 ps
CPU time 0.62 seconds
Started Mar 21 02:34:37 PM PDT 24
Finished Mar 21 02:34:38 PM PDT 24
Peak memory 193752 kb
Host smart-fb2132ca-7ab8-421e-b294-2bb413b52d33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291172002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.4291172002
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2644175659
Short name T802
Test name
Test status
Simulation time 24935626 ps
CPU time 0.73 seconds
Started Mar 21 02:34:34 PM PDT 24
Finished Mar 21 02:34:35 PM PDT 24
Peak memory 195080 kb
Host smart-edefc8a4-e74c-4a0f-9de0-2a7ccc5606b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644175659 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2644175659
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.4215394542
Short name T724
Test name
Test status
Simulation time 252260423 ps
CPU time 1.42 seconds
Started Mar 21 02:34:36 PM PDT 24
Finished Mar 21 02:34:38 PM PDT 24
Peak memory 198048 kb
Host smart-108d95f8-6ae6-412f-8d11-4910ea909897
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215394542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.4215394542
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3958696817
Short name T806
Test name
Test status
Simulation time 278458474 ps
CPU time 1.15 seconds
Started Mar 21 02:34:34 PM PDT 24
Finished Mar 21 02:34:35 PM PDT 24
Peak memory 198012 kb
Host smart-aa716269-4078-4291-a437-5ee823ed828b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958696817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3958696817
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.539617495
Short name T729
Test name
Test status
Simulation time 28287884 ps
CPU time 0.85 seconds
Started Mar 21 02:34:36 PM PDT 24
Finished Mar 21 02:34:37 PM PDT 24
Peak memory 198004 kb
Host smart-ec29dc5a-d017-4b9d-829a-e8e2ff27dd1f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539617495 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.539617495
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.642323730
Short name T100
Test name
Test status
Simulation time 33644105 ps
CPU time 0.59 seconds
Started Mar 21 02:34:32 PM PDT 24
Finished Mar 21 02:34:33 PM PDT 24
Peak memory 194588 kb
Host smart-eee23dc8-0bef-4b5b-9f99-b40416235bfc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642323730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.642323730
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1599231557
Short name T824
Test name
Test status
Simulation time 23047914 ps
CPU time 0.6 seconds
Started Mar 21 02:34:34 PM PDT 24
Finished Mar 21 02:34:35 PM PDT 24
Peak memory 193676 kb
Host smart-d7daa874-8bbb-4a61-9005-c2a2e9bb1cbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599231557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1599231557
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.4238243532
Short name T104
Test name
Test status
Simulation time 15984230 ps
CPU time 0.66 seconds
Started Mar 21 02:34:32 PM PDT 24
Finished Mar 21 02:34:33 PM PDT 24
Peak memory 194832 kb
Host smart-16e4879b-d301-41d1-b374-f02ecb1042e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238243532 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.4238243532
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1158380426
Short name T738
Test name
Test status
Simulation time 156079946 ps
CPU time 2.25 seconds
Started Mar 21 02:34:36 PM PDT 24
Finished Mar 21 02:34:38 PM PDT 24
Peak memory 198044 kb
Host smart-cd7abb78-04cf-4169-ab24-2a1c931af4ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158380426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1158380426
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.227390993
Short name T827
Test name
Test status
Simulation time 130453532 ps
CPU time 0.9 seconds
Started Mar 21 02:34:40 PM PDT 24
Finished Mar 21 02:34:41 PM PDT 24
Peak memory 197292 kb
Host smart-4868eb75-d07c-4a58-bbeb-3a7c18f943a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227390993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.227390993
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.601806306
Short name T819
Test name
Test status
Simulation time 53179090 ps
CPU time 1.4 seconds
Started Mar 21 02:34:34 PM PDT 24
Finished Mar 21 02:34:35 PM PDT 24
Peak memory 198092 kb
Host smart-747d81a7-88f9-431c-a076-b41f808134f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601806306 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.601806306
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3740368632
Short name T89
Test name
Test status
Simulation time 22718611 ps
CPU time 0.6 seconds
Started Mar 21 02:34:35 PM PDT 24
Finished Mar 21 02:34:35 PM PDT 24
Peak memory 194652 kb
Host smart-0995dba1-278c-439c-ac33-f90df4a11039
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740368632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3740368632
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.530556696
Short name T754
Test name
Test status
Simulation time 26458805 ps
CPU time 0.63 seconds
Started Mar 21 02:34:34 PM PDT 24
Finished Mar 21 02:34:35 PM PDT 24
Peak memory 194376 kb
Host smart-aa6ee337-9b27-4ed7-a9e5-997546b3c70a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530556696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.530556696
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3056528761
Short name T783
Test name
Test status
Simulation time 29481100 ps
CPU time 0.65 seconds
Started Mar 21 02:34:35 PM PDT 24
Finished Mar 21 02:34:35 PM PDT 24
Peak memory 194792 kb
Host smart-1335b15c-a467-421a-b687-da5000f53d3e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056528761 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3056528761
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.477530370
Short name T818
Test name
Test status
Simulation time 167345277 ps
CPU time 1.46 seconds
Started Mar 21 02:34:37 PM PDT 24
Finished Mar 21 02:34:39 PM PDT 24
Peak memory 198040 kb
Host smart-66a97b14-6d35-455e-acd5-7fc8b0df7193
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477530370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.477530370
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3567068481
Short name T831
Test name
Test status
Simulation time 42763004 ps
CPU time 0.91 seconds
Started Mar 21 02:34:40 PM PDT 24
Finished Mar 21 02:34:41 PM PDT 24
Peak memory 197224 kb
Host smart-6f771588-9bf7-4138-ad6c-4bf159c6c791
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567068481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3567068481
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3905874520
Short name T763
Test name
Test status
Simulation time 92198733 ps
CPU time 1.15 seconds
Started Mar 21 02:34:32 PM PDT 24
Finished Mar 21 02:34:34 PM PDT 24
Peak memory 198116 kb
Host smart-367b1f95-c4c6-4598-b24f-23b5e9723bcd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905874520 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3905874520
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4253322534
Short name T109
Test name
Test status
Simulation time 11589080 ps
CPU time 0.59 seconds
Started Mar 21 02:34:42 PM PDT 24
Finished Mar 21 02:34:46 PM PDT 24
Peak memory 194676 kb
Host smart-8a5adfc8-5310-444f-8bf5-3255c3f1b34c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253322534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4253322534
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2151465351
Short name T812
Test name
Test status
Simulation time 29718400 ps
CPU time 0.62 seconds
Started Mar 21 02:34:35 PM PDT 24
Finished Mar 21 02:34:36 PM PDT 24
Peak memory 193724 kb
Host smart-5824f3de-73d2-4e9d-969e-e058339c6d16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151465351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2151465351
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.888623648
Short name T81
Test name
Test status
Simulation time 40262409 ps
CPU time 0.7 seconds
Started Mar 21 02:34:39 PM PDT 24
Finished Mar 21 02:34:39 PM PDT 24
Peak memory 195720 kb
Host smart-d64aebaa-70cb-48ac-b59f-43d354288e64
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888623648 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.888623648
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2228278511
Short name T733
Test name
Test status
Simulation time 101224358 ps
CPU time 1.52 seconds
Started Mar 21 02:34:55 PM PDT 24
Finished Mar 21 02:34:56 PM PDT 24
Peak memory 198064 kb
Host smart-a0cf93e4-a5f1-4461-adb3-71a175b3afac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228278511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2228278511
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1420000686
Short name T782
Test name
Test status
Simulation time 148631892 ps
CPU time 0.9 seconds
Started Mar 21 02:34:41 PM PDT 24
Finished Mar 21 02:34:45 PM PDT 24
Peak memory 197892 kb
Host smart-582af854-f970-4de1-8530-2ea3b3811bdf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420000686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1420000686
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3512776353
Short name T96
Test name
Test status
Simulation time 88926379 ps
CPU time 0.76 seconds
Started Mar 21 02:33:55 PM PDT 24
Finished Mar 21 02:33:56 PM PDT 24
Peak memory 196044 kb
Host smart-d6e5c21e-d25a-4e1f-b923-57ec13696c94
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512776353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3512776353
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2688629525
Short name T717
Test name
Test status
Simulation time 360882754 ps
CPU time 1.45 seconds
Started Mar 21 02:34:07 PM PDT 24
Finished Mar 21 02:34:11 PM PDT 24
Peak memory 198000 kb
Host smart-f94d9edd-e1bd-4123-92ad-246c6cd4f840
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688629525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2688629525
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1015840700
Short name T773
Test name
Test status
Simulation time 105132046 ps
CPU time 0.61 seconds
Started Mar 21 02:34:03 PM PDT 24
Finished Mar 21 02:34:03 PM PDT 24
Peak memory 195476 kb
Host smart-a7ec9389-aaa4-46ea-a14f-22304d012d77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015840700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1015840700
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.4158422552
Short name T790
Test name
Test status
Simulation time 32236619 ps
CPU time 0.86 seconds
Started Mar 21 02:34:04 PM PDT 24
Finished Mar 21 02:34:05 PM PDT 24
Peak memory 198044 kb
Host smart-994a83bb-dfb7-427f-9902-2083d9a09219
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158422552 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.4158422552
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.4216334374
Short name T795
Test name
Test status
Simulation time 27624366 ps
CPU time 0.57 seconds
Started Mar 21 02:33:53 PM PDT 24
Finished Mar 21 02:33:54 PM PDT 24
Peak memory 193940 kb
Host smart-0a4f8c5d-fa85-4111-bc29-37f12efa9852
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216334374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.4216334374
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1975079194
Short name T789
Test name
Test status
Simulation time 16684000 ps
CPU time 0.62 seconds
Started Mar 21 02:34:06 PM PDT 24
Finished Mar 21 02:34:08 PM PDT 24
Peak memory 194388 kb
Host smart-de50d67f-3e6e-476e-8520-3a04902dd8dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975079194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1975079194
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3773023549
Short name T101
Test name
Test status
Simulation time 97211106 ps
CPU time 0.65 seconds
Started Mar 21 02:33:57 PM PDT 24
Finished Mar 21 02:33:57 PM PDT 24
Peak memory 194956 kb
Host smart-95b49550-9a3f-458f-a800-32270e41b31e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773023549 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3773023549
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2179828404
Short name T715
Test name
Test status
Simulation time 219817584 ps
CPU time 1.47 seconds
Started Mar 21 02:34:05 PM PDT 24
Finished Mar 21 02:34:06 PM PDT 24
Peak memory 198064 kb
Host smart-630bf214-bca1-46f7-8136-66f94ec00d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179828404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2179828404
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1409492420
Short name T51
Test name
Test status
Simulation time 83740321 ps
CPU time 0.89 seconds
Started Mar 21 02:34:03 PM PDT 24
Finished Mar 21 02:34:04 PM PDT 24
Peak memory 197952 kb
Host smart-a7503983-499b-4207-b646-15a379029345
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409492420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1409492420
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.615163203
Short name T735
Test name
Test status
Simulation time 11697254 ps
CPU time 0.64 seconds
Started Mar 21 02:34:36 PM PDT 24
Finished Mar 21 02:34:37 PM PDT 24
Peak memory 193768 kb
Host smart-43a34eb3-332e-4552-a890-6f3399422a06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615163203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.615163203
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2035959971
Short name T776
Test name
Test status
Simulation time 14073293 ps
CPU time 0.6 seconds
Started Mar 21 02:34:41 PM PDT 24
Finished Mar 21 02:34:46 PM PDT 24
Peak memory 193684 kb
Host smart-44dbc2be-6cff-454c-a759-2f95ba027733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035959971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2035959971
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1763887469
Short name T741
Test name
Test status
Simulation time 16265319 ps
CPU time 0.58 seconds
Started Mar 21 02:34:36 PM PDT 24
Finished Mar 21 02:34:36 PM PDT 24
Peak memory 194332 kb
Host smart-144a49e8-b05e-430e-ac90-542b7cee221f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763887469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1763887469
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3214262831
Short name T821
Test name
Test status
Simulation time 13429002 ps
CPU time 0.61 seconds
Started Mar 21 02:34:37 PM PDT 24
Finished Mar 21 02:34:37 PM PDT 24
Peak memory 193688 kb
Host smart-9c68a036-c664-4964-9609-b9e047fbcd5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214262831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3214262831
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1539672307
Short name T734
Test name
Test status
Simulation time 18519729 ps
CPU time 0.62 seconds
Started Mar 21 02:34:39 PM PDT 24
Finished Mar 21 02:34:39 PM PDT 24
Peak memory 193652 kb
Host smart-cb43ae7d-471e-44fd-893a-ff226909c357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539672307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1539672307
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.896373469
Short name T749
Test name
Test status
Simulation time 37314028 ps
CPU time 0.61 seconds
Started Mar 21 02:34:33 PM PDT 24
Finished Mar 21 02:34:34 PM PDT 24
Peak memory 194308 kb
Host smart-26713e1f-c80a-4ed9-99e7-f20f19b759ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896373469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.896373469
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.941530632
Short name T774
Test name
Test status
Simulation time 46827568 ps
CPU time 0.61 seconds
Started Mar 21 02:34:41 PM PDT 24
Finished Mar 21 02:34:45 PM PDT 24
Peak memory 193796 kb
Host smart-90b42703-bfc5-457f-8c81-d66d8755a2b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941530632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.941530632
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2835760321
Short name T737
Test name
Test status
Simulation time 15843283 ps
CPU time 0.65 seconds
Started Mar 21 02:34:34 PM PDT 24
Finished Mar 21 02:34:35 PM PDT 24
Peak memory 194484 kb
Host smart-3c8d9433-b406-4686-a75c-98d7e6acf210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835760321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2835760321
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2891029030
Short name T728
Test name
Test status
Simulation time 42881746 ps
CPU time 0.6 seconds
Started Mar 21 02:34:41 PM PDT 24
Finished Mar 21 02:34:46 PM PDT 24
Peak memory 193708 kb
Host smart-ab8020ae-37c2-4d3e-a690-e9a6ad179492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891029030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2891029030
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.810321677
Short name T750
Test name
Test status
Simulation time 69937991 ps
CPU time 0.61 seconds
Started Mar 21 02:34:34 PM PDT 24
Finished Mar 21 02:34:35 PM PDT 24
Peak memory 194348 kb
Host smart-01a153a9-593e-4016-81ed-430fb6534738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810321677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.810321677
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3555796372
Short name T83
Test name
Test status
Simulation time 48078780 ps
CPU time 0.81 seconds
Started Mar 21 02:34:05 PM PDT 24
Finished Mar 21 02:34:07 PM PDT 24
Peak memory 196732 kb
Host smart-8de1a983-b323-4c5b-92c0-f6cea5589e65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555796372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3555796372
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1419362192
Short name T769
Test name
Test status
Simulation time 327101613 ps
CPU time 3.54 seconds
Started Mar 21 02:34:06 PM PDT 24
Finished Mar 21 02:34:10 PM PDT 24
Peak memory 197848 kb
Host smart-e81e9c6b-2b62-4961-a7c3-2563b90710a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419362192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1419362192
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2575886935
Short name T781
Test name
Test status
Simulation time 68673405 ps
CPU time 0.71 seconds
Started Mar 21 02:34:05 PM PDT 24
Finished Mar 21 02:34:07 PM PDT 24
Peak memory 194696 kb
Host smart-4c468803-d212-4cb0-b30b-d2f140feda4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575886935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2575886935
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3952545732
Short name T771
Test name
Test status
Simulation time 54371527 ps
CPU time 0.66 seconds
Started Mar 21 02:34:05 PM PDT 24
Finished Mar 21 02:34:06 PM PDT 24
Peak memory 197152 kb
Host smart-468d1585-3766-4c70-89c7-b2cf8bde8783
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952545732 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3952545732
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.630232139
Short name T88
Test name
Test status
Simulation time 18213639 ps
CPU time 0.64 seconds
Started Mar 21 02:34:05 PM PDT 24
Finished Mar 21 02:34:06 PM PDT 24
Peak memory 194816 kb
Host smart-c41c5b3f-9bcb-4cb8-b058-91275a989fa8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630232139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.630232139
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2821055446
Short name T796
Test name
Test status
Simulation time 27176929 ps
CPU time 0.65 seconds
Started Mar 21 02:34:05 PM PDT 24
Finished Mar 21 02:34:06 PM PDT 24
Peak memory 193776 kb
Host smart-d688fab3-60c5-443a-930c-493d8cd9d461
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821055446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2821055446
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1160817184
Short name T816
Test name
Test status
Simulation time 50138950 ps
CPU time 0.78 seconds
Started Mar 21 02:34:08 PM PDT 24
Finished Mar 21 02:34:11 PM PDT 24
Peak memory 196888 kb
Host smart-4a03bec8-17f3-4dfd-9fb6-201953cc216a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160817184 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1160817184
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.210391293
Short name T803
Test name
Test status
Simulation time 166047067 ps
CPU time 2.01 seconds
Started Mar 21 02:34:05 PM PDT 24
Finished Mar 21 02:34:08 PM PDT 24
Peak memory 197984 kb
Host smart-70920397-eb73-4318-a484-2832f74462f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210391293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.210391293
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1691988586
Short name T43
Test name
Test status
Simulation time 212382791 ps
CPU time 1.5 seconds
Started Mar 21 02:34:06 PM PDT 24
Finished Mar 21 02:34:09 PM PDT 24
Peak memory 198080 kb
Host smart-997b1dd7-fc3d-46a9-8e67-2b4a739fdebb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691988586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1691988586
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1848468721
Short name T727
Test name
Test status
Simulation time 15000447 ps
CPU time 0.59 seconds
Started Mar 21 02:34:34 PM PDT 24
Finished Mar 21 02:34:35 PM PDT 24
Peak memory 194300 kb
Host smart-89797036-e300-4dae-975e-5e6b306d0b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848468721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1848468721
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1764037184
Short name T826
Test name
Test status
Simulation time 15764400 ps
CPU time 0.63 seconds
Started Mar 21 02:34:39 PM PDT 24
Finished Mar 21 02:34:41 PM PDT 24
Peak memory 193668 kb
Host smart-c8131ad1-459c-4283-a182-311b19c08ca1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764037184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1764037184
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2872215145
Short name T722
Test name
Test status
Simulation time 61229319 ps
CPU time 0.58 seconds
Started Mar 21 02:34:32 PM PDT 24
Finished Mar 21 02:34:33 PM PDT 24
Peak memory 193704 kb
Host smart-071f9b50-5350-4e0f-a144-d9e466e9a622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872215145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2872215145
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.846335694
Short name T775
Test name
Test status
Simulation time 56896558 ps
CPU time 0.65 seconds
Started Mar 21 02:34:35 PM PDT 24
Finished Mar 21 02:34:36 PM PDT 24
Peak memory 193684 kb
Host smart-e55b985e-2101-48bd-8ac6-baace1b22524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846335694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.846335694
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2543557633
Short name T829
Test name
Test status
Simulation time 20535358 ps
CPU time 0.64 seconds
Started Mar 21 02:34:40 PM PDT 24
Finished Mar 21 02:34:41 PM PDT 24
Peak memory 193708 kb
Host smart-2eecbf05-db82-48b0-be1d-914716f8f5dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543557633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2543557633
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1087270121
Short name T784
Test name
Test status
Simulation time 46237228 ps
CPU time 0.61 seconds
Started Mar 21 02:34:50 PM PDT 24
Finished Mar 21 02:34:51 PM PDT 24
Peak memory 193700 kb
Host smart-6c4bf30e-8254-441d-a024-09eeb8c46a26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087270121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1087270121
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3182801250
Short name T764
Test name
Test status
Simulation time 15776270 ps
CPU time 0.64 seconds
Started Mar 21 02:34:50 PM PDT 24
Finished Mar 21 02:34:51 PM PDT 24
Peak memory 193732 kb
Host smart-53cc7af1-a474-4796-be98-397cf091ef93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182801250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3182801250
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.45905700
Short name T792
Test name
Test status
Simulation time 21374744 ps
CPU time 0.63 seconds
Started Mar 21 02:34:49 PM PDT 24
Finished Mar 21 02:34:50 PM PDT 24
Peak memory 193724 kb
Host smart-49117018-2b2a-49c8-86ed-2210882fa17f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45905700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.45905700
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2652255432
Short name T745
Test name
Test status
Simulation time 54133889 ps
CPU time 0.61 seconds
Started Mar 21 02:34:53 PM PDT 24
Finished Mar 21 02:34:55 PM PDT 24
Peak memory 193660 kb
Host smart-7ffb02ac-720e-4311-ac2c-a827c4312999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652255432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2652255432
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.602216160
Short name T739
Test name
Test status
Simulation time 13757127 ps
CPU time 0.58 seconds
Started Mar 21 02:34:50 PM PDT 24
Finished Mar 21 02:34:50 PM PDT 24
Peak memory 193580 kb
Host smart-d3b5db83-587e-4107-ba31-fb87eba818d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602216160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.602216160
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.833712722
Short name T95
Test name
Test status
Simulation time 114631153 ps
CPU time 0.9 seconds
Started Mar 21 02:34:06 PM PDT 24
Finished Mar 21 02:34:08 PM PDT 24
Peak memory 196196 kb
Host smart-e26f15e9-133c-4364-a75e-74589138c9ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833712722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.833712722
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4149105926
Short name T793
Test name
Test status
Simulation time 578957396 ps
CPU time 1.49 seconds
Started Mar 21 02:34:08 PM PDT 24
Finished Mar 21 02:34:11 PM PDT 24
Peak memory 197116 kb
Host smart-dbae2e17-0f45-40c4-9530-5dec8d816591
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149105926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.4149105926
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.4153931125
Short name T93
Test name
Test status
Simulation time 27266511 ps
CPU time 0.65 seconds
Started Mar 21 02:34:07 PM PDT 24
Finished Mar 21 02:34:10 PM PDT 24
Peak memory 194732 kb
Host smart-04b69cd7-4931-4556-9dda-640f15b9db4b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153931125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.4153931125
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3983595488
Short name T805
Test name
Test status
Simulation time 110754256 ps
CPU time 0.99 seconds
Started Mar 21 02:34:06 PM PDT 24
Finished Mar 21 02:34:08 PM PDT 24
Peak memory 198040 kb
Host smart-c28c2790-d578-46db-9a8d-a25a8cd6f0b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983595488 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3983595488
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.509201166
Short name T86
Test name
Test status
Simulation time 11910913 ps
CPU time 0.61 seconds
Started Mar 21 02:34:06 PM PDT 24
Finished Mar 21 02:34:08 PM PDT 24
Peak memory 194612 kb
Host smart-45eebe99-c61d-47ca-aad1-7b7e6aefcba8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509201166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.509201166
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1779741879
Short name T732
Test name
Test status
Simulation time 15125665 ps
CPU time 0.59 seconds
Started Mar 21 02:34:08 PM PDT 24
Finished Mar 21 02:34:11 PM PDT 24
Peak memory 193668 kb
Host smart-fe48a497-3750-48a2-ae0b-ac7cf69791f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779741879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1779741879
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3594899454
Short name T767
Test name
Test status
Simulation time 211943970 ps
CPU time 0.9 seconds
Started Mar 21 02:34:05 PM PDT 24
Finished Mar 21 02:34:07 PM PDT 24
Peak memory 196256 kb
Host smart-e46660f6-f488-4021-a5b8-855bcaacebf1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594899454 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3594899454
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2235711871
Short name T761
Test name
Test status
Simulation time 118090322 ps
CPU time 2.39 seconds
Started Mar 21 02:34:07 PM PDT 24
Finished Mar 21 02:34:12 PM PDT 24
Peak memory 198052 kb
Host smart-2d70d4ba-0aa5-4467-843f-d2a170810196
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235711871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2235711871
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1811917786
Short name T53
Test name
Test status
Simulation time 41746469 ps
CPU time 0.87 seconds
Started Mar 21 02:34:07 PM PDT 24
Finished Mar 21 02:34:10 PM PDT 24
Peak memory 197240 kb
Host smart-7d182a8d-fa5c-4064-b5eb-b15fae137945
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811917786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1811917786
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2432879345
Short name T757
Test name
Test status
Simulation time 16591774 ps
CPU time 0.64 seconds
Started Mar 21 02:34:49 PM PDT 24
Finished Mar 21 02:34:50 PM PDT 24
Peak memory 193712 kb
Host smart-b6a7a6ca-4e20-4368-aea7-a8f1f0d64e54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432879345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2432879345
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.340754973
Short name T766
Test name
Test status
Simulation time 15776291 ps
CPU time 0.61 seconds
Started Mar 21 02:34:51 PM PDT 24
Finished Mar 21 02:34:52 PM PDT 24
Peak memory 193676 kb
Host smart-a65146c6-2d2d-4d25-80c7-454d92c37fae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340754973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.340754973
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3308763294
Short name T740
Test name
Test status
Simulation time 121172806 ps
CPU time 0.63 seconds
Started Mar 21 02:34:49 PM PDT 24
Finished Mar 21 02:34:50 PM PDT 24
Peak memory 193676 kb
Host smart-f16e7648-d6b7-411d-9c23-296d298f3abb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308763294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3308763294
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.487893265
Short name T770
Test name
Test status
Simulation time 11382099 ps
CPU time 0.67 seconds
Started Mar 21 02:34:49 PM PDT 24
Finished Mar 21 02:34:50 PM PDT 24
Peak memory 193756 kb
Host smart-49d3b18a-b6d7-492c-9798-cf93aada5f23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487893265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.487893265
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3662003844
Short name T778
Test name
Test status
Simulation time 40106991 ps
CPU time 0.64 seconds
Started Mar 21 02:34:48 PM PDT 24
Finished Mar 21 02:34:49 PM PDT 24
Peak memory 193776 kb
Host smart-0763e331-448e-4dda-b053-2a85f2fb22f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662003844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3662003844
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2202945850
Short name T751
Test name
Test status
Simulation time 17125253 ps
CPU time 0.6 seconds
Started Mar 21 02:34:50 PM PDT 24
Finished Mar 21 02:34:51 PM PDT 24
Peak memory 193676 kb
Host smart-b11fb1b9-07db-4be6-87e8-91bb1809ff08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202945850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2202945850
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.527886527
Short name T731
Test name
Test status
Simulation time 15723969 ps
CPU time 0.59 seconds
Started Mar 21 02:34:49 PM PDT 24
Finished Mar 21 02:34:50 PM PDT 24
Peak memory 193668 kb
Host smart-be954889-d67d-47fd-9318-e38382c8e34a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527886527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.527886527
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2719826112
Short name T736
Test name
Test status
Simulation time 66416625 ps
CPU time 0.67 seconds
Started Mar 21 02:34:51 PM PDT 24
Finished Mar 21 02:34:52 PM PDT 24
Peak memory 193748 kb
Host smart-058fe749-6022-4fcd-8688-3c9ac0a6da10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719826112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2719826112
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.116662542
Short name T797
Test name
Test status
Simulation time 13774049 ps
CPU time 0.61 seconds
Started Mar 21 02:34:50 PM PDT 24
Finished Mar 21 02:34:50 PM PDT 24
Peak memory 193744 kb
Host smart-96560228-6510-49ba-8999-1640754d072c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116662542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.116662542
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2273878403
Short name T807
Test name
Test status
Simulation time 15134854 ps
CPU time 0.61 seconds
Started Mar 21 02:34:50 PM PDT 24
Finished Mar 21 02:34:51 PM PDT 24
Peak memory 193672 kb
Host smart-a4d017cc-5383-4f65-b219-508f528dd120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273878403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2273878403
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3249832193
Short name T716
Test name
Test status
Simulation time 223610095 ps
CPU time 0.74 seconds
Started Mar 21 02:34:08 PM PDT 24
Finished Mar 21 02:34:11 PM PDT 24
Peak memory 197716 kb
Host smart-24ad299f-1f03-4cae-b62d-638c8c5216ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249832193 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3249832193
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1384017674
Short name T753
Test name
Test status
Simulation time 14391608 ps
CPU time 0.61 seconds
Started Mar 21 02:34:06 PM PDT 24
Finished Mar 21 02:34:08 PM PDT 24
Peak memory 193964 kb
Host smart-c594af53-0878-4b56-ba26-b227a11c0573
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384017674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1384017674
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1089758548
Short name T760
Test name
Test status
Simulation time 14652936 ps
CPU time 0.65 seconds
Started Mar 21 02:34:08 PM PDT 24
Finished Mar 21 02:34:11 PM PDT 24
Peak memory 193664 kb
Host smart-3a5f3d82-ba70-44e3-af56-59e76fcea933
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089758548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1089758548
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3429140187
Short name T82
Test name
Test status
Simulation time 126381866 ps
CPU time 0.89 seconds
Started Mar 21 02:34:05 PM PDT 24
Finished Mar 21 02:34:06 PM PDT 24
Peak memory 197108 kb
Host smart-4b1dbd34-14c8-4a75-bc2a-1d1f68cdede4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429140187 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3429140187
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1000450152
Short name T721
Test name
Test status
Simulation time 505378531 ps
CPU time 2.33 seconds
Started Mar 21 02:34:06 PM PDT 24
Finished Mar 21 02:34:10 PM PDT 24
Peak memory 198024 kb
Host smart-3071545e-70df-44c1-9f9d-f61b0840d605
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000450152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1000450152
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3489418284
Short name T49
Test name
Test status
Simulation time 87425725 ps
CPU time 1.2 seconds
Started Mar 21 02:34:07 PM PDT 24
Finished Mar 21 02:34:10 PM PDT 24
Peak memory 197980 kb
Host smart-f1183074-f4cd-4a9c-8f0f-c9f3e25af75e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489418284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3489418284
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.4048559389
Short name T723
Test name
Test status
Simulation time 42305262 ps
CPU time 0.71 seconds
Started Mar 21 02:34:22 PM PDT 24
Finished Mar 21 02:34:23 PM PDT 24
Peak memory 197708 kb
Host smart-93bfd874-573d-4cad-b9bc-970297cd5acd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048559389 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.4048559389
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2975569865
Short name T94
Test name
Test status
Simulation time 32832720 ps
CPU time 0.65 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 194748 kb
Host smart-c4b916f5-2c86-4a4a-bf1b-89e631291b0f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975569865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2975569865
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.4289995841
Short name T742
Test name
Test status
Simulation time 15143561 ps
CPU time 0.64 seconds
Started Mar 21 02:34:23 PM PDT 24
Finished Mar 21 02:34:24 PM PDT 24
Peak memory 194360 kb
Host smart-680e9bdb-7025-49ff-9128-0719d745d747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289995841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.4289995841
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1069563333
Short name T102
Test name
Test status
Simulation time 17802614 ps
CPU time 0.68 seconds
Started Mar 21 02:34:18 PM PDT 24
Finished Mar 21 02:34:19 PM PDT 24
Peak memory 195484 kb
Host smart-7c628bec-104a-40bb-8c98-f44299571ee8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069563333 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1069563333
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3243122026
Short name T743
Test name
Test status
Simulation time 35458319 ps
CPU time 0.92 seconds
Started Mar 21 02:34:18 PM PDT 24
Finished Mar 21 02:34:19 PM PDT 24
Peak memory 197960 kb
Host smart-3cbbf793-fbac-488d-803a-3840ed86e59c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243122026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3243122026
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2234193257
Short name T752
Test name
Test status
Simulation time 206687972 ps
CPU time 0.93 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 197028 kb
Host smart-fb5d21a7-842e-4232-8b53-bf784c1072fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234193257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2234193257
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.107572346
Short name T758
Test name
Test status
Simulation time 75233959 ps
CPU time 0.81 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 198036 kb
Host smart-375e2a75-8e06-4bed-b8cd-764c6c4bfe55
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107572346 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.107572346
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1708526583
Short name T85
Test name
Test status
Simulation time 12043457 ps
CPU time 0.66 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 194824 kb
Host smart-ee73d70f-33fb-4161-8b08-ed6e786c4c33
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708526583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1708526583
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2603875997
Short name T714
Test name
Test status
Simulation time 16462466 ps
CPU time 0.64 seconds
Started Mar 21 02:34:18 PM PDT 24
Finished Mar 21 02:34:19 PM PDT 24
Peak memory 194292 kb
Host smart-043649a8-d99d-40b9-843e-9007e241bca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603875997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2603875997
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1951689123
Short name T813
Test name
Test status
Simulation time 59673011 ps
CPU time 0.8 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 197080 kb
Host smart-b870c8da-a7bb-43f6-b193-44053821baa6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951689123 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1951689123
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.819389250
Short name T788
Test name
Test status
Simulation time 67974112 ps
CPU time 1.01 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 197956 kb
Host smart-a0628b36-b414-4584-ba15-1d5b80a18357
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819389250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.819389250
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3595426180
Short name T111
Test name
Test status
Simulation time 50383184 ps
CPU time 0.91 seconds
Started Mar 21 02:34:18 PM PDT 24
Finished Mar 21 02:34:19 PM PDT 24
Peak memory 197300 kb
Host smart-d76e97b3-7474-484d-a68a-082ac5878091
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595426180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3595426180
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.763231312
Short name T777
Test name
Test status
Simulation time 137841519 ps
CPU time 1 seconds
Started Mar 21 02:34:20 PM PDT 24
Finished Mar 21 02:34:21 PM PDT 24
Peak memory 198020 kb
Host smart-b569680f-09bb-4d25-add9-f1bb04f1c4f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763231312 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.763231312
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.978541916
Short name T91
Test name
Test status
Simulation time 15629341 ps
CPU time 0.63 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 194416 kb
Host smart-cc05dbfe-2b67-46f9-be21-b7a52552ce3b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978541916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.978541916
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.43908760
Short name T825
Test name
Test status
Simulation time 59698823 ps
CPU time 0.64 seconds
Started Mar 21 02:34:18 PM PDT 24
Finished Mar 21 02:34:19 PM PDT 24
Peak memory 194392 kb
Host smart-b4387d5b-970b-4c4a-9d44-7ec8ddf2761a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43908760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.43908760
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3435467318
Short name T105
Test name
Test status
Simulation time 51405114 ps
CPU time 0.84 seconds
Started Mar 21 02:34:23 PM PDT 24
Finished Mar 21 02:34:24 PM PDT 24
Peak memory 196264 kb
Host smart-b55cb390-aa04-4d91-a004-404e21715670
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435467318 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3435467318
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1191861886
Short name T787
Test name
Test status
Simulation time 43453609 ps
CPU time 1.25 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 198084 kb
Host smart-3fb9c729-f35f-4654-9914-dbc8e97076f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191861886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1191861886
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1480193212
Short name T794
Test name
Test status
Simulation time 344911407 ps
CPU time 1.51 seconds
Started Mar 21 02:34:20 PM PDT 24
Finished Mar 21 02:34:22 PM PDT 24
Peak memory 197844 kb
Host smart-2bdc29b3-dace-41b8-97ff-9c20b0a0c396
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480193212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1480193212
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2122116608
Short name T810
Test name
Test status
Simulation time 20315608 ps
CPU time 0.98 seconds
Started Mar 21 02:34:20 PM PDT 24
Finished Mar 21 02:34:21 PM PDT 24
Peak memory 198044 kb
Host smart-39e4837a-1bd3-467d-b630-957119dd0684
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122116608 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2122116608
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2653335313
Short name T832
Test name
Test status
Simulation time 20723951 ps
CPU time 0.61 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:19 PM PDT 24
Peak memory 194656 kb
Host smart-feffd8ca-e87f-4e74-9bde-6359b3bc8d0e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653335313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2653335313
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2469812886
Short name T834
Test name
Test status
Simulation time 88866603 ps
CPU time 0.61 seconds
Started Mar 21 02:34:24 PM PDT 24
Finished Mar 21 02:34:24 PM PDT 24
Peak memory 193716 kb
Host smart-3fbff6c5-60ef-4f71-93a0-635a274c8884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469812886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2469812886
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.4172810745
Short name T798
Test name
Test status
Simulation time 112533519 ps
CPU time 0.74 seconds
Started Mar 21 02:34:19 PM PDT 24
Finished Mar 21 02:34:20 PM PDT 24
Peak memory 196088 kb
Host smart-ce89e805-8b9d-422d-9291-e9b5ce97fbe2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172810745 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.4172810745
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2631763489
Short name T762
Test name
Test status
Simulation time 20615162 ps
CPU time 1.1 seconds
Started Mar 21 02:34:16 PM PDT 24
Finished Mar 21 02:34:18 PM PDT 24
Peak memory 197976 kb
Host smart-4688946f-e094-45e7-8d01-3aa2ad136c70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631763489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2631763489
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1971038420
Short name T823
Test name
Test status
Simulation time 43483983 ps
CPU time 0.87 seconds
Started Mar 21 02:34:20 PM PDT 24
Finished Mar 21 02:34:21 PM PDT 24
Peak memory 197692 kb
Host smart-919d613d-9e29-4bec-8d83-c90e02b8632e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971038420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1971038420
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1345712405
Short name T488
Test name
Test status
Simulation time 30081668 ps
CPU time 0.68 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:38:41 PM PDT 24
Peak memory 193756 kb
Host smart-d02074e3-0124-4896-ab11-0f241accb364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345712405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1345712405
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2634724775
Short name T42
Test name
Test status
Simulation time 14953029 ps
CPU time 0.64 seconds
Started Mar 21 12:38:26 PM PDT 24
Finished Mar 21 12:38:27 PM PDT 24
Peak memory 194544 kb
Host smart-4272dda7-d346-4172-a521-e1eff89ba46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634724775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2634724775
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2649151508
Short name T558
Test name
Test status
Simulation time 456001945 ps
CPU time 25.05 seconds
Started Mar 21 12:38:44 PM PDT 24
Finished Mar 21 12:39:09 PM PDT 24
Peak memory 197904 kb
Host smart-c6b476f2-1b08-44b3-bd20-035b28bffdc7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649151508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2649151508
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.680825699
Short name T469
Test name
Test status
Simulation time 153914798 ps
CPU time 0.97 seconds
Started Mar 21 12:38:52 PM PDT 24
Finished Mar 21 12:38:53 PM PDT 24
Peak memory 197032 kb
Host smart-a1f33550-69f2-4efc-a5af-5c151fa65dc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680825699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.680825699
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2465362271
Short name T448
Test name
Test status
Simulation time 324620909 ps
CPU time 1.51 seconds
Started Mar 21 12:38:39 PM PDT 24
Finished Mar 21 12:38:42 PM PDT 24
Peak memory 195672 kb
Host smart-2c699476-b635-45c9-ba00-c13fa4d69752
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465362271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2465362271
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2956596775
Short name T209
Test name
Test status
Simulation time 134249451 ps
CPU time 1.35 seconds
Started Mar 21 12:38:32 PM PDT 24
Finished Mar 21 12:38:34 PM PDT 24
Peak memory 196560 kb
Host smart-1bb1d312-313f-42a1-ad8f-fdff22f5d5fa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956596775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2956596775
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2488308752
Short name T471
Test name
Test status
Simulation time 120108968 ps
CPU time 0.86 seconds
Started Mar 21 12:38:32 PM PDT 24
Finished Mar 21 12:38:34 PM PDT 24
Peak memory 194984 kb
Host smart-62def176-fb6e-42e9-9ed6-227a5f164b57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488308752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2488308752
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.4112975285
Short name T551
Test name
Test status
Simulation time 68695603 ps
CPU time 0.77 seconds
Started Mar 21 12:38:38 PM PDT 24
Finished Mar 21 12:38:39 PM PDT 24
Peak memory 196484 kb
Host smart-2978bf95-d133-46a6-b00b-238b24a803b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112975285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.4112975285
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2103845946
Short name T470
Test name
Test status
Simulation time 64908998 ps
CPU time 0.92 seconds
Started Mar 21 12:38:51 PM PDT 24
Finished Mar 21 12:38:52 PM PDT 24
Peak memory 195792 kb
Host smart-408807cf-e46f-42c5-95d6-93206aca1fca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103845946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.2103845946
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2662532908
Short name T75
Test name
Test status
Simulation time 259696222 ps
CPU time 2.8 seconds
Started Mar 21 12:38:25 PM PDT 24
Finished Mar 21 12:38:28 PM PDT 24
Peak memory 197892 kb
Host smart-d733e6c9-6907-4d9f-8f94-2c8333e8b429
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662532908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2662532908
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.3684502791
Short name T259
Test name
Test status
Simulation time 126434415 ps
CPU time 1.33 seconds
Started Mar 21 12:38:46 PM PDT 24
Finished Mar 21 12:38:47 PM PDT 24
Peak memory 196636 kb
Host smart-53f3055a-3652-44e5-ba9b-e4bf186564e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684502791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3684502791
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2414103938
Short name T385
Test name
Test status
Simulation time 117264958 ps
CPU time 1.07 seconds
Started Mar 21 12:38:46 PM PDT 24
Finished Mar 21 12:38:47 PM PDT 24
Peak memory 195632 kb
Host smart-a617986d-bbc9-4631-b8c2-af03afbad41b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414103938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2414103938
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2966222991
Short name T190
Test name
Test status
Simulation time 3380768507 ps
CPU time 84.99 seconds
Started Mar 21 12:38:44 PM PDT 24
Finished Mar 21 12:40:09 PM PDT 24
Peak memory 198092 kb
Host smart-2c4abb59-f90e-4cc1-8e7e-74c42318874c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966222991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2966222991
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3461573582
Short name T527
Test name
Test status
Simulation time 28214775 ps
CPU time 0.56 seconds
Started Mar 21 12:38:20 PM PDT 24
Finished Mar 21 12:38:21 PM PDT 24
Peak memory 193744 kb
Host smart-5b4bd887-ec5e-45b3-9a6e-e74cbdd67158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461573582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3461573582
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2381589339
Short name T356
Test name
Test status
Simulation time 44782392 ps
CPU time 0.63 seconds
Started Mar 21 12:38:42 PM PDT 24
Finished Mar 21 12:38:43 PM PDT 24
Peak memory 193840 kb
Host smart-6ad6af35-57c8-4f0b-b4dc-142ffdae84f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381589339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2381589339
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.265797686
Short name T272
Test name
Test status
Simulation time 1776379997 ps
CPU time 23.63 seconds
Started Mar 21 12:38:34 PM PDT 24
Finished Mar 21 12:38:58 PM PDT 24
Peak memory 197896 kb
Host smart-a3749536-e7bd-4224-89f1-bfbe10ed5a26
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265797686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.265797686
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.799883579
Short name T23
Test name
Test status
Simulation time 102519096 ps
CPU time 0.83 seconds
Started Mar 21 12:38:37 PM PDT 24
Finished Mar 21 12:38:39 PM PDT 24
Peak memory 195844 kb
Host smart-3af7844f-077a-4cab-81a8-b6e445a6ba56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799883579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.799883579
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3928454333
Short name T495
Test name
Test status
Simulation time 34007260 ps
CPU time 0.75 seconds
Started Mar 21 12:38:46 PM PDT 24
Finished Mar 21 12:38:47 PM PDT 24
Peak memory 196044 kb
Host smart-fbacc373-fe94-47cd-be41-c64da149bdcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928454333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3928454333
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1901104719
Short name T678
Test name
Test status
Simulation time 152248666 ps
CPU time 3.54 seconds
Started Mar 21 12:38:37 PM PDT 24
Finished Mar 21 12:38:41 PM PDT 24
Peak memory 197952 kb
Host smart-0bb3cd11-612e-40dc-ba31-ec195ad078b0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901104719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1901104719
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2090306223
Short name T618
Test name
Test status
Simulation time 140467309 ps
CPU time 3.15 seconds
Started Mar 21 12:38:42 PM PDT 24
Finished Mar 21 12:38:46 PM PDT 24
Peak memory 196508 kb
Host smart-ccd1dcb6-ac72-459f-a8ec-4832fa778655
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090306223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2090306223
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1418757492
Short name T234
Test name
Test status
Simulation time 54383480 ps
CPU time 1.12 seconds
Started Mar 21 12:38:49 PM PDT 24
Finished Mar 21 12:38:50 PM PDT 24
Peak memory 196628 kb
Host smart-69cf4e54-379d-4ea6-9d1f-1e8373db3de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418757492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1418757492
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1103802866
Short name T14
Test name
Test status
Simulation time 244917670 ps
CPU time 1.1 seconds
Started Mar 21 12:38:38 PM PDT 24
Finished Mar 21 12:38:39 PM PDT 24
Peak memory 196392 kb
Host smart-51c48e1a-e118-44aa-b12e-d7c79d35e0cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103802866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1103802866
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3127234605
Short name T185
Test name
Test status
Simulation time 500171741 ps
CPU time 2.1 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:38:43 PM PDT 24
Peak memory 197840 kb
Host smart-3746ebe0-613a-4d81-8910-28d80d1da94f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127234605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3127234605
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1636630831
Short name T45
Test name
Test status
Simulation time 641482662 ps
CPU time 1.03 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:38:42 PM PDT 24
Peak memory 214672 kb
Host smart-7dca0ace-ced7-49f3-92ca-3901e1472e7c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636630831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1636630831
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3275713558
Short name T343
Test name
Test status
Simulation time 120463671 ps
CPU time 1.04 seconds
Started Mar 21 12:38:27 PM PDT 24
Finished Mar 21 12:38:29 PM PDT 24
Peak memory 196336 kb
Host smart-316d4281-4c5b-48dd-9046-085523669797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275713558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3275713558
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1616586757
Short name T656
Test name
Test status
Simulation time 163148983 ps
CPU time 0.9 seconds
Started Mar 21 12:38:42 PM PDT 24
Finished Mar 21 12:38:43 PM PDT 24
Peak memory 195364 kb
Host smart-f52ca97d-9034-425f-a698-c2cabfb1bc52
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616586757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1616586757
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.126972833
Short name T502
Test name
Test status
Simulation time 7054821338 ps
CPU time 68.8 seconds
Started Mar 21 12:38:36 PM PDT 24
Finished Mar 21 12:39:45 PM PDT 24
Peak memory 198052 kb
Host smart-fefa5c5c-aeb4-4b6d-b7d9-e2d8aeaf0252
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126972833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.126972833
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.4290540005
Short name T503
Test name
Test status
Simulation time 15157746 ps
CPU time 0.6 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:38:56 PM PDT 24
Peak memory 194852 kb
Host smart-261fcf7c-095a-481e-abe2-3b7fe57d82af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290540005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.4290540005
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2603736312
Short name T74
Test name
Test status
Simulation time 35025808 ps
CPU time 0.77 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 196016 kb
Host smart-5b9ede5c-d40f-4144-a917-279a8591903e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603736312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2603736312
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1008194402
Short name T393
Test name
Test status
Simulation time 284226815 ps
CPU time 14.8 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:39:08 PM PDT 24
Peak memory 196692 kb
Host smart-158f935d-4ad7-4c07-84c6-ebad51266bb3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008194402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1008194402
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2363156249
Short name T621
Test name
Test status
Simulation time 47978095 ps
CPU time 0.8 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:38:54 PM PDT 24
Peak memory 195912 kb
Host smart-11c122f2-8d46-4877-ab82-1fdfc37b316f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363156249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2363156249
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2758560138
Short name T182
Test name
Test status
Simulation time 20501564 ps
CPU time 0.78 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 196240 kb
Host smart-31fdfb7a-a679-472b-8f85-b83e0977e217
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758560138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2758560138
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3147060433
Short name T313
Test name
Test status
Simulation time 135840540 ps
CPU time 2.86 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 197916 kb
Host smart-e6b6d54b-d94a-46b4-9634-fb615c0357da
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147060433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3147060433
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3514522767
Short name T696
Test name
Test status
Simulation time 327015817 ps
CPU time 2.04 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 196020 kb
Host smart-5f6bed2e-c44b-4c04-b6e0-fa48c5db9281
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514522767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3514522767
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.563712592
Short name T159
Test name
Test status
Simulation time 107584581 ps
CPU time 0.79 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:38:55 PM PDT 24
Peak memory 195388 kb
Host smart-5555b7bc-9ded-46a9-bf46-c46722b2f465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563712592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.563712592
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.4082437643
Short name T597
Test name
Test status
Simulation time 55129477 ps
CPU time 1.14 seconds
Started Mar 21 12:38:50 PM PDT 24
Finished Mar 21 12:38:51 PM PDT 24
Peak memory 196336 kb
Host smart-e58cb007-a7b6-48bf-be7d-c34f63498394
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082437643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.4082437643
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1225590691
Short name T627
Test name
Test status
Simulation time 456667958 ps
CPU time 5.73 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:39:06 PM PDT 24
Peak memory 197772 kb
Host smart-941fefb9-495f-4f3d-b17d-9d71e5ca3d3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225590691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1225590691
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3841931477
Short name T352
Test name
Test status
Simulation time 56869558 ps
CPU time 0.82 seconds
Started Mar 21 12:38:51 PM PDT 24
Finished Mar 21 12:38:52 PM PDT 24
Peak memory 195852 kb
Host smart-03202b01-7808-4b36-9ae6-e0b0f76fb556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841931477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3841931477
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.922243
Short name T214
Test name
Test status
Simulation time 31406479 ps
CPU time 0.94 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:38:54 PM PDT 24
Peak memory 195528 kb
Host smart-b27003b5-043b-4bde-b596-cd60b7d653f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.922243
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1730231338
Short name T56
Test name
Test status
Simulation time 21897595675 ps
CPU time 80.57 seconds
Started Mar 21 12:38:48 PM PDT 24
Finished Mar 21 12:40:10 PM PDT 24
Peak memory 198040 kb
Host smart-72ea36d1-3325-45a0-b809-cd31cf95341e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730231338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1730231338
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.514741932
Short name T433
Test name
Test status
Simulation time 93909024 ps
CPU time 0.55 seconds
Started Mar 21 12:38:54 PM PDT 24
Finished Mar 21 12:38:56 PM PDT 24
Peak memory 194800 kb
Host smart-e845c2e4-ff91-436a-ac88-8d9c57c464b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514741932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.514741932
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.537825423
Short name T565
Test name
Test status
Simulation time 176005574 ps
CPU time 0.81 seconds
Started Mar 21 12:38:47 PM PDT 24
Finished Mar 21 12:38:48 PM PDT 24
Peak memory 195400 kb
Host smart-6576c313-6293-421f-947a-3cdf26a86d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537825423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.537825423
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2941095432
Short name T270
Test name
Test status
Simulation time 97978995 ps
CPU time 3.15 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:04 PM PDT 24
Peak memory 195348 kb
Host smart-71a20aa8-f37b-4c32-b23a-b15a1f2dd476
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941095432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2941095432
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1060313192
Short name T22
Test name
Test status
Simulation time 69972921 ps
CPU time 0.72 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:38:54 PM PDT 24
Peak memory 194656 kb
Host smart-e121aaad-2a2f-42c5-ad05-2103bcf4a8f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060313192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1060313192
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1483534907
Short name T13
Test name
Test status
Simulation time 159394888 ps
CPU time 0.86 seconds
Started Mar 21 12:38:49 PM PDT 24
Finished Mar 21 12:38:50 PM PDT 24
Peak memory 196068 kb
Host smart-c20c3c6e-6560-4a66-8db0-036a1f631af7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483534907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1483534907
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3636520297
Short name T591
Test name
Test status
Simulation time 281730821 ps
CPU time 2.72 seconds
Started Mar 21 12:38:56 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 197912 kb
Host smart-d8e717b2-572a-429d-84c9-48031ba1e390
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636520297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3636520297
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2239180901
Short name T454
Test name
Test status
Simulation time 123838372 ps
CPU time 1.04 seconds
Started Mar 21 12:38:59 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 195444 kb
Host smart-3998da6f-e0f3-47ae-aeed-d84b2e1fbdeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239180901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2239180901
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.4034030205
Short name T112
Test name
Test status
Simulation time 116636405 ps
CPU time 0.82 seconds
Started Mar 21 12:38:49 PM PDT 24
Finished Mar 21 12:38:50 PM PDT 24
Peak memory 195236 kb
Host smart-2582978c-c8a9-443d-8147-97ab491dd414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034030205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.4034030205
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.4250278104
Short name T334
Test name
Test status
Simulation time 41546037 ps
CPU time 1.1 seconds
Started Mar 21 12:39:10 PM PDT 24
Finished Mar 21 12:39:12 PM PDT 24
Peak memory 195896 kb
Host smart-a75b05f5-9428-4dde-b838-80937d778712
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250278104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.4250278104
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1999866579
Short name T451
Test name
Test status
Simulation time 84327415 ps
CPU time 1.67 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 197836 kb
Host smart-4fa5419a-2b95-4fa8-a7fc-9dbded624eef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999866579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1999866579
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2364515744
Short name T354
Test name
Test status
Simulation time 82132530 ps
CPU time 1.13 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:38:54 PM PDT 24
Peak memory 195544 kb
Host smart-e3db9321-448d-4f22-b6e7-bc8c2eda39ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364515744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2364515744
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2848686523
Short name T682
Test name
Test status
Simulation time 341504869 ps
CPU time 1.39 seconds
Started Mar 21 12:38:50 PM PDT 24
Finished Mar 21 12:38:52 PM PDT 24
Peak memory 196532 kb
Host smart-bc8630c7-f4f3-407c-b126-388a65423cec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848686523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2848686523
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3219440881
Short name T124
Test name
Test status
Simulation time 26330738960 ps
CPU time 188.88 seconds
Started Mar 21 12:38:51 PM PDT 24
Finished Mar 21 12:42:01 PM PDT 24
Peak memory 197948 kb
Host smart-1fcb6dab-390c-4be3-a684-2713276b1a91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219440881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3219440881
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2615799623
Short name T513
Test name
Test status
Simulation time 10967276 ps
CPU time 0.58 seconds
Started Mar 21 12:38:54 PM PDT 24
Finished Mar 21 12:38:56 PM PDT 24
Peak memory 193784 kb
Host smart-25f92f6a-7a0d-4ef8-a264-57159821f06f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615799623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2615799623
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2776641797
Short name T347
Test name
Test status
Simulation time 51722668 ps
CPU time 0.87 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:38:56 PM PDT 24
Peak memory 196392 kb
Host smart-060951ba-118b-439e-9708-c844fd1dc6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776641797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2776641797
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.608615246
Short name T401
Test name
Test status
Simulation time 1513897256 ps
CPU time 13.3 seconds
Started Mar 21 12:38:54 PM PDT 24
Finished Mar 21 12:39:09 PM PDT 24
Peak memory 196680 kb
Host smart-cf2080d5-8c23-44e0-bfa1-4b56d92a08e9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608615246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.608615246
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2360309334
Short name T365
Test name
Test status
Simulation time 231311694 ps
CPU time 0.89 seconds
Started Mar 21 12:38:59 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 196900 kb
Host smart-e4c463ca-0c55-4972-8151-6ea195d136e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360309334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2360309334
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.4057861256
Short name T144
Test name
Test status
Simulation time 67459722 ps
CPU time 0.64 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:38:59 PM PDT 24
Peak memory 194912 kb
Host smart-384e61b5-bc0b-4a33-9c6f-fdeaf07c0994
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057861256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.4057861256
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1073914142
Short name T152
Test name
Test status
Simulation time 134776650 ps
CPU time 1.82 seconds
Started Mar 21 12:38:59 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 196312 kb
Host smart-12c19ee2-a04a-4ed1-b6e9-2d26958e8e8f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073914142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1073914142
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.55805327
Short name T536
Test name
Test status
Simulation time 48529622 ps
CPU time 1.52 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:38:59 PM PDT 24
Peak memory 195836 kb
Host smart-b66fdc30-459d-4c41-987b-e2a046e8e60c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55805327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.55805327
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1098217915
Short name T113
Test name
Test status
Simulation time 121832618 ps
CPU time 1.18 seconds
Started Mar 21 12:38:52 PM PDT 24
Finished Mar 21 12:38:54 PM PDT 24
Peak memory 196952 kb
Host smart-494e2316-46da-4192-9c92-135e8c3f302b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098217915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1098217915
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.497555636
Short name T607
Test name
Test status
Simulation time 71561610 ps
CPU time 1.24 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 196588 kb
Host smart-ceb3a519-0d4f-4a76-b04d-dfca346c9bdf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497555636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.497555636
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3004536418
Short name T33
Test name
Test status
Simulation time 609975440 ps
CPU time 3.09 seconds
Started Mar 21 12:38:51 PM PDT 24
Finished Mar 21 12:38:54 PM PDT 24
Peak memory 197960 kb
Host smart-9b858fe6-4513-4776-af61-45c366493a71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004536418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3004536418
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.225460459
Short name T122
Test name
Test status
Simulation time 218014868 ps
CPU time 1.15 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:38:57 PM PDT 24
Peak memory 195480 kb
Host smart-131503f3-9c62-49e3-b266-41e5049d767e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225460459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.225460459
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2431485658
Short name T212
Test name
Test status
Simulation time 87288345 ps
CPU time 1.19 seconds
Started Mar 21 12:38:59 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 197796 kb
Host smart-55b37bdb-b9f7-454b-80bc-b85fa6e45f57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431485658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2431485658
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3713251411
Short name T432
Test name
Test status
Simulation time 11791429972 ps
CPU time 79.86 seconds
Started Mar 21 12:39:07 PM PDT 24
Finished Mar 21 12:40:27 PM PDT 24
Peak memory 198092 kb
Host smart-e81c58fa-9771-4d8a-80c3-b7d36f2147fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713251411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3713251411
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3537323188
Short name T282
Test name
Test status
Simulation time 38494356 ps
CPU time 0.59 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:38:54 PM PDT 24
Peak memory 193984 kb
Host smart-916bc895-a1d9-4ce7-ac09-b779abf05df9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537323188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3537323188
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1625271940
Short name T146
Test name
Test status
Simulation time 21998500 ps
CPU time 0.69 seconds
Started Mar 21 12:38:51 PM PDT 24
Finished Mar 21 12:38:52 PM PDT 24
Peak memory 194044 kb
Host smart-9b9e2599-93e4-49e4-8db2-3b0e6dc7a426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625271940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1625271940
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.520191947
Short name T216
Test name
Test status
Simulation time 350965370 ps
CPU time 12.86 seconds
Started Mar 21 12:38:51 PM PDT 24
Finished Mar 21 12:39:05 PM PDT 24
Peak memory 197800 kb
Host smart-3ad52703-95e5-4ad5-81cf-f7f5b5debe1a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520191947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.520191947
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3890943069
Short name T641
Test name
Test status
Simulation time 116376845 ps
CPU time 0.8 seconds
Started Mar 21 12:38:52 PM PDT 24
Finished Mar 21 12:38:53 PM PDT 24
Peak memory 195260 kb
Host smart-859c281e-01ef-4b7d-be6a-39df0b23162c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890943069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3890943069
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2790285782
Short name T552
Test name
Test status
Simulation time 226225531 ps
CPU time 0.99 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 195828 kb
Host smart-7c6ac9a3-2f66-48c6-b4d4-5e98282dfdb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790285782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2790285782
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3958366043
Short name T489
Test name
Test status
Simulation time 45455919 ps
CPU time 1.2 seconds
Started Mar 21 12:39:02 PM PDT 24
Finished Mar 21 12:39:04 PM PDT 24
Peak memory 197288 kb
Host smart-48dab84c-fbb7-4c2d-9529-d45573912363
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958366043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3958366043
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1789046734
Short name T220
Test name
Test status
Simulation time 102204095 ps
CPU time 3.18 seconds
Started Mar 21 12:39:03 PM PDT 24
Finished Mar 21 12:39:06 PM PDT 24
Peak memory 196912 kb
Host smart-7bd7a342-c322-486d-8d5b-b4b5e8ba442a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789046734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1789046734
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1612694387
Short name T379
Test name
Test status
Simulation time 31545055 ps
CPU time 1.1 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:38:54 PM PDT 24
Peak memory 195816 kb
Host smart-4c8877c2-c6d3-46d2-875f-d7f3e8e919d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612694387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1612694387
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.4163475724
Short name T449
Test name
Test status
Simulation time 29071825 ps
CPU time 1.11 seconds
Started Mar 21 12:38:59 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 195744 kb
Host smart-3e89bd1f-829b-4e3a-8ffa-771af00e0a37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163475724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.4163475724
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.4098577747
Short name T8
Test name
Test status
Simulation time 150904106 ps
CPU time 2.03 seconds
Started Mar 21 12:38:54 PM PDT 24
Finished Mar 21 12:38:58 PM PDT 24
Peak memory 197696 kb
Host smart-b4f3b7ee-2d95-4e35-8c8e-c399de608510
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098577747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.4098577747
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1738955386
Short name T134
Test name
Test status
Simulation time 84939660 ps
CPU time 1.13 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:38:57 PM PDT 24
Peak memory 196160 kb
Host smart-ede6bc7b-5f0d-48d2-abe2-94d66d7f5637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738955386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1738955386
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1709628161
Short name T381
Test name
Test status
Simulation time 39208712 ps
CPU time 0.78 seconds
Started Mar 21 12:38:56 PM PDT 24
Finished Mar 21 12:38:59 PM PDT 24
Peak memory 195144 kb
Host smart-97b30c5d-8650-420b-808c-7e30a3486571
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709628161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1709628161
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.765489610
Short name T7
Test name
Test status
Simulation time 35868350494 ps
CPU time 193.63 seconds
Started Mar 21 12:39:05 PM PDT 24
Finished Mar 21 12:42:19 PM PDT 24
Peak memory 198036 kb
Host smart-56ebc4bf-671c-433f-ab6a-cd4b931d9241
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765489610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.765489610
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2541526448
Short name T312
Test name
Test status
Simulation time 35302404 ps
CPU time 0.56 seconds
Started Mar 21 12:38:51 PM PDT 24
Finished Mar 21 12:38:52 PM PDT 24
Peak memory 193752 kb
Host smart-ee40ac3a-4ee8-46be-b959-df12d0e3b1be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541526448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2541526448
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.4248321235
Short name T233
Test name
Test status
Simulation time 39785156 ps
CPU time 0.86 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 195252 kb
Host smart-d93b5f66-16e9-4272-aee9-e040a8c3a819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248321235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.4248321235
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3948218365
Short name T179
Test name
Test status
Simulation time 256968267 ps
CPU time 8.61 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:39:07 PM PDT 24
Peak memory 196608 kb
Host smart-e21dc620-16b9-4f2f-af99-6dfe5ccd33c3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948218365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3948218365
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.592771612
Short name T20
Test name
Test status
Simulation time 222093208 ps
CPU time 0.9 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 195780 kb
Host smart-7057dd3e-f523-4f28-858d-9eade5907487
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592771612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.592771612
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.193622646
Short name T541
Test name
Test status
Simulation time 38339644 ps
CPU time 1.02 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 196412 kb
Host smart-c4b368da-c262-4b52-a565-7f820cc73a60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193622646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.193622646
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.485748705
Short name T237
Test name
Test status
Simulation time 138347534 ps
CPU time 3.12 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:04 PM PDT 24
Peak memory 197968 kb
Host smart-c295e022-676f-43bd-9f8e-60e824aed806
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485748705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.485748705
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.112854096
Short name T310
Test name
Test status
Simulation time 417169131 ps
CPU time 3.14 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 196384 kb
Host smart-f9723984-b5e6-497a-be70-7ef551a8fcff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112854096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
112854096
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.256105626
Short name T266
Test name
Test status
Simulation time 176346524 ps
CPU time 1.07 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 196560 kb
Host smart-f82a1b23-9688-4214-bafe-02ca908d4030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256105626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.256105626
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2868560761
Short name T328
Test name
Test status
Simulation time 100311558 ps
CPU time 0.75 seconds
Started Mar 21 12:39:02 PM PDT 24
Finished Mar 21 12:39:03 PM PDT 24
Peak memory 196128 kb
Host smart-327486f8-0002-4373-9083-11915fe8f69b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868560761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2868560761
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1051448489
Short name T21
Test name
Test status
Simulation time 316840708 ps
CPU time 1.71 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 197908 kb
Host smart-ece2aad9-3c01-4406-b002-d7038c0bfe48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051448489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1051448489
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3011452684
Short name T595
Test name
Test status
Simulation time 203368218 ps
CPU time 0.86 seconds
Started Mar 21 12:39:02 PM PDT 24
Finished Mar 21 12:39:03 PM PDT 24
Peak memory 196296 kb
Host smart-77969b40-1758-4ae8-a757-27fee882f816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011452684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3011452684
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3284781719
Short name T410
Test name
Test status
Simulation time 33269778 ps
CPU time 0.99 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 195384 kb
Host smart-7cf140ee-66d9-41f5-991a-3dc8a92576ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284781719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3284781719
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.987868524
Short name T125
Test name
Test status
Simulation time 7853384545 ps
CPU time 110.75 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:40:49 PM PDT 24
Peak memory 198052 kb
Host smart-81c9335a-e3e4-4607-ae55-6450926bb4ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987868524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.987868524
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.323690395
Short name T700
Test name
Test status
Simulation time 56266334533 ps
CPU time 1337.38 seconds
Started Mar 21 12:39:17 PM PDT 24
Finished Mar 21 01:01:35 PM PDT 24
Peak memory 198068 kb
Host smart-453363f9-e485-44a2-a73f-e6851e0ed34c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=323690395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.323690395
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1928411304
Short name T606
Test name
Test status
Simulation time 136557954 ps
CPU time 0.56 seconds
Started Mar 21 12:39:08 PM PDT 24
Finished Mar 21 12:39:09 PM PDT 24
Peak memory 193804 kb
Host smart-fd962924-4339-4ed0-b5c4-fd0bd5770d05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928411304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1928411304
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1859787201
Short name T57
Test name
Test status
Simulation time 41482495 ps
CPU time 0.82 seconds
Started Mar 21 12:38:52 PM PDT 24
Finished Mar 21 12:38:54 PM PDT 24
Peak memory 196396 kb
Host smart-ff62b0c0-6340-4685-971c-e2f397937e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859787201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1859787201
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.4149928751
Short name T323
Test name
Test status
Simulation time 200171299 ps
CPU time 6.43 seconds
Started Mar 21 12:38:59 PM PDT 24
Finished Mar 21 12:39:06 PM PDT 24
Peak memory 196124 kb
Host smart-3df77a78-e215-49e1-ab88-2cb415f87290
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149928751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.4149928751
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.4126694292
Short name T5
Test name
Test status
Simulation time 30836948 ps
CPU time 0.64 seconds
Started Mar 21 12:38:59 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 194164 kb
Host smart-2a7e349f-3be9-4cf6-a204-d298b176d6a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126694292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.4126694292
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3140734229
Short name T632
Test name
Test status
Simulation time 71246267 ps
CPU time 1.2 seconds
Started Mar 21 12:38:56 PM PDT 24
Finished Mar 21 12:38:59 PM PDT 24
Peak memory 195904 kb
Host smart-36395501-8be0-46e0-8fef-5471b0e47b4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140734229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3140734229
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1373036839
Short name T206
Test name
Test status
Simulation time 58533879 ps
CPU time 2.32 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 197972 kb
Host smart-daf9852a-8d5d-4f04-b4ba-073a5c4ff106
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373036839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1373036839
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.318316454
Short name T583
Test name
Test status
Simulation time 124327494 ps
CPU time 3.66 seconds
Started Mar 21 12:38:59 PM PDT 24
Finished Mar 21 12:39:04 PM PDT 24
Peak memory 197912 kb
Host smart-89ffb455-0651-483d-b4aa-799b1eb12b71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318316454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
318316454
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.4120631365
Short name T626
Test name
Test status
Simulation time 21974185 ps
CPU time 0.75 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:38:58 PM PDT 24
Peak memory 194152 kb
Host smart-37085c1e-de87-46bd-8e52-aa1564b6bf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120631365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.4120631365
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.4061580596
Short name T164
Test name
Test status
Simulation time 310505704 ps
CPU time 1.32 seconds
Started Mar 21 12:38:52 PM PDT 24
Finished Mar 21 12:38:54 PM PDT 24
Peak memory 196660 kb
Host smart-4d142920-68d5-4258-930e-868cb1b7a9f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061580596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.4061580596
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1346249721
Short name T129
Test name
Test status
Simulation time 422690481 ps
CPU time 4.75 seconds
Started Mar 21 12:39:11 PM PDT 24
Finished Mar 21 12:39:16 PM PDT 24
Peak memory 197708 kb
Host smart-bdf6d81e-cc27-4755-9771-c7549ca0b11b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346249721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1346249721
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1458848815
Short name T250
Test name
Test status
Simulation time 80840744 ps
CPU time 1.31 seconds
Started Mar 21 12:38:51 PM PDT 24
Finished Mar 21 12:38:52 PM PDT 24
Peak memory 196552 kb
Host smart-e48308ee-6acc-49fe-874f-28b1e4b81d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458848815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1458848815
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1344751812
Short name T208
Test name
Test status
Simulation time 64505769 ps
CPU time 1.27 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:38:57 PM PDT 24
Peak memory 195500 kb
Host smart-e1d1b6bc-6197-440e-8e92-477bf5748bf3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344751812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1344751812
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2573392993
Short name T200
Test name
Test status
Simulation time 27745121824 ps
CPU time 90.86 seconds
Started Mar 21 12:38:59 PM PDT 24
Finished Mar 21 12:40:31 PM PDT 24
Peak memory 198048 kb
Host smart-09d2539b-a558-4002-9858-9b99e70f419a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573392993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2573392993
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.342331389
Short name T426
Test name
Test status
Simulation time 166313111435 ps
CPU time 2494.17 seconds
Started Mar 21 12:38:59 PM PDT 24
Finished Mar 21 01:20:35 PM PDT 24
Peak memory 198120 kb
Host smart-9598c4a5-2a44-42e8-98bf-d381842c0e6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=342331389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.342331389
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.598196635
Short name T186
Test name
Test status
Simulation time 20564978 ps
CPU time 0.59 seconds
Started Mar 21 12:39:08 PM PDT 24
Finished Mar 21 12:39:09 PM PDT 24
Peak memory 194552 kb
Host smart-51a8a10f-ef8b-4056-99cb-ba71a322c0a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598196635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.598196635
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3044136737
Short name T435
Test name
Test status
Simulation time 43871399 ps
CPU time 0.89 seconds
Started Mar 21 12:39:01 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 196496 kb
Host smart-d23ecaca-7215-4cce-829e-22db473a6553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044136737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3044136737
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.224150006
Short name T183
Test name
Test status
Simulation time 1109930232 ps
CPU time 14.29 seconds
Started Mar 21 12:39:05 PM PDT 24
Finished Mar 21 12:39:20 PM PDT 24
Peak memory 196188 kb
Host smart-7ad2af72-b0a9-4263-86c4-bd729ee25c77
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224150006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.224150006
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1340190629
Short name T484
Test name
Test status
Simulation time 871812672 ps
CPU time 0.82 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:38:59 PM PDT 24
Peak memory 196572 kb
Host smart-8abc65f8-c746-4a06-ada2-366d13907329
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340190629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1340190629
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3901243855
Short name T649
Test name
Test status
Simulation time 737437047 ps
CPU time 0.8 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 195292 kb
Host smart-e11b7847-f216-47e9-89a5-a8df0b370548
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901243855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3901243855
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3986414395
Short name T36
Test name
Test status
Simulation time 159578359 ps
CPU time 1.85 seconds
Started Mar 21 12:39:01 PM PDT 24
Finished Mar 21 12:39:03 PM PDT 24
Peak memory 196396 kb
Host smart-631332b7-df98-40a6-b42d-e5f837165d13
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986414395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3986414395
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2299046968
Short name T258
Test name
Test status
Simulation time 171415799 ps
CPU time 2.53 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:03 PM PDT 24
Peak memory 197948 kb
Host smart-669461b9-d54e-44aa-91ae-0826938dadfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299046968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2299046968
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.215383685
Short name T293
Test name
Test status
Simulation time 76849574 ps
CPU time 1.47 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 197884 kb
Host smart-1936d51d-0041-4945-be60-0d1ca05dfc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215383685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.215383685
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2158859203
Short name T465
Test name
Test status
Simulation time 36514533 ps
CPU time 0.87 seconds
Started Mar 21 12:39:01 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 197156 kb
Host smart-372353fc-1325-4a4e-a1f6-37d7c797a266
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158859203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2158859203
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1097429807
Short name T299
Test name
Test status
Simulation time 47827801 ps
CPU time 2.34 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 197804 kb
Host smart-a9dc3c78-878a-4c8b-832b-faa709875eaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097429807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1097429807
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2539403036
Short name T601
Test name
Test status
Simulation time 61408387 ps
CPU time 1.15 seconds
Started Mar 21 12:39:12 PM PDT 24
Finished Mar 21 12:39:14 PM PDT 24
Peak memory 195604 kb
Host smart-ea15db4a-5c77-4046-8e06-231a5e52aa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539403036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2539403036
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1542180333
Short name T170
Test name
Test status
Simulation time 50559938 ps
CPU time 1 seconds
Started Mar 21 12:39:01 PM PDT 24
Finished Mar 21 12:39:03 PM PDT 24
Peak memory 196208 kb
Host smart-1158bbea-2482-4cf6-8780-32904282e352
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542180333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1542180333
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3079384205
Short name T458
Test name
Test status
Simulation time 2537606965 ps
CPU time 32.02 seconds
Started Mar 21 12:39:02 PM PDT 24
Finished Mar 21 12:39:34 PM PDT 24
Peak memory 198024 kb
Host smart-c385b8fa-779a-4e1f-80fc-81eca71e0001
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079384205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3079384205
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2694449685
Short name T245
Test name
Test status
Simulation time 14829139 ps
CPU time 0.63 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 194044 kb
Host smart-e2acdf72-67c1-4e7a-b5dd-a292092b6b89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694449685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2694449685
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3410804839
Short name T475
Test name
Test status
Simulation time 103934727 ps
CPU time 0.91 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 195572 kb
Host smart-666050ff-574f-493c-b150-9b58e4d68d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410804839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3410804839
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1111075533
Short name T444
Test name
Test status
Simulation time 6593817936 ps
CPU time 11.88 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:13 PM PDT 24
Peak memory 196800 kb
Host smart-f10e43bf-4e71-423d-90c8-3a186eb5fd9d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111075533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1111075533
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.4181316146
Short name T702
Test name
Test status
Simulation time 46227901 ps
CPU time 0.65 seconds
Started Mar 21 12:38:59 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 194392 kb
Host smart-6ad29dd9-70f4-463d-bdcd-90d9fe2b46e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181316146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.4181316146
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2600572716
Short name T482
Test name
Test status
Simulation time 315802429 ps
CPU time 1.45 seconds
Started Mar 21 12:38:56 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 197928 kb
Host smart-3d96a28f-e8f6-4f15-a7e5-6120ca0607b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600572716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2600572716
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2684811623
Short name T205
Test name
Test status
Simulation time 105168249 ps
CPU time 2.17 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:38:58 PM PDT 24
Peak memory 198016 kb
Host smart-e25c0d25-e31e-4fee-a86d-1bb8e26e5583
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684811623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2684811623
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.4279213955
Short name T279
Test name
Test status
Simulation time 474608737 ps
CPU time 2.82 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 197084 kb
Host smart-5fbdcb51-5238-4108-ad98-71e065cadae3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279213955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.4279213955
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3655300405
Short name T265
Test name
Test status
Simulation time 52576287 ps
CPU time 1.09 seconds
Started Mar 21 12:38:56 PM PDT 24
Finished Mar 21 12:38:59 PM PDT 24
Peak memory 196484 kb
Host smart-69b105eb-d476-449b-bbac-ea7d89c2297f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655300405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3655300405
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1539431224
Short name T168
Test name
Test status
Simulation time 214844604 ps
CPU time 1.13 seconds
Started Mar 21 12:39:05 PM PDT 24
Finished Mar 21 12:39:06 PM PDT 24
Peak memory 195688 kb
Host smart-3cc3292e-1360-45d9-a5df-05996086dede
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539431224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1539431224
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.896746106
Short name T619
Test name
Test status
Simulation time 367421502 ps
CPU time 1.4 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 197840 kb
Host smart-11386328-6e94-4450-9e16-057984823925
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896746106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.896746106
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1704661381
Short name T305
Test name
Test status
Simulation time 224686362 ps
CPU time 1.31 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 196628 kb
Host smart-bf12a90b-31ec-4778-b2eb-4bbd64aeb3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704661381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1704661381
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3736697647
Short name T73
Test name
Test status
Simulation time 57010254 ps
CPU time 1.07 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 196292 kb
Host smart-18b92ec2-6944-41b7-b07e-e4de97a311b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736697647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3736697647
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3421151173
Short name T413
Test name
Test status
Simulation time 11190090236 ps
CPU time 144.21 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:41:22 PM PDT 24
Peak memory 197992 kb
Host smart-bee209a9-5b35-46e5-834d-3d2adce2ba68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421151173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3421151173
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.211244613
Short name T366
Test name
Test status
Simulation time 13093079 ps
CPU time 0.6 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 193944 kb
Host smart-b7bd46a7-2408-4e73-94ee-7f5050b10329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211244613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.211244613
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1309270542
Short name T684
Test name
Test status
Simulation time 39757355 ps
CPU time 0.68 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:38:56 PM PDT 24
Peak memory 195884 kb
Host smart-d6ff6376-8338-40f3-a68d-bbcb43c23808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309270542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1309270542
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.657938815
Short name T447
Test name
Test status
Simulation time 4788349950 ps
CPU time 14.62 seconds
Started Mar 21 12:38:52 PM PDT 24
Finished Mar 21 12:39:07 PM PDT 24
Peak memory 197136 kb
Host smart-acc75c8d-402f-4c21-b673-032af57a289c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657938815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.657938815
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.858273956
Short name T497
Test name
Test status
Simulation time 87901704 ps
CPU time 0.67 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 194416 kb
Host smart-e7c4d8a5-7503-48de-b7df-f8f1802176a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858273956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.858273956
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1478096287
Short name T61
Test name
Test status
Simulation time 46896163 ps
CPU time 1.19 seconds
Started Mar 21 12:38:52 PM PDT 24
Finished Mar 21 12:38:54 PM PDT 24
Peak memory 197052 kb
Host smart-e4a6b0bd-11c6-4245-8b43-652d19625b15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478096287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1478096287
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2711871028
Short name T587
Test name
Test status
Simulation time 87304672 ps
CPU time 3.4 seconds
Started Mar 21 12:38:56 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 197892 kb
Host smart-70c9a2ad-98ad-4746-b211-35409c5bdb61
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711871028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2711871028
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1135204299
Short name T476
Test name
Test status
Simulation time 148581800 ps
CPU time 2.58 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 196808 kb
Host smart-9ba447cb-9ab1-4f34-8b55-ac22be11243b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135204299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1135204299
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.787083968
Short name T187
Test name
Test status
Simulation time 220767151 ps
CPU time 1.22 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 195640 kb
Host smart-edf2578a-7027-4bde-9c15-4edd5bc7d0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787083968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.787083968
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.4115902739
Short name T177
Test name
Test status
Simulation time 111660665 ps
CPU time 1.18 seconds
Started Mar 21 12:38:59 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 196492 kb
Host smart-4f4dc5e4-e146-4601-a9c2-36fb6e36d9a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115902739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.4115902739
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2538053019
Short name T218
Test name
Test status
Simulation time 663773139 ps
CPU time 5.4 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:39:05 PM PDT 24
Peak memory 197804 kb
Host smart-49a1ba1c-b15f-46d1-a8dc-f341d08d97f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538053019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2538053019
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3729982778
Short name T143
Test name
Test status
Simulation time 46349945 ps
CPU time 0.99 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 196264 kb
Host smart-1f05c887-9426-4ff9-a9c5-775bf605b436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729982778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3729982778
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1847437031
Short name T243
Test name
Test status
Simulation time 448822424 ps
CPU time 1.24 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 196576 kb
Host smart-c5979e4b-d767-4a64-a5ef-e481f9efa0eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847437031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1847437031
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2039358526
Short name T697
Test name
Test status
Simulation time 15651286149 ps
CPU time 201.91 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:42:22 PM PDT 24
Peak memory 197664 kb
Host smart-c04356fb-a2e9-4cbb-9090-246607b59488
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039358526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2039358526
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2282500321
Short name T223
Test name
Test status
Simulation time 14956440 ps
CPU time 0.62 seconds
Started Mar 21 12:39:19 PM PDT 24
Finished Mar 21 12:39:20 PM PDT 24
Peak memory 193744 kb
Host smart-33744335-21fa-4027-bd0b-2b185a27ea3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282500321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2282500321
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3185770855
Short name T487
Test name
Test status
Simulation time 87933474 ps
CPU time 0.74 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:38:59 PM PDT 24
Peak memory 195072 kb
Host smart-c17205b3-0e2d-48bb-af85-9d3384d84909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185770855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3185770855
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3057857762
Short name T466
Test name
Test status
Simulation time 314656225 ps
CPU time 3.37 seconds
Started Mar 21 12:39:26 PM PDT 24
Finished Mar 21 12:39:30 PM PDT 24
Peak memory 195584 kb
Host smart-4695f5a5-3a32-4452-ad30-a1fbf4a29a8c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057857762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3057857762
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3340786726
Short name T699
Test name
Test status
Simulation time 101384961 ps
CPU time 1.14 seconds
Started Mar 21 12:39:19 PM PDT 24
Finished Mar 21 12:39:20 PM PDT 24
Peak memory 196564 kb
Host smart-b391d72c-5930-49b6-90ea-fd6af194f0f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340786726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3340786726
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.125945017
Short name T389
Test name
Test status
Simulation time 269747399 ps
CPU time 0.83 seconds
Started Mar 21 12:39:21 PM PDT 24
Finished Mar 21 12:39:23 PM PDT 24
Peak memory 195408 kb
Host smart-7a545a0f-953a-4989-bb60-986db594ef84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125945017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.125945017
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1452842817
Short name T636
Test name
Test status
Simulation time 361441857 ps
CPU time 3.32 seconds
Started Mar 21 12:39:17 PM PDT 24
Finished Mar 21 12:39:20 PM PDT 24
Peak memory 196872 kb
Host smart-e3840ace-acea-4065-b905-358d2a0b8ac1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452842817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1452842817
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.772060847
Short name T659
Test name
Test status
Simulation time 26012422 ps
CPU time 0.94 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 195820 kb
Host smart-253a0f7b-99ed-4c62-ad48-4d7f607c06fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772060847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.772060847
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.707321123
Short name T692
Test name
Test status
Simulation time 134963331 ps
CPU time 1.32 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:02 PM PDT 24
Peak memory 196868 kb
Host smart-a6513a39-607f-48ab-98e9-8c26ad52dd59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707321123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.707321123
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.852487365
Short name T486
Test name
Test status
Simulation time 355371501 ps
CPU time 4.53 seconds
Started Mar 21 12:39:18 PM PDT 24
Finished Mar 21 12:39:22 PM PDT 24
Peak memory 197844 kb
Host smart-89f93e01-3ee7-4ab1-b6dc-13649a1be1cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852487365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.852487365
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.822932119
Short name T654
Test name
Test status
Simulation time 44075219 ps
CPU time 0.96 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 196036 kb
Host smart-676e6919-5b2e-40f4-9ea0-1d1c1bbacee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822932119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.822932119
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3314528094
Short name T596
Test name
Test status
Simulation time 96927579 ps
CPU time 1.18 seconds
Started Mar 21 12:38:58 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 195660 kb
Host smart-cda930ec-76bc-420b-b5d1-8bf1024dd001
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314528094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3314528094
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.211469001
Short name T202
Test name
Test status
Simulation time 21193231256 ps
CPU time 73.89 seconds
Started Mar 21 12:39:17 PM PDT 24
Finished Mar 21 12:40:31 PM PDT 24
Peak memory 198012 kb
Host smart-f94b32f8-77bf-4c3c-abd3-22e7fca1e26b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211469001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.211469001
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2298495306
Short name T630
Test name
Test status
Simulation time 14767772 ps
CPU time 0.6 seconds
Started Mar 21 12:38:33 PM PDT 24
Finished Mar 21 12:38:34 PM PDT 24
Peak memory 194644 kb
Host smart-41dec302-1f45-4c22-8fd0-7af27287b8bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298495306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2298495306
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3868809411
Short name T512
Test name
Test status
Simulation time 39124905 ps
CPU time 0.78 seconds
Started Mar 21 12:38:39 PM PDT 24
Finished Mar 21 12:38:41 PM PDT 24
Peak memory 195852 kb
Host smart-f3cd7c4d-2dde-45b4-919e-015d1d2d6ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868809411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3868809411
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2855398471
Short name T510
Test name
Test status
Simulation time 445940174 ps
CPU time 5.19 seconds
Started Mar 21 12:38:29 PM PDT 24
Finished Mar 21 12:38:34 PM PDT 24
Peak memory 196672 kb
Host smart-07429f70-e6e2-49bd-82fd-71f5ea06f1b5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855398471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2855398471
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.800213615
Short name T171
Test name
Test status
Simulation time 89610594 ps
CPU time 0.75 seconds
Started Mar 21 12:38:33 PM PDT 24
Finished Mar 21 12:38:34 PM PDT 24
Peak memory 194492 kb
Host smart-61b3eb59-7724-4f29-ba14-d046fb2cf297
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800213615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.800213615
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.669807385
Short name T663
Test name
Test status
Simulation time 342239631 ps
CPU time 1.41 seconds
Started Mar 21 12:38:38 PM PDT 24
Finished Mar 21 12:38:40 PM PDT 24
Peak memory 196804 kb
Host smart-d942f661-fb60-4f82-8da9-d73fcf15025f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669807385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.669807385
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.260556604
Short name T604
Test name
Test status
Simulation time 230952516 ps
CPU time 2.65 seconds
Started Mar 21 12:38:41 PM PDT 24
Finished Mar 21 12:38:43 PM PDT 24
Peak memory 196160 kb
Host smart-cc0cdc6d-993b-4ad4-8a9e-4f8d8f6dafe4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260556604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.260556604
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3563857607
Short name T399
Test name
Test status
Simulation time 507229045 ps
CPU time 2.91 seconds
Started Mar 21 12:38:41 PM PDT 24
Finished Mar 21 12:38:45 PM PDT 24
Peak memory 197256 kb
Host smart-fc42170f-f8b8-4dc9-bfe6-5a52a571f6ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563857607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3563857607
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.160135543
Short name T409
Test name
Test status
Simulation time 27295317 ps
CPU time 0.78 seconds
Started Mar 21 12:38:25 PM PDT 24
Finished Mar 21 12:38:26 PM PDT 24
Peak memory 195348 kb
Host smart-e6c6fb22-c5e4-4294-8c68-c8980f48f999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160135543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.160135543
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1736939220
Short name T540
Test name
Test status
Simulation time 153264727 ps
CPU time 1.03 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:38:41 PM PDT 24
Peak memory 195884 kb
Host smart-11d2453e-c94d-40e6-bea6-2a6c5c609bc4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736939220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1736939220
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3924688889
Short name T628
Test name
Test status
Simulation time 268635906 ps
CPU time 4.61 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:38:45 PM PDT 24
Peak memory 197800 kb
Host smart-253529f7-fb42-4604-ad0c-6bc39292b143
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924688889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3924688889
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3786709386
Short name T54
Test name
Test status
Simulation time 36322182 ps
CPU time 0.81 seconds
Started Mar 21 12:38:38 PM PDT 24
Finished Mar 21 12:38:40 PM PDT 24
Peak memory 213396 kb
Host smart-1a12ead2-0ce5-4cfc-9852-8b9828af7c00
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786709386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3786709386
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2643260423
Short name T211
Test name
Test status
Simulation time 144993770 ps
CPU time 0.9 seconds
Started Mar 21 12:38:32 PM PDT 24
Finished Mar 21 12:38:34 PM PDT 24
Peak memory 196880 kb
Host smart-71efbb7b-659a-49bf-bb93-9cbbfebd2841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643260423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2643260423
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1416268430
Short name T408
Test name
Test status
Simulation time 295792692 ps
CPU time 1.26 seconds
Started Mar 21 12:38:41 PM PDT 24
Finished Mar 21 12:38:43 PM PDT 24
Peak memory 195776 kb
Host smart-2f526a3a-01f7-4a71-86d2-08ef0896ece5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416268430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1416268430
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3349441947
Short name T547
Test name
Test status
Simulation time 61829124804 ps
CPU time 79.5 seconds
Started Mar 21 12:38:41 PM PDT 24
Finished Mar 21 12:40:00 PM PDT 24
Peak memory 197980 kb
Host smart-f1043d19-1808-46f0-bf46-e01e37d2b1b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349441947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3349441947
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.4067343473
Short name T63
Test name
Test status
Simulation time 89234964036 ps
CPU time 1758.5 seconds
Started Mar 21 12:38:35 PM PDT 24
Finished Mar 21 01:07:54 PM PDT 24
Peak memory 198176 kb
Host smart-be70863b-f6d1-490e-a752-8a6567af0f5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4067343473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.4067343473
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.600872345
Short name T225
Test name
Test status
Simulation time 39969663 ps
CPU time 0.57 seconds
Started Mar 21 12:39:19 PM PDT 24
Finished Mar 21 12:39:23 PM PDT 24
Peak memory 194564 kb
Host smart-dc7e9923-2a09-4251-80b0-62851c6cf0ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600872345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.600872345
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2753770173
Short name T653
Test name
Test status
Simulation time 49580601 ps
CPU time 0.9 seconds
Started Mar 21 12:39:17 PM PDT 24
Finished Mar 21 12:39:18 PM PDT 24
Peak memory 196532 kb
Host smart-7c43805f-2c27-453c-ab75-c07b6cb4ed0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753770173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2753770173
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.895746974
Short name T594
Test name
Test status
Simulation time 664553097 ps
CPU time 19.36 seconds
Started Mar 21 12:39:18 PM PDT 24
Finished Mar 21 12:39:37 PM PDT 24
Peak memory 196788 kb
Host smart-b63dc580-3921-4a58-9404-b67b90957cb5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895746974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.895746974
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2402744901
Short name T533
Test name
Test status
Simulation time 98228838 ps
CPU time 0.67 seconds
Started Mar 21 12:39:20 PM PDT 24
Finished Mar 21 12:39:23 PM PDT 24
Peak memory 194960 kb
Host smart-7b227a65-a526-4957-8228-dfbc669e75df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402744901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2402744901
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1247663385
Short name T686
Test name
Test status
Simulation time 66748910 ps
CPU time 1.09 seconds
Started Mar 21 12:39:23 PM PDT 24
Finished Mar 21 12:39:24 PM PDT 24
Peak memory 195880 kb
Host smart-4347413c-f017-4ab1-a82e-2be49205fb76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247663385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1247663385
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.337124013
Short name T167
Test name
Test status
Simulation time 377669587 ps
CPU time 1.72 seconds
Started Mar 21 12:39:19 PM PDT 24
Finished Mar 21 12:39:21 PM PDT 24
Peak memory 196640 kb
Host smart-9c4fca63-3d39-4ee6-a8ed-2cef4f827caf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337124013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.337124013
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1541853961
Short name T574
Test name
Test status
Simulation time 97715217 ps
CPU time 1.7 seconds
Started Mar 21 12:39:23 PM PDT 24
Finished Mar 21 12:39:25 PM PDT 24
Peak memory 195596 kb
Host smart-8e9dfdee-da21-4c30-9c49-f2e613dd8132
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541853961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1541853961
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3894782123
Short name T504
Test name
Test status
Simulation time 51944843 ps
CPU time 0.8 seconds
Started Mar 21 12:39:26 PM PDT 24
Finished Mar 21 12:39:27 PM PDT 24
Peak memory 196064 kb
Host smart-2892a0ab-9ace-430b-9ca4-8679e8b32605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894782123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3894782123
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2652194274
Short name T657
Test name
Test status
Simulation time 38710196 ps
CPU time 1.02 seconds
Started Mar 21 12:39:22 PM PDT 24
Finished Mar 21 12:39:23 PM PDT 24
Peak memory 196072 kb
Host smart-16292533-6e08-48b0-a1b8-e5f910e434dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652194274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2652194274
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1194398338
Short name T478
Test name
Test status
Simulation time 1452916321 ps
CPU time 5.95 seconds
Started Mar 21 12:39:20 PM PDT 24
Finished Mar 21 12:39:28 PM PDT 24
Peak memory 197860 kb
Host smart-30f0ec2b-f80c-4b48-86ce-99d0dbc46fbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194398338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1194398338
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1259726560
Short name T581
Test name
Test status
Simulation time 41056663 ps
CPU time 0.87 seconds
Started Mar 21 12:39:28 PM PDT 24
Finished Mar 21 12:39:29 PM PDT 24
Peak memory 195328 kb
Host smart-ce30bd57-1729-4ba5-b504-01477cc2cca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259726560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1259726560
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1270107995
Short name T184
Test name
Test status
Simulation time 118823407 ps
CPU time 1.11 seconds
Started Mar 21 12:39:29 PM PDT 24
Finished Mar 21 12:39:30 PM PDT 24
Peak memory 195612 kb
Host smart-81ea106b-0e55-46ec-8b89-b77bf08aeabb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270107995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1270107995
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2562969815
Short name T25
Test name
Test status
Simulation time 13809711499 ps
CPU time 43.7 seconds
Started Mar 21 12:39:18 PM PDT 24
Finished Mar 21 12:40:02 PM PDT 24
Peak memory 197972 kb
Host smart-744cb7b1-22e0-4e1b-af55-8c5333a43f3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562969815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2562969815
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1850317477
Short name T276
Test name
Test status
Simulation time 59531920 ps
CPU time 0.6 seconds
Started Mar 21 12:39:22 PM PDT 24
Finished Mar 21 12:39:23 PM PDT 24
Peak memory 193784 kb
Host smart-e711d99c-066c-4b84-bcc6-c1302bdff461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850317477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1850317477
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.4098667186
Short name T481
Test name
Test status
Simulation time 153786368 ps
CPU time 0.93 seconds
Started Mar 21 12:39:18 PM PDT 24
Finished Mar 21 12:39:19 PM PDT 24
Peak memory 195180 kb
Host smart-74c76372-341f-427c-a470-9786153bf1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098667186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.4098667186
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.614959377
Short name T480
Test name
Test status
Simulation time 467477858 ps
CPU time 24.27 seconds
Started Mar 21 12:39:19 PM PDT 24
Finished Mar 21 12:39:46 PM PDT 24
Peak memory 195360 kb
Host smart-f097469a-6aa3-477e-9533-cc2f94f6df6a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614959377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.614959377
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2673229590
Short name T24
Test name
Test status
Simulation time 140598536 ps
CPU time 0.98 seconds
Started Mar 21 12:39:20 PM PDT 24
Finished Mar 21 12:39:23 PM PDT 24
Peak memory 195832 kb
Host smart-b754887d-2244-4c57-aa3e-5e6e1905d1ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673229590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2673229590
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.4116989256
Short name T415
Test name
Test status
Simulation time 172975219 ps
CPU time 1.23 seconds
Started Mar 21 12:39:18 PM PDT 24
Finished Mar 21 12:39:20 PM PDT 24
Peak memory 197008 kb
Host smart-6e211da6-3ae7-4b05-bf8b-1a760ebfc3ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116989256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.4116989256
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.95295829
Short name T337
Test name
Test status
Simulation time 298794597 ps
CPU time 2.42 seconds
Started Mar 21 12:39:21 PM PDT 24
Finished Mar 21 12:39:25 PM PDT 24
Peak memory 197836 kb
Host smart-a82c1e7d-71b5-437d-900b-e0708f455007
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95295829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.gpio_intr_with_filter_rand_intr_event.95295829
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1616753496
Short name T422
Test name
Test status
Simulation time 387972520 ps
CPU time 2.38 seconds
Started Mar 21 12:39:21 PM PDT 24
Finished Mar 21 12:39:24 PM PDT 24
Peak memory 197056 kb
Host smart-3afdb66c-0196-42bf-a98f-1cccb7f3bf08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616753496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1616753496
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1888894225
Short name T380
Test name
Test status
Simulation time 58990445 ps
CPU time 1.32 seconds
Started Mar 21 12:39:27 PM PDT 24
Finished Mar 21 12:39:29 PM PDT 24
Peak memory 196928 kb
Host smart-127c7b22-6924-4592-8983-705adb8e75b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888894225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1888894225
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3258833977
Short name T289
Test name
Test status
Simulation time 57839560 ps
CPU time 1.19 seconds
Started Mar 21 12:39:27 PM PDT 24
Finished Mar 21 12:39:28 PM PDT 24
Peak memory 195972 kb
Host smart-62bd1219-8609-46ef-97dd-fe2322801fe3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258833977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3258833977
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.595301134
Short name T9
Test name
Test status
Simulation time 236014105 ps
CPU time 3.35 seconds
Started Mar 21 12:39:21 PM PDT 24
Finished Mar 21 12:39:26 PM PDT 24
Peak memory 197768 kb
Host smart-2593357c-4c55-45db-a90d-cc65205e87aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595301134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.595301134
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.34424387
Short name T342
Test name
Test status
Simulation time 166941255 ps
CPU time 1.01 seconds
Started Mar 21 12:39:17 PM PDT 24
Finished Mar 21 12:39:18 PM PDT 24
Peak memory 196224 kb
Host smart-b3e1f88a-4b67-4bc5-8b64-e2772d7ded31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34424387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.34424387
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.75332905
Short name T639
Test name
Test status
Simulation time 35335132 ps
CPU time 1.14 seconds
Started Mar 21 12:39:19 PM PDT 24
Finished Mar 21 12:39:23 PM PDT 24
Peak memory 195696 kb
Host smart-5f8f32ca-b842-48f2-94e0-6872bb4d622f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75332905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.75332905
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.178819342
Short name T280
Test name
Test status
Simulation time 17178810513 ps
CPU time 68.16 seconds
Started Mar 21 12:39:18 PM PDT 24
Finished Mar 21 12:40:26 PM PDT 24
Peak memory 198020 kb
Host smart-652d0f6d-d069-4dc1-a925-204f360663dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178819342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.178819342
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1008206407
Short name T438
Test name
Test status
Simulation time 82134288002 ps
CPU time 2018.62 seconds
Started Mar 21 12:39:18 PM PDT 24
Finished Mar 21 01:12:57 PM PDT 24
Peak memory 198164 kb
Host smart-d75c1d1d-f3aa-4831-80a3-b68e29e6ae0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1008206407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1008206407
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2183184792
Short name T709
Test name
Test status
Simulation time 15030528 ps
CPU time 0.6 seconds
Started Mar 21 12:39:33 PM PDT 24
Finished Mar 21 12:39:34 PM PDT 24
Peak memory 193892 kb
Host smart-c5e6895c-049c-48ab-a751-a809e49030c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183184792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2183184792
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.381981280
Short name T154
Test name
Test status
Simulation time 18613654 ps
CPU time 0.74 seconds
Started Mar 21 12:39:21 PM PDT 24
Finished Mar 21 12:39:23 PM PDT 24
Peak memory 194044 kb
Host smart-346a3d46-e56f-47bd-ae59-efbadd0fd072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381981280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.381981280
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.298122217
Short name T371
Test name
Test status
Simulation time 1591526301 ps
CPU time 20.86 seconds
Started Mar 21 12:39:21 PM PDT 24
Finished Mar 21 12:39:43 PM PDT 24
Peak memory 196788 kb
Host smart-b0617184-6dea-4e7b-a3f5-fb850ffdd6d9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298122217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.298122217
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2276693320
Short name T453
Test name
Test status
Simulation time 46297572 ps
CPU time 0.72 seconds
Started Mar 21 12:39:18 PM PDT 24
Finished Mar 21 12:39:19 PM PDT 24
Peak memory 195216 kb
Host smart-1cabe141-a967-45cc-94d0-c95a766fbd0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276693320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2276693320
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.470383185
Short name T238
Test name
Test status
Simulation time 73678422 ps
CPU time 1.27 seconds
Started Mar 21 12:39:23 PM PDT 24
Finished Mar 21 12:39:25 PM PDT 24
Peak memory 197852 kb
Host smart-9d0442a8-3251-44b6-b226-55c34e5ea518
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470383185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.470383185
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.49772415
Short name T390
Test name
Test status
Simulation time 73831682 ps
CPU time 0.97 seconds
Started Mar 21 12:39:18 PM PDT 24
Finished Mar 21 12:39:19 PM PDT 24
Peak memory 196168 kb
Host smart-2f246f12-277a-4c0d-9487-5476b821dd70
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49772415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.gpio_intr_with_filter_rand_intr_event.49772415
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.566068850
Short name T345
Test name
Test status
Simulation time 414042983 ps
CPU time 2.12 seconds
Started Mar 21 12:39:22 PM PDT 24
Finished Mar 21 12:39:24 PM PDT 24
Peak memory 197048 kb
Host smart-aadd1f73-fbf1-42a5-8f68-b5f5345c0d04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566068850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
566068850
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1210177574
Short name T163
Test name
Test status
Simulation time 36849341 ps
CPU time 0.75 seconds
Started Mar 21 12:39:17 PM PDT 24
Finished Mar 21 12:39:18 PM PDT 24
Peak memory 195316 kb
Host smart-9b4398fa-88bd-401b-b08b-c823f5d6aec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210177574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1210177574
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2780930633
Short name T142
Test name
Test status
Simulation time 24002961 ps
CPU time 0.91 seconds
Started Mar 21 12:39:25 PM PDT 24
Finished Mar 21 12:39:26 PM PDT 24
Peak memory 195836 kb
Host smart-a765b94b-b75b-4f57-8f55-ffb101186588
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780930633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2780930633
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.873967397
Short name T241
Test name
Test status
Simulation time 946202562 ps
CPU time 4.76 seconds
Started Mar 21 12:39:29 PM PDT 24
Finished Mar 21 12:39:34 PM PDT 24
Peak memory 197776 kb
Host smart-954a959b-c263-41a5-b972-098797a545e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873967397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.873967397
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2195733199
Short name T221
Test name
Test status
Simulation time 74046410 ps
CPU time 1.29 seconds
Started Mar 21 12:39:22 PM PDT 24
Finished Mar 21 12:39:23 PM PDT 24
Peak memory 195356 kb
Host smart-b6c6128a-530d-4cc4-83aa-240cbd930aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195733199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2195733199
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1252117396
Short name T65
Test name
Test status
Simulation time 1310340149 ps
CPU time 1.13 seconds
Started Mar 21 12:39:18 PM PDT 24
Finished Mar 21 12:39:19 PM PDT 24
Peak memory 195676 kb
Host smart-2f3ec5f7-2442-4e23-b17a-8fa9481fcae4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252117396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1252117396
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1835487430
Short name T431
Test name
Test status
Simulation time 4761230931 ps
CPU time 33.95 seconds
Started Mar 21 12:39:26 PM PDT 24
Finished Mar 21 12:40:00 PM PDT 24
Peak memory 198008 kb
Host smart-581755d2-f7b9-4f3d-8e47-0af8fc928e5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835487430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1835487430
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2148722223
Short name T176
Test name
Test status
Simulation time 13573113 ps
CPU time 0.55 seconds
Started Mar 21 12:39:32 PM PDT 24
Finished Mar 21 12:39:32 PM PDT 24
Peak memory 193792 kb
Host smart-845fb20a-6971-4705-ada8-075b82ffc5b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148722223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2148722223
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2017844662
Short name T260
Test name
Test status
Simulation time 46942392 ps
CPU time 0.77 seconds
Started Mar 21 12:39:23 PM PDT 24
Finished Mar 21 12:39:25 PM PDT 24
Peak memory 194636 kb
Host smart-0cdad030-c65b-4238-ac43-dbb1186e7f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017844662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2017844662
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.928655171
Short name T463
Test name
Test status
Simulation time 872910911 ps
CPU time 27.11 seconds
Started Mar 21 12:39:22 PM PDT 24
Finished Mar 21 12:39:49 PM PDT 24
Peak memory 196680 kb
Host smart-56662442-b44d-4e17-8243-dbfce097086c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928655171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.928655171
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3228671303
Short name T456
Test name
Test status
Simulation time 47961010 ps
CPU time 0.74 seconds
Started Mar 21 12:39:25 PM PDT 24
Finished Mar 21 12:39:25 PM PDT 24
Peak memory 195828 kb
Host smart-1605f4e6-8bdf-4a84-a44a-d7e9a0d259ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228671303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3228671303
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3673159062
Short name T537
Test name
Test status
Simulation time 249944964 ps
CPU time 1.22 seconds
Started Mar 21 12:39:23 PM PDT 24
Finished Mar 21 12:39:25 PM PDT 24
Peak memory 195968 kb
Host smart-935ffba5-83b8-47b5-8c23-e75e260beb3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673159062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3673159062
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.165243458
Short name T353
Test name
Test status
Simulation time 561866337 ps
CPU time 3.39 seconds
Started Mar 21 12:39:32 PM PDT 24
Finished Mar 21 12:39:35 PM PDT 24
Peak memory 196368 kb
Host smart-0edcfbd9-a36a-44c3-8934-764c83dda86e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165243458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.gpio_intr_with_filter_rand_intr_event.165243458
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2483893419
Short name T340
Test name
Test status
Simulation time 68006662 ps
CPU time 1.79 seconds
Started Mar 21 12:39:20 PM PDT 24
Finished Mar 21 12:39:24 PM PDT 24
Peak memory 196828 kb
Host smart-97645053-aa98-440d-af74-8afc6587d0ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483893419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2483893419
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.460444084
Short name T514
Test name
Test status
Simulation time 85466004 ps
CPU time 0.77 seconds
Started Mar 21 12:39:25 PM PDT 24
Finished Mar 21 12:39:26 PM PDT 24
Peak memory 195276 kb
Host smart-299c1616-1721-4559-993d-570d264c25fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460444084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.460444084
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3459119480
Short name T509
Test name
Test status
Simulation time 47637030 ps
CPU time 1.09 seconds
Started Mar 21 12:39:24 PM PDT 24
Finished Mar 21 12:39:26 PM PDT 24
Peak memory 195888 kb
Host smart-54152547-cf9a-43b6-b932-0facf34f149c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459119480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3459119480
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3200721733
Short name T629
Test name
Test status
Simulation time 474549865 ps
CPU time 6.09 seconds
Started Mar 21 12:39:23 PM PDT 24
Finished Mar 21 12:39:29 PM PDT 24
Peak memory 197940 kb
Host smart-673c46ba-06fb-4c14-b1f7-4ba5e1602666
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200721733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3200721733
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2873345414
Short name T642
Test name
Test status
Simulation time 148901009 ps
CPU time 1.12 seconds
Started Mar 21 12:39:28 PM PDT 24
Finished Mar 21 12:39:30 PM PDT 24
Peak memory 195656 kb
Host smart-30e56ae5-b4dd-402e-992e-01f7b3cdbb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873345414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2873345414
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3182330366
Short name T306
Test name
Test status
Simulation time 88208087 ps
CPU time 1.53 seconds
Started Mar 21 12:39:21 PM PDT 24
Finished Mar 21 12:39:24 PM PDT 24
Peak memory 197920 kb
Host smart-d98d9676-7366-4e73-abca-a36d432ce92d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182330366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3182330366
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1770350760
Short name T210
Test name
Test status
Simulation time 12204697201 ps
CPU time 66.44 seconds
Started Mar 21 12:39:32 PM PDT 24
Finished Mar 21 12:40:38 PM PDT 24
Peak memory 198024 kb
Host smart-34019837-5099-41f6-bf0e-a97bd63517de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770350760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1770350760
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1967604009
Short name T196
Test name
Test status
Simulation time 11117094 ps
CPU time 0.56 seconds
Started Mar 21 12:39:24 PM PDT 24
Finished Mar 21 12:39:25 PM PDT 24
Peak memory 193800 kb
Host smart-b8b439d5-dda1-41fe-bd4a-803c0b645e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967604009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1967604009
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1913948616
Short name T62
Test name
Test status
Simulation time 187862717 ps
CPU time 0.9 seconds
Started Mar 21 12:39:24 PM PDT 24
Finished Mar 21 12:39:25 PM PDT 24
Peak memory 196180 kb
Host smart-fafe19f9-0098-4817-abcc-9eaeca5f89a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913948616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1913948616
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1608772730
Short name T694
Test name
Test status
Simulation time 1001201462 ps
CPU time 27.22 seconds
Started Mar 21 12:39:24 PM PDT 24
Finished Mar 21 12:39:52 PM PDT 24
Peak memory 196736 kb
Host smart-02d1495d-ac0c-479a-9073-99d5f740ec9c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608772730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1608772730
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2143159606
Short name T608
Test name
Test status
Simulation time 22484569 ps
CPU time 0.65 seconds
Started Mar 21 12:39:25 PM PDT 24
Finished Mar 21 12:39:26 PM PDT 24
Peak memory 194536 kb
Host smart-8e95a785-7b6b-4a3a-9828-17eb6f9d9aba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143159606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2143159606
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.4114967353
Short name T479
Test name
Test status
Simulation time 36004399 ps
CPU time 0.64 seconds
Started Mar 21 12:39:26 PM PDT 24
Finished Mar 21 12:39:27 PM PDT 24
Peak memory 195008 kb
Host smart-e205bcae-106f-443f-aba5-00fe9e01d7cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114967353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.4114967353
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.99841963
Short name T228
Test name
Test status
Simulation time 99118165 ps
CPU time 3.61 seconds
Started Mar 21 12:39:28 PM PDT 24
Finished Mar 21 12:39:32 PM PDT 24
Peak memory 197868 kb
Host smart-4317d6ed-85ca-486a-9936-a3c5fbc14ff8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99841963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.gpio_intr_with_filter_rand_intr_event.99841963
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.646652329
Short name T612
Test name
Test status
Simulation time 155326501 ps
CPU time 3.18 seconds
Started Mar 21 12:39:29 PM PDT 24
Finished Mar 21 12:39:32 PM PDT 24
Peak memory 196892 kb
Host smart-3fd71a9f-a2ae-4d6b-ac97-3d5691840f5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646652329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
646652329
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3643701963
Short name T688
Test name
Test status
Simulation time 75018060 ps
CPU time 0.77 seconds
Started Mar 21 12:39:30 PM PDT 24
Finished Mar 21 12:39:31 PM PDT 24
Peak memory 195424 kb
Host smart-cbd12da9-bdfa-4377-8d6d-38edbe4b776d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643701963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3643701963
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1663874421
Short name T314
Test name
Test status
Simulation time 38045473 ps
CPU time 0.92 seconds
Started Mar 21 12:39:25 PM PDT 24
Finished Mar 21 12:39:26 PM PDT 24
Peak memory 196448 kb
Host smart-0187e836-510f-4a7e-b896-87384790011b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663874421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1663874421
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.4054532064
Short name T445
Test name
Test status
Simulation time 54922753 ps
CPU time 2.56 seconds
Started Mar 21 12:39:29 PM PDT 24
Finished Mar 21 12:39:32 PM PDT 24
Peak memory 197796 kb
Host smart-fac9d1a7-903c-4608-a6bf-ae9e1091a89f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054532064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.4054532064
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.4167454216
Short name T188
Test name
Test status
Simulation time 55362044 ps
CPU time 1.13 seconds
Started Mar 21 12:39:25 PM PDT 24
Finished Mar 21 12:39:26 PM PDT 24
Peak memory 195648 kb
Host smart-ed66091b-5efa-41ed-a017-c22fef4df2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167454216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.4167454216
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.865332113
Short name T290
Test name
Test status
Simulation time 68598685 ps
CPU time 0.83 seconds
Started Mar 21 12:39:29 PM PDT 24
Finished Mar 21 12:39:30 PM PDT 24
Peak memory 195144 kb
Host smart-02ef4f4a-4748-44a4-9bd1-12bc98e1c65d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865332113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.865332113
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.4028568233
Short name T151
Test name
Test status
Simulation time 11905439603 ps
CPU time 83.93 seconds
Started Mar 21 12:39:45 PM PDT 24
Finished Mar 21 12:41:09 PM PDT 24
Peak memory 197904 kb
Host smart-cc4eb6d2-49e0-4a99-9d7a-ecc60c706cb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028568233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.4028568233
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2251811253
Short name T707
Test name
Test status
Simulation time 22380705 ps
CPU time 0.56 seconds
Started Mar 21 12:39:44 PM PDT 24
Finished Mar 21 12:39:44 PM PDT 24
Peak memory 193768 kb
Host smart-b05b3c31-f15e-4d9b-b483-54bc7fde4397
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251811253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2251811253
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1975901031
Short name T439
Test name
Test status
Simulation time 87394428 ps
CPU time 0.67 seconds
Started Mar 21 12:39:29 PM PDT 24
Finished Mar 21 12:39:30 PM PDT 24
Peak memory 193992 kb
Host smart-8a3f9482-2055-4045-81e2-6228abe67f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975901031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1975901031
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.272799580
Short name T150
Test name
Test status
Simulation time 463199775 ps
CPU time 23.01 seconds
Started Mar 21 12:39:30 PM PDT 24
Finished Mar 21 12:39:53 PM PDT 24
Peak memory 197780 kb
Host smart-ec2692b1-5d4b-4682-ab40-8626faad3bae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272799580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.272799580
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.439830158
Short name T349
Test name
Test status
Simulation time 287312492 ps
CPU time 1.05 seconds
Started Mar 21 12:39:29 PM PDT 24
Finished Mar 21 12:39:30 PM PDT 24
Peak memory 197812 kb
Host smart-106d0be7-bf9a-48bf-a862-e92e0aaff25c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439830158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.439830158
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1929273156
Short name T126
Test name
Test status
Simulation time 106631148 ps
CPU time 1.45 seconds
Started Mar 21 12:39:27 PM PDT 24
Finished Mar 21 12:39:29 PM PDT 24
Peak memory 197868 kb
Host smart-aa75def8-369e-4923-9331-9eadd853f76d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929273156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1929273156
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2713053161
Short name T425
Test name
Test status
Simulation time 49148270 ps
CPU time 1.97 seconds
Started Mar 21 12:39:29 PM PDT 24
Finished Mar 21 12:39:31 PM PDT 24
Peak memory 197448 kb
Host smart-13fc3831-9a1f-436f-9d40-0cf46f582783
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713053161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2713053161
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3706916124
Short name T224
Test name
Test status
Simulation time 133838278 ps
CPU time 2.14 seconds
Started Mar 21 12:39:29 PM PDT 24
Finished Mar 21 12:39:32 PM PDT 24
Peak memory 195876 kb
Host smart-687126e6-1d21-4303-b00f-91c73dc9ad3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706916124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3706916124
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2690406915
Short name T400
Test name
Test status
Simulation time 49162243 ps
CPU time 1.12 seconds
Started Mar 21 12:39:28 PM PDT 24
Finished Mar 21 12:39:29 PM PDT 24
Peak memory 195992 kb
Host smart-625df2a9-a825-41ad-91a2-faf1c4ff203e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690406915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2690406915
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.4200833183
Short name T128
Test name
Test status
Simulation time 97153969 ps
CPU time 0.79 seconds
Started Mar 21 12:39:34 PM PDT 24
Finished Mar 21 12:39:35 PM PDT 24
Peak memory 195404 kb
Host smart-3160cbba-9ef7-4a44-8ff6-5cb768f1f9f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200833183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.4200833183
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.148110913
Short name T398
Test name
Test status
Simulation time 235111708 ps
CPU time 4.11 seconds
Started Mar 21 12:39:26 PM PDT 24
Finished Mar 21 12:39:31 PM PDT 24
Peak memory 197828 kb
Host smart-107910ed-8f15-4f7e-8478-30cf36f41584
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148110913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.148110913
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.4200728216
Short name T468
Test name
Test status
Simulation time 40682349 ps
CPU time 1.09 seconds
Started Mar 21 12:39:32 PM PDT 24
Finished Mar 21 12:39:33 PM PDT 24
Peak memory 195656 kb
Host smart-cdd88241-ee60-4a70-8aaf-460b0b02c7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200728216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.4200728216
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.112619630
Short name T457
Test name
Test status
Simulation time 63390434 ps
CPU time 0.81 seconds
Started Mar 21 12:39:31 PM PDT 24
Finished Mar 21 12:39:32 PM PDT 24
Peak memory 195724 kb
Host smart-ea0f6e54-c397-451c-9aed-2d75405ef4aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112619630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.112619630
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.4216959391
Short name T362
Test name
Test status
Simulation time 2981693503 ps
CPU time 40.67 seconds
Started Mar 21 12:39:45 PM PDT 24
Finished Mar 21 12:40:31 PM PDT 24
Peak memory 198080 kb
Host smart-e1c8033a-e867-4d8e-9120-c4cecd52e5a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216959391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.4216959391
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.75850142
Short name T416
Test name
Test status
Simulation time 78659613 ps
CPU time 0.6 seconds
Started Mar 21 12:39:32 PM PDT 24
Finished Mar 21 12:39:32 PM PDT 24
Peak memory 194456 kb
Host smart-47e76851-ced4-4137-81d5-b3f2639263e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75850142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.75850142
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1568747023
Short name T147
Test name
Test status
Simulation time 27987290 ps
CPU time 0.74 seconds
Started Mar 21 12:39:30 PM PDT 24
Finished Mar 21 12:39:31 PM PDT 24
Peak memory 195776 kb
Host smart-e36455b8-7a7e-4eee-8be9-eab9a4f6d077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568747023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1568747023
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2719111307
Short name T452
Test name
Test status
Simulation time 187805152 ps
CPU time 10 seconds
Started Mar 21 12:39:45 PM PDT 24
Finished Mar 21 12:39:55 PM PDT 24
Peak memory 196692 kb
Host smart-2c18fb9d-6445-4d21-a29b-78f846e1cfc6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719111307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2719111307
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2470610764
Short name T459
Test name
Test status
Simulation time 146855495 ps
CPU time 0.78 seconds
Started Mar 21 12:39:44 PM PDT 24
Finished Mar 21 12:39:45 PM PDT 24
Peak memory 195876 kb
Host smart-28e320c9-4526-4898-958b-ede4d202df0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470610764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2470610764
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.64712185
Short name T443
Test name
Test status
Simulation time 90446741 ps
CPU time 1.31 seconds
Started Mar 21 12:39:33 PM PDT 24
Finished Mar 21 12:39:35 PM PDT 24
Peak memory 196004 kb
Host smart-d8031d5f-46e1-4c5b-a492-b9f6b8d8b57e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64712185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.64712185
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.445809882
Short name T329
Test name
Test status
Simulation time 166589272 ps
CPU time 3.38 seconds
Started Mar 21 12:39:46 PM PDT 24
Finished Mar 21 12:39:51 PM PDT 24
Peak memory 197912 kb
Host smart-a6899a5c-dbf9-46fa-bdc9-c02d0e61e634
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445809882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.445809882
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.596746111
Short name T572
Test name
Test status
Simulation time 208392973 ps
CPU time 3.4 seconds
Started Mar 21 12:39:37 PM PDT 24
Finished Mar 21 12:39:40 PM PDT 24
Peak memory 197884 kb
Host smart-a1058dd8-a1d0-4af5-b576-caea4896131d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596746111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
596746111
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1204500565
Short name T321
Test name
Test status
Simulation time 15831953 ps
CPU time 0.75 seconds
Started Mar 21 12:39:32 PM PDT 24
Finished Mar 21 12:39:33 PM PDT 24
Peak memory 195956 kb
Host smart-80d5e089-b17d-49ba-8abc-33f05fe6a75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204500565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1204500565
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2356124014
Short name T650
Test name
Test status
Simulation time 145382414 ps
CPU time 0.92 seconds
Started Mar 21 12:39:30 PM PDT 24
Finished Mar 21 12:39:31 PM PDT 24
Peak memory 196540 kb
Host smart-212b33d4-b8cd-4e3a-8e9f-2e2337fe0080
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356124014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2356124014
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1094039494
Short name T661
Test name
Test status
Simulation time 278477175 ps
CPU time 2.08 seconds
Started Mar 21 12:39:30 PM PDT 24
Finished Mar 21 12:39:32 PM PDT 24
Peak memory 197840 kb
Host smart-c46d3202-7dec-42d4-bed4-a47f45e5fcac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094039494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1094039494
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3674099753
Short name T166
Test name
Test status
Simulation time 84642350 ps
CPU time 1.24 seconds
Started Mar 21 12:39:29 PM PDT 24
Finished Mar 21 12:39:30 PM PDT 24
Peak memory 195356 kb
Host smart-efba4849-ca9f-4c74-81c2-cf94648e4970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674099753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3674099753
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3714024455
Short name T315
Test name
Test status
Simulation time 79329932 ps
CPU time 1.13 seconds
Started Mar 21 12:39:30 PM PDT 24
Finished Mar 21 12:39:31 PM PDT 24
Peak memory 196288 kb
Host smart-cdd5b25e-517b-4b1f-9b54-fe779f87e020
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714024455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3714024455
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_alert_test.329587305
Short name T464
Test name
Test status
Simulation time 19056605 ps
CPU time 0.65 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 194560 kb
Host smart-f16c11b3-22c5-4f5f-b69e-e625221a0f1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329587305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.329587305
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2298228528
Short name T710
Test name
Test status
Simulation time 34708200 ps
CPU time 0.87 seconds
Started Mar 21 12:39:37 PM PDT 24
Finished Mar 21 12:39:38 PM PDT 24
Peak memory 195284 kb
Host smart-96cae936-716b-4034-93cb-1727dc2aae91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298228528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2298228528
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2265857005
Short name T145
Test name
Test status
Simulation time 597964248 ps
CPU time 10.71 seconds
Started Mar 21 12:39:35 PM PDT 24
Finished Mar 21 12:39:46 PM PDT 24
Peak memory 195328 kb
Host smart-110d38d5-41ff-4fa5-89a2-cc30e12b8eaa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265857005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2265857005
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1810974013
Short name T283
Test name
Test status
Simulation time 214003447 ps
CPU time 1.11 seconds
Started Mar 21 12:39:38 PM PDT 24
Finished Mar 21 12:39:39 PM PDT 24
Peak memory 196508 kb
Host smart-e886fcf8-ee49-4ca6-bce4-9fba6dc2874b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810974013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1810974013
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2535182521
Short name T668
Test name
Test status
Simulation time 56003839 ps
CPU time 0.68 seconds
Started Mar 21 12:39:32 PM PDT 24
Finished Mar 21 12:39:33 PM PDT 24
Peak memory 194112 kb
Host smart-3606b0c5-2984-4763-a520-820dfdc11116
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535182521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2535182521
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2628684465
Short name T580
Test name
Test status
Simulation time 35664144 ps
CPU time 1.44 seconds
Started Mar 21 12:39:30 PM PDT 24
Finished Mar 21 12:39:32 PM PDT 24
Peak memory 196700 kb
Host smart-d6344893-c29c-4faa-8a34-76aec3fbf3e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628684465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2628684465
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3347838573
Short name T322
Test name
Test status
Simulation time 242644252 ps
CPU time 1.02 seconds
Started Mar 21 12:39:31 PM PDT 24
Finished Mar 21 12:39:32 PM PDT 24
Peak memory 195600 kb
Host smart-e6f50be5-6a20-4269-a92d-ac1d39b5d9e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347838573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3347838573
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.633855370
Short name T492
Test name
Test status
Simulation time 85639328 ps
CPU time 0.65 seconds
Started Mar 21 12:39:40 PM PDT 24
Finished Mar 21 12:39:41 PM PDT 24
Peak memory 194096 kb
Host smart-2da1a479-cc42-4682-b7b3-ffe602918b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633855370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.633855370
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1099540638
Short name T450
Test name
Test status
Simulation time 177549556 ps
CPU time 0.99 seconds
Started Mar 21 12:39:33 PM PDT 24
Finished Mar 21 12:39:34 PM PDT 24
Peak memory 195828 kb
Host smart-54fe19c7-3484-4c00-a788-8b5306d0baad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099540638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1099540638
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3478021935
Short name T424
Test name
Test status
Simulation time 35396013 ps
CPU time 1.7 seconds
Started Mar 21 12:39:37 PM PDT 24
Finished Mar 21 12:39:38 PM PDT 24
Peak memory 197824 kb
Host smart-f36ec097-b29f-4789-9bdf-8ab1a3b96c50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478021935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3478021935
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.344237242
Short name T304
Test name
Test status
Simulation time 93896430 ps
CPU time 0.86 seconds
Started Mar 21 12:39:39 PM PDT 24
Finished Mar 21 12:39:40 PM PDT 24
Peak memory 195312 kb
Host smart-d7f815e9-44d0-4cc2-987f-edde665f5440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344237242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.344237242
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2361140367
Short name T673
Test name
Test status
Simulation time 235686881 ps
CPU time 1.15 seconds
Started Mar 21 12:39:41 PM PDT 24
Finished Mar 21 12:39:43 PM PDT 24
Peak memory 195504 kb
Host smart-6d7eefa0-1f87-4f19-8822-a87976bcbfd3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361140367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2361140367
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.97135218
Short name T638
Test name
Test status
Simulation time 115687919380 ps
CPU time 134.08 seconds
Started Mar 21 12:39:43 PM PDT 24
Finished Mar 21 12:41:57 PM PDT 24
Peak memory 198084 kb
Host smart-8c942fe2-33c3-4f00-8ee3-70bf4f05b078
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97135218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gp
io_stress_all.97135218
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3677642147
Short name T341
Test name
Test status
Simulation time 24043212 ps
CPU time 0.61 seconds
Started Mar 21 12:39:35 PM PDT 24
Finished Mar 21 12:39:36 PM PDT 24
Peak memory 193944 kb
Host smart-5a51d8b6-830b-4b92-997f-8542258b818b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677642147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3677642147
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.4208096717
Short name T635
Test name
Test status
Simulation time 36134911 ps
CPU time 0.84 seconds
Started Mar 21 12:39:34 PM PDT 24
Finished Mar 21 12:39:35 PM PDT 24
Peak memory 195140 kb
Host smart-6e63cb03-b554-4eac-984c-013e06541f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208096717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.4208096717
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1971240710
Short name T178
Test name
Test status
Simulation time 337722022 ps
CPU time 12.28 seconds
Started Mar 21 12:39:31 PM PDT 24
Finished Mar 21 12:39:44 PM PDT 24
Peak memory 196816 kb
Host smart-45738a52-3deb-4fb6-af21-1bfd14bc3769
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971240710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1971240710
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3920166858
Short name T4
Test name
Test status
Simulation time 89596464 ps
CPU time 1.05 seconds
Started Mar 21 12:39:34 PM PDT 24
Finished Mar 21 12:39:35 PM PDT 24
Peak memory 196504 kb
Host smart-cb9ef0e8-f4b9-4fea-a5f5-944a6249e2f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920166858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3920166858
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.447344773
Short name T419
Test name
Test status
Simulation time 1033321756 ps
CPU time 1.36 seconds
Started Mar 21 12:39:42 PM PDT 24
Finished Mar 21 12:39:43 PM PDT 24
Peak memory 197852 kb
Host smart-bcc82ec7-343b-426d-a3cc-bf865bfcf130
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447344773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.447344773
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2807622515
Short name T339
Test name
Test status
Simulation time 174759757 ps
CPU time 1.95 seconds
Started Mar 21 12:39:32 PM PDT 24
Finished Mar 21 12:39:35 PM PDT 24
Peak memory 196516 kb
Host smart-2788aa58-895b-4295-935f-5179e041e550
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807622515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2807622515
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.158524684
Short name T623
Test name
Test status
Simulation time 288149618 ps
CPU time 3.06 seconds
Started Mar 21 12:39:36 PM PDT 24
Finished Mar 21 12:39:39 PM PDT 24
Peak memory 195652 kb
Host smart-9636d594-a3d6-4417-9c24-6c1ef62ecbf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158524684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
158524684
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3547291014
Short name T336
Test name
Test status
Simulation time 120896621 ps
CPU time 0.93 seconds
Started Mar 21 12:39:33 PM PDT 24
Finished Mar 21 12:39:34 PM PDT 24
Peak memory 195876 kb
Host smart-30b8f31c-682f-435a-a076-d7027c201759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547291014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3547291014
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.209262802
Short name T198
Test name
Test status
Simulation time 39245289 ps
CPU time 0.79 seconds
Started Mar 21 12:39:45 PM PDT 24
Finished Mar 21 12:39:46 PM PDT 24
Peak memory 195252 kb
Host smart-4058a263-f154-4cdf-9fb9-c3fd6fa8f893
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209262802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.209262802
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.351780422
Short name T76
Test name
Test status
Simulation time 1144255843 ps
CPU time 1.48 seconds
Started Mar 21 12:39:47 PM PDT 24
Finished Mar 21 12:39:48 PM PDT 24
Peak memory 197912 kb
Host smart-926be0c8-9e23-48ed-a201-88d701b87295
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351780422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.351780422
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.4163099090
Short name T498
Test name
Test status
Simulation time 38684804 ps
CPU time 1.1 seconds
Started Mar 21 12:39:31 PM PDT 24
Finished Mar 21 12:39:32 PM PDT 24
Peak memory 196140 kb
Host smart-f5731013-68e0-4901-80aa-088713a7368d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163099090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.4163099090
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.853691364
Short name T277
Test name
Test status
Simulation time 181680816 ps
CPU time 1 seconds
Started Mar 21 12:39:43 PM PDT 24
Finished Mar 21 12:39:44 PM PDT 24
Peak memory 197156 kb
Host smart-64e9a9d0-827c-4dde-9cc2-f18dd86b1f7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853691364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.853691364
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.4177627512
Short name T633
Test name
Test status
Simulation time 23306978791 ps
CPU time 88.97 seconds
Started Mar 21 12:39:46 PM PDT 24
Finished Mar 21 12:41:15 PM PDT 24
Peak memory 197964 kb
Host smart-3f659ad7-968f-4965-9ef7-0d604eb4b025
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177627512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.4177627512
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2904573798
Short name T17
Test name
Test status
Simulation time 54351325166 ps
CPU time 764.93 seconds
Started Mar 21 12:39:38 PM PDT 24
Finished Mar 21 12:52:23 PM PDT 24
Peak memory 198064 kb
Host smart-a0e24995-3cc3-46a3-945f-df82ba9fdbfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2904573798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2904573798
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1735336314
Short name T388
Test name
Test status
Simulation time 21349901 ps
CPU time 0.57 seconds
Started Mar 21 12:39:46 PM PDT 24
Finished Mar 21 12:39:47 PM PDT 24
Peak memory 193784 kb
Host smart-7d167c7a-5647-4a43-b0a5-28f751b50a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735336314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1735336314
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.385786598
Short name T12
Test name
Test status
Simulation time 257701591 ps
CPU time 0.8 seconds
Started Mar 21 12:39:39 PM PDT 24
Finished Mar 21 12:39:39 PM PDT 24
Peak memory 195220 kb
Host smart-fe15466c-780b-45bc-99df-ffe4c1a2cab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385786598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.385786598
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2006477582
Short name T374
Test name
Test status
Simulation time 246384144 ps
CPU time 9.17 seconds
Started Mar 21 12:39:35 PM PDT 24
Finished Mar 21 12:39:44 PM PDT 24
Peak memory 195288 kb
Host smart-a9ca0490-d401-4f89-a1da-70ec453887f0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006477582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2006477582
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1213641030
Short name T369
Test name
Test status
Simulation time 96503891 ps
CPU time 0.66 seconds
Started Mar 21 12:39:35 PM PDT 24
Finished Mar 21 12:39:35 PM PDT 24
Peak memory 194284 kb
Host smart-cf53076d-8d14-4d93-9464-bf34407fc1c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213641030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1213641030
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3637996696
Short name T520
Test name
Test status
Simulation time 189258471 ps
CPU time 1.35 seconds
Started Mar 21 12:39:45 PM PDT 24
Finished Mar 21 12:39:52 PM PDT 24
Peak memory 197048 kb
Host smart-91475008-28ee-4863-ab3f-fe20341223f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637996696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3637996696
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3377228740
Short name T338
Test name
Test status
Simulation time 65448021 ps
CPU time 2.44 seconds
Started Mar 21 12:39:47 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 197948 kb
Host smart-1eacc293-0828-4c2b-9acb-feea70b5186a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377228740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3377228740
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.954265665
Short name T207
Test name
Test status
Simulation time 220657473 ps
CPU time 1.5 seconds
Started Mar 21 12:39:42 PM PDT 24
Finished Mar 21 12:39:44 PM PDT 24
Peak memory 195924 kb
Host smart-58e5e181-d27d-4d59-acda-e54ac4e75cc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954265665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
954265665
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.4273932529
Short name T246
Test name
Test status
Simulation time 686348625 ps
CPU time 1.19 seconds
Started Mar 21 12:39:43 PM PDT 24
Finished Mar 21 12:39:44 PM PDT 24
Peak memory 197856 kb
Host smart-ee048929-1acc-49b7-9153-040f3481936b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273932529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.4273932529
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.362032473
Short name T27
Test name
Test status
Simulation time 181122200 ps
CPU time 1.11 seconds
Started Mar 21 12:39:33 PM PDT 24
Finished Mar 21 12:39:34 PM PDT 24
Peak memory 195924 kb
Host smart-ba58618c-a017-44d2-810c-cd5748c4c9c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362032473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.362032473
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.4125971780
Short name T404
Test name
Test status
Simulation time 536127227 ps
CPU time 6.37 seconds
Started Mar 21 12:39:46 PM PDT 24
Finished Mar 21 12:39:53 PM PDT 24
Peak memory 197804 kb
Host smart-27b68063-d0eb-456e-8cc3-523d8841e2b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125971780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.4125971780
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.4113016241
Short name T519
Test name
Test status
Simulation time 33773664 ps
CPU time 0.84 seconds
Started Mar 21 12:39:31 PM PDT 24
Finished Mar 21 12:39:32 PM PDT 24
Peak memory 195900 kb
Host smart-b68ffd48-e890-4981-800d-5243944c4078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113016241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.4113016241
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3994037345
Short name T549
Test name
Test status
Simulation time 80851161 ps
CPU time 1.01 seconds
Started Mar 21 12:39:35 PM PDT 24
Finished Mar 21 12:39:36 PM PDT 24
Peak memory 196276 kb
Host smart-84601841-0f13-40a0-a690-5d3fd79401db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994037345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3994037345
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2930671876
Short name T620
Test name
Test status
Simulation time 9096501591 ps
CPU time 68.42 seconds
Started Mar 21 12:39:47 PM PDT 24
Finished Mar 21 12:40:56 PM PDT 24
Peak memory 198032 kb
Host smart-1b4d66bc-8b9c-427d-aa36-02d56c7119d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930671876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2930671876
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.4228197508
Short name T71
Test name
Test status
Simulation time 83934755299 ps
CPU time 931.94 seconds
Started Mar 21 12:39:38 PM PDT 24
Finished Mar 21 12:55:10 PM PDT 24
Peak memory 198028 kb
Host smart-0714a839-4966-4ce8-af6e-2f3581327fa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4228197508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.4228197508
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.600407818
Short name T382
Test name
Test status
Simulation time 26514886 ps
CPU time 0.67 seconds
Started Mar 21 12:38:47 PM PDT 24
Finished Mar 21 12:38:48 PM PDT 24
Peak memory 194740 kb
Host smart-62ffabc9-3739-49d3-bbf7-1aeaa474af49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600407818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.600407818
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2613656389
Short name T577
Test name
Test status
Simulation time 1614417305 ps
CPU time 26.31 seconds
Started Mar 21 12:38:47 PM PDT 24
Finished Mar 21 12:39:14 PM PDT 24
Peak memory 196740 kb
Host smart-6dd5c97d-b025-4570-a1a0-b927333cff40
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613656389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2613656389
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.4178655758
Short name T680
Test name
Test status
Simulation time 27727612 ps
CPU time 0.66 seconds
Started Mar 21 12:38:54 PM PDT 24
Finished Mar 21 12:38:56 PM PDT 24
Peak memory 194600 kb
Host smart-668fe27a-b5f7-45c2-a640-724bd64ee471
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178655758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.4178655758
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1466222746
Short name T288
Test name
Test status
Simulation time 50365065 ps
CPU time 1.44 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:38:42 PM PDT 24
Peak memory 197792 kb
Host smart-904ff217-8543-4068-adfb-82e74a4c2602
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466222746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1466222746
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.4055583054
Short name T507
Test name
Test status
Simulation time 27752173 ps
CPU time 1.04 seconds
Started Mar 21 12:38:42 PM PDT 24
Finished Mar 21 12:38:43 PM PDT 24
Peak memory 195892 kb
Host smart-94472d37-476d-4c96-85e9-7248b17afaa0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055583054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.4055583054
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1734610813
Short name T483
Test name
Test status
Simulation time 1834822353 ps
CPU time 3.02 seconds
Started Mar 21 12:38:41 PM PDT 24
Finished Mar 21 12:38:45 PM PDT 24
Peak memory 197844 kb
Host smart-fc087de9-1bcc-4976-81d9-793076055487
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734610813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1734610813
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3653913361
Short name T344
Test name
Test status
Simulation time 43117940 ps
CPU time 0.98 seconds
Started Mar 21 12:38:48 PM PDT 24
Finished Mar 21 12:38:50 PM PDT 24
Peak memory 195860 kb
Host smart-58d0c37b-4491-40ec-8b07-d555166e9a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653913361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3653913361
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.478790507
Short name T705
Test name
Test status
Simulation time 204027983 ps
CPU time 0.92 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:38:41 PM PDT 24
Peak memory 196384 kb
Host smart-042cd5b8-8db2-4564-8e25-7aac4448de01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478790507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.478790507
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2906724232
Short name T297
Test name
Test status
Simulation time 242499127 ps
CPU time 5.4 seconds
Started Mar 21 12:38:49 PM PDT 24
Finished Mar 21 12:38:55 PM PDT 24
Peak memory 197944 kb
Host smart-406fd321-339a-45dc-99f7-952540c91532
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906724232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2906724232
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3657529609
Short name T46
Test name
Test status
Simulation time 70942644 ps
CPU time 0.87 seconds
Started Mar 21 12:38:41 PM PDT 24
Finished Mar 21 12:38:43 PM PDT 24
Peak memory 213632 kb
Host smart-37d01387-80fc-4452-8a63-0cafb084efb0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657529609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3657529609
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2675637163
Short name T117
Test name
Test status
Simulation time 79970204 ps
CPU time 1.15 seconds
Started Mar 21 12:38:36 PM PDT 24
Finished Mar 21 12:38:37 PM PDT 24
Peak memory 195516 kb
Host smart-411d33c8-d11b-49e0-bf07-5bb29f0d6350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675637163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2675637163
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2412536550
Short name T405
Test name
Test status
Simulation time 68323278 ps
CPU time 0.91 seconds
Started Mar 21 12:38:48 PM PDT 24
Finished Mar 21 12:38:50 PM PDT 24
Peak memory 195228 kb
Host smart-6fbe983b-4283-4f20-87dd-3a17a0fa8ec3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412536550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2412536550
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2894836482
Short name T546
Test name
Test status
Simulation time 2298789840 ps
CPU time 27.38 seconds
Started Mar 21 12:38:44 PM PDT 24
Finished Mar 21 12:39:11 PM PDT 24
Peak memory 197880 kb
Host smart-3b9ea703-f43e-445e-98f6-9fd37fa3d2cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894836482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2894836482
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2650891737
Short name T69
Test name
Test status
Simulation time 182701319287 ps
CPU time 826.64 seconds
Started Mar 21 12:38:52 PM PDT 24
Finished Mar 21 12:52:39 PM PDT 24
Peak memory 198068 kb
Host smart-d92af605-eed4-482e-8e47-25d147b7e075
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2650891737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2650891737
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2802858528
Short name T386
Test name
Test status
Simulation time 14392520 ps
CPU time 0.56 seconds
Started Mar 21 12:39:44 PM PDT 24
Finished Mar 21 12:39:44 PM PDT 24
Peak memory 194536 kb
Host smart-c2ce299c-357b-495c-96df-c9a1ff96aa05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802858528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2802858528
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1374037909
Short name T394
Test name
Test status
Simulation time 160797407 ps
CPU time 0.87 seconds
Started Mar 21 12:39:38 PM PDT 24
Finished Mar 21 12:39:39 PM PDT 24
Peak memory 195356 kb
Host smart-0668c8af-ae14-4b6d-82b8-ee465d09c4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374037909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1374037909
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1952006751
Short name T518
Test name
Test status
Simulation time 496685715 ps
CPU time 14.43 seconds
Started Mar 21 12:39:37 PM PDT 24
Finished Mar 21 12:39:52 PM PDT 24
Peak memory 196772 kb
Host smart-2607beca-e3d7-4ba6-9131-b33403b2bf9f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952006751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1952006751
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3086989697
Short name T676
Test name
Test status
Simulation time 61931026 ps
CPU time 1 seconds
Started Mar 21 12:39:54 PM PDT 24
Finished Mar 21 12:39:55 PM PDT 24
Peak memory 196224 kb
Host smart-44b2c1c3-7033-450f-8fd3-243e6ce92938
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086989697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3086989697
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2637712990
Short name T467
Test name
Test status
Simulation time 26224119 ps
CPU time 0.83 seconds
Started Mar 21 12:39:39 PM PDT 24
Finished Mar 21 12:39:40 PM PDT 24
Peak memory 195556 kb
Host smart-a4d04bf8-737a-4813-8d64-e998d429f62d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637712990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2637712990
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1853325676
Short name T180
Test name
Test status
Simulation time 90162191 ps
CPU time 3.65 seconds
Started Mar 21 12:39:40 PM PDT 24
Finished Mar 21 12:39:44 PM PDT 24
Peak memory 197972 kb
Host smart-ac8b3ff9-9296-4c56-b671-a0200561ba7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853325676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1853325676
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2773625651
Short name T539
Test name
Test status
Simulation time 75954290 ps
CPU time 0.94 seconds
Started Mar 21 12:39:39 PM PDT 24
Finished Mar 21 12:39:40 PM PDT 24
Peak memory 194280 kb
Host smart-fcba4229-332e-4418-8e27-40a6d617796a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773625651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2773625651
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1767626542
Short name T403
Test name
Test status
Simulation time 16987920 ps
CPU time 0.72 seconds
Started Mar 21 12:39:47 PM PDT 24
Finished Mar 21 12:39:48 PM PDT 24
Peak memory 195320 kb
Host smart-a2e83595-db76-422c-9052-1ca310323b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767626542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1767626542
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.378826014
Short name T685
Test name
Test status
Simulation time 148815866 ps
CPU time 1.03 seconds
Started Mar 21 12:39:33 PM PDT 24
Finished Mar 21 12:39:34 PM PDT 24
Peak memory 196540 kb
Host smart-3d585ae2-9f7a-4d09-9a09-430d13e249f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378826014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.378826014
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3817516594
Short name T331
Test name
Test status
Simulation time 230264024 ps
CPU time 3.75 seconds
Started Mar 21 12:39:38 PM PDT 24
Finished Mar 21 12:39:42 PM PDT 24
Peak memory 197824 kb
Host smart-f6c1a026-bfd5-46b0-9d78-a92551f66671
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817516594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3817516594
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.929667298
Short name T30
Test name
Test status
Simulation time 398130939 ps
CPU time 1.51 seconds
Started Mar 21 12:39:33 PM PDT 24
Finished Mar 21 12:39:35 PM PDT 24
Peak memory 195448 kb
Host smart-3e7fd366-0398-4711-989a-c45c98db71e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929667298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.929667298
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3079280637
Short name T402
Test name
Test status
Simulation time 40435301 ps
CPU time 0.8 seconds
Started Mar 21 12:39:30 PM PDT 24
Finished Mar 21 12:39:31 PM PDT 24
Peak memory 195168 kb
Host smart-e49fed76-db13-49bc-b64b-06e1e3f4559d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079280637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3079280637
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3213406992
Short name T655
Test name
Test status
Simulation time 102595672376 ps
CPU time 99.49 seconds
Started Mar 21 12:39:39 PM PDT 24
Finished Mar 21 12:41:19 PM PDT 24
Peak memory 197976 kb
Host smart-e82511cc-4205-4ab5-9bc0-af9720f12847
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213406992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3213406992
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2896779184
Short name T522
Test name
Test status
Simulation time 13526207 ps
CPU time 0.61 seconds
Started Mar 21 12:39:30 PM PDT 24
Finished Mar 21 12:39:31 PM PDT 24
Peak memory 194052 kb
Host smart-76ea6af7-8939-42c0-a898-f5f6c7659714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896779184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2896779184
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3427088246
Short name T505
Test name
Test status
Simulation time 46337985 ps
CPU time 1.01 seconds
Started Mar 21 12:39:44 PM PDT 24
Finished Mar 21 12:39:45 PM PDT 24
Peak memory 196568 kb
Host smart-845bc5a6-3760-4020-a55d-45a2fc1ca162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427088246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3427088246
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1009504448
Short name T523
Test name
Test status
Simulation time 1833841236 ps
CPU time 24.37 seconds
Started Mar 21 12:39:39 PM PDT 24
Finished Mar 21 12:40:04 PM PDT 24
Peak memory 197900 kb
Host smart-6e4b2bcb-2934-4772-9241-5b941d596085
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009504448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1009504448
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3491323936
Short name T646
Test name
Test status
Simulation time 52878283 ps
CPU time 0.93 seconds
Started Mar 21 12:39:35 PM PDT 24
Finished Mar 21 12:39:36 PM PDT 24
Peak memory 197816 kb
Host smart-535f3c79-d124-4368-a38d-3075dbbcec50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491323936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3491323936
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3176481025
Short name T550
Test name
Test status
Simulation time 292648250 ps
CPU time 1.28 seconds
Started Mar 21 12:39:31 PM PDT 24
Finished Mar 21 12:39:33 PM PDT 24
Peak memory 197068 kb
Host smart-6fcc7e37-d8e5-4b3c-95d4-65444d614433
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176481025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3176481025
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2930938561
Short name T232
Test name
Test status
Simulation time 50199675 ps
CPU time 1.96 seconds
Started Mar 21 12:39:32 PM PDT 24
Finished Mar 21 12:39:34 PM PDT 24
Peak memory 196152 kb
Host smart-9c4618d3-e881-4496-a49e-a48a8d2e6cd9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930938561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2930938561
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.197396856
Short name T491
Test name
Test status
Simulation time 231626291 ps
CPU time 1.69 seconds
Started Mar 21 12:39:35 PM PDT 24
Finished Mar 21 12:39:37 PM PDT 24
Peak memory 195916 kb
Host smart-71c401df-0f25-416b-84b0-b80f0770f0ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197396856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
197396856
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.332718528
Short name T417
Test name
Test status
Simulation time 58614539 ps
CPU time 1.32 seconds
Started Mar 21 12:39:36 PM PDT 24
Finished Mar 21 12:39:37 PM PDT 24
Peak memory 196716 kb
Host smart-e8e39912-d860-4f11-81dd-e26f9b186a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332718528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.332718528
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1690370754
Short name T561
Test name
Test status
Simulation time 51873272 ps
CPU time 0.85 seconds
Started Mar 21 12:39:44 PM PDT 24
Finished Mar 21 12:39:45 PM PDT 24
Peak memory 196584 kb
Host smart-f0a71ef9-90d5-4457-98d1-6b03d7ea5399
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690370754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1690370754
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.701428417
Short name T436
Test name
Test status
Simulation time 537821914 ps
CPU time 5.46 seconds
Started Mar 21 12:39:30 PM PDT 24
Finished Mar 21 12:39:36 PM PDT 24
Peak memory 196928 kb
Host smart-41d9309b-bc54-4420-8980-684597b8e86f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701428417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.701428417
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.4209099505
Short name T119
Test name
Test status
Simulation time 454092041 ps
CPU time 1.21 seconds
Started Mar 21 12:39:32 PM PDT 24
Finished Mar 21 12:39:33 PM PDT 24
Peak memory 196788 kb
Host smart-650fe1b6-ca65-4e9f-9be6-44d550db4cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209099505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.4209099505
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.12597891
Short name T660
Test name
Test status
Simulation time 165491300 ps
CPU time 1.03 seconds
Started Mar 21 12:39:55 PM PDT 24
Finished Mar 21 12:39:56 PM PDT 24
Peak memory 196392 kb
Host smart-51925e90-428b-4307-9275-4499e934e235
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12597891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.12597891
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2281858931
Short name T149
Test name
Test status
Simulation time 21561414168 ps
CPU time 144.33 seconds
Started Mar 21 12:39:32 PM PDT 24
Finished Mar 21 12:41:57 PM PDT 24
Peak memory 197992 kb
Host smart-78f21bde-6b0e-4e2c-a74f-b7b6299c7e71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281858931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2281858931
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.511051103
Short name T506
Test name
Test status
Simulation time 15878132 ps
CPU time 0.57 seconds
Started Mar 21 12:39:47 PM PDT 24
Finished Mar 21 12:39:48 PM PDT 24
Peak memory 193792 kb
Host smart-b5ee6ef1-ca1f-4fc3-96d8-bfeada59255d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511051103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.511051103
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.660358116
Short name T231
Test name
Test status
Simulation time 59997856 ps
CPU time 0.77 seconds
Started Mar 21 12:39:41 PM PDT 24
Finished Mar 21 12:39:42 PM PDT 24
Peak memory 195076 kb
Host smart-a7b1e044-fc02-4602-bdc0-fb767f577e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660358116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.660358116
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.4067272395
Short name T462
Test name
Test status
Simulation time 364608735 ps
CPU time 9.92 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:59 PM PDT 24
Peak memory 196260 kb
Host smart-765c9032-5bc0-4e0a-b2f3-372a867afcec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067272395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.4067272395
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.4254846047
Short name T485
Test name
Test status
Simulation time 45375500 ps
CPU time 0.79 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:39:51 PM PDT 24
Peak memory 195720 kb
Host smart-f25d9c83-ee86-4c7c-8145-a156db84ec1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254846047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.4254846047
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1821822437
Short name T132
Test name
Test status
Simulation time 474714407 ps
CPU time 1.14 seconds
Started Mar 21 12:39:46 PM PDT 24
Finished Mar 21 12:39:47 PM PDT 24
Peak memory 196336 kb
Host smart-9e25e923-dd7a-450f-a7f2-9d320a155c9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821822437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1821822437
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1021610097
Short name T704
Test name
Test status
Simulation time 308242303 ps
CPU time 3.29 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:39:53 PM PDT 24
Peak memory 196388 kb
Host smart-f3309512-7c12-4b08-a319-b0c3402adb31
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021610097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1021610097
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3917002333
Short name T155
Test name
Test status
Simulation time 267322147 ps
CPU time 1.59 seconds
Started Mar 21 12:39:47 PM PDT 24
Finished Mar 21 12:39:49 PM PDT 24
Peak memory 196392 kb
Host smart-a98314d6-1eca-4f6a-b4d8-0603d6bde508
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917002333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3917002333
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1672730134
Short name T560
Test name
Test status
Simulation time 25096677 ps
CPU time 0.83 seconds
Started Mar 21 12:39:31 PM PDT 24
Finished Mar 21 12:39:32 PM PDT 24
Peak memory 196464 kb
Host smart-135d5599-b8fe-4a38-a429-a477c4b3b331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672730134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1672730134
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1175718106
Short name T615
Test name
Test status
Simulation time 19238640 ps
CPU time 0.72 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 195344 kb
Host smart-e8fb9862-98c9-4459-95dd-675a969d2678
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175718106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1175718106
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1309441336
Short name T139
Test name
Test status
Simulation time 67064711 ps
CPU time 2.95 seconds
Started Mar 21 12:39:47 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 197808 kb
Host smart-371d9254-df24-45d2-bf19-85de2a3a1d20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309441336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1309441336
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1473437409
Short name T617
Test name
Test status
Simulation time 138418035 ps
CPU time 0.81 seconds
Started Mar 21 12:39:45 PM PDT 24
Finished Mar 21 12:39:46 PM PDT 24
Peak memory 195124 kb
Host smart-1c0745ce-fb1c-4baa-9fc8-d9c49eafd851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473437409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1473437409
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2991700415
Short name T373
Test name
Test status
Simulation time 168577921 ps
CPU time 1.22 seconds
Started Mar 21 12:39:32 PM PDT 24
Finished Mar 21 12:39:33 PM PDT 24
Peak memory 196192 kb
Host smart-18488f05-2eef-446d-a17f-6796d76300c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991700415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2991700415
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.509113533
Short name T247
Test name
Test status
Simulation time 13784317456 ps
CPU time 182.61 seconds
Started Mar 21 12:39:46 PM PDT 24
Finished Mar 21 12:42:49 PM PDT 24
Peak memory 197960 kb
Host smart-4cc6a059-3dea-4834-b674-b2cee9f703fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509113533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.509113533
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2151108147
Short name T679
Test name
Test status
Simulation time 14915268 ps
CPU time 0.6 seconds
Started Mar 21 12:39:56 PM PDT 24
Finished Mar 21 12:39:57 PM PDT 24
Peak memory 193756 kb
Host smart-4cdd0154-94c3-4b2d-9eeb-42952c94380a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151108147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2151108147
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2522219622
Short name T156
Test name
Test status
Simulation time 43991143 ps
CPU time 0.79 seconds
Started Mar 21 12:39:48 PM PDT 24
Finished Mar 21 12:39:49 PM PDT 24
Peak memory 195124 kb
Host smart-ac408004-a260-4577-b03a-0fa0661504f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522219622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2522219622
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3396475234
Short name T593
Test name
Test status
Simulation time 528858051 ps
CPU time 16.62 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:40:05 PM PDT 24
Peak memory 196152 kb
Host smart-4fc161a1-e5f2-4daf-9e47-82121a6bb83d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396475234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3396475234
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2809921312
Short name T418
Test name
Test status
Simulation time 113013276 ps
CPU time 0.92 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 197028 kb
Host smart-bccb9ddc-befb-4534-856c-6e635bce9b1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809921312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2809921312
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1325279545
Short name T364
Test name
Test status
Simulation time 253919435 ps
CPU time 1.02 seconds
Started Mar 21 12:39:43 PM PDT 24
Finished Mar 21 12:39:44 PM PDT 24
Peak memory 195904 kb
Host smart-fdec2fe5-837d-4ffc-a3a7-9623c379dbcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325279545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1325279545
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.4157764397
Short name T528
Test name
Test status
Simulation time 26208642 ps
CPU time 1.11 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:51 PM PDT 24
Peak memory 195988 kb
Host smart-8057c73b-0c48-479f-90c8-7c72093e5452
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157764397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.4157764397
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2660775994
Short name T511
Test name
Test status
Simulation time 506260537 ps
CPU time 3.46 seconds
Started Mar 21 12:39:46 PM PDT 24
Finished Mar 21 12:39:49 PM PDT 24
Peak memory 196988 kb
Host smart-c8f73548-6ada-4662-920d-058a0cb18dda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660775994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2660775994
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3177141116
Short name T434
Test name
Test status
Simulation time 37588234 ps
CPU time 0.83 seconds
Started Mar 21 12:39:46 PM PDT 24
Finished Mar 21 12:39:47 PM PDT 24
Peak memory 196512 kb
Host smart-c403e970-c6e2-4329-ba87-44920f2209c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177141116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3177141116
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2361364670
Short name T217
Test name
Test status
Simulation time 28922383 ps
CPU time 1.18 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 196784 kb
Host smart-8a2e619e-55b4-438f-88f6-8d2c68290cd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361364670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.2361364670
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.75074733
Short name T681
Test name
Test status
Simulation time 5733866872 ps
CPU time 4.33 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:53 PM PDT 24
Peak memory 197948 kb
Host smart-48c7c2a4-6a41-45fe-87f2-ce7b0820e8db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75074733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand
om_long_reg_writes_reg_reads.75074733
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.389700939
Short name T298
Test name
Test status
Simulation time 89385494 ps
CPU time 0.86 seconds
Started Mar 21 12:39:48 PM PDT 24
Finished Mar 21 12:39:49 PM PDT 24
Peak memory 195816 kb
Host smart-c4edb468-87d9-4d14-8768-714e4375b339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389700939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.389700939
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.851656969
Short name T472
Test name
Test status
Simulation time 245324019 ps
CPU time 1.38 seconds
Started Mar 21 12:39:43 PM PDT 24
Finished Mar 21 12:39:44 PM PDT 24
Peak memory 198152 kb
Host smart-29889dbd-95cc-4e05-9631-d7c5c3b099cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851656969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.851656969
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1637154288
Short name T571
Test name
Test status
Simulation time 894249870 ps
CPU time 19.69 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:40:09 PM PDT 24
Peak memory 197944 kb
Host smart-b805f8f7-9e3a-417c-ae68-0212da0bba36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637154288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1637154288
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3848317278
Short name T47
Test name
Test status
Simulation time 22363493 ps
CPU time 0.6 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 194432 kb
Host smart-20291daf-2431-4d89-bced-c3e0b19c12e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848317278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3848317278
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1270065441
Short name T295
Test name
Test status
Simulation time 19465043 ps
CPU time 0.77 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 195128 kb
Host smart-b37583aa-1291-4f03-9f0a-98213eb0c937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270065441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1270065441
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.113710735
Short name T610
Test name
Test status
Simulation time 996299273 ps
CPU time 18.36 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:40:08 PM PDT 24
Peak memory 196916 kb
Host smart-fac2611b-8e62-4b01-8b31-f6394113e858
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113710735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.113710735
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3178665196
Short name T148
Test name
Test status
Simulation time 23853962 ps
CPU time 0.65 seconds
Started Mar 21 12:39:56 PM PDT 24
Finished Mar 21 12:39:57 PM PDT 24
Peak memory 194176 kb
Host smart-8e66af38-cc77-452a-a082-7c8201d5d84f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178665196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3178665196
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2983038794
Short name T316
Test name
Test status
Simulation time 98006741 ps
CPU time 1.37 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 196468 kb
Host smart-c6205d75-e8a8-4bf7-9db4-c57d7365eb32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983038794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2983038794
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2263298604
Short name T324
Test name
Test status
Simulation time 67797345 ps
CPU time 1.49 seconds
Started Mar 21 12:39:48 PM PDT 24
Finished Mar 21 12:39:49 PM PDT 24
Peak memory 196700 kb
Host smart-2741b8f2-d0ef-4b7f-9fa8-0432198b4ae1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263298604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2263298604
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1911398727
Short name T116
Test name
Test status
Simulation time 115886137 ps
CPU time 1.13 seconds
Started Mar 21 12:39:48 PM PDT 24
Finished Mar 21 12:39:49 PM PDT 24
Peak memory 196720 kb
Host smart-6c98f340-23f8-434c-b1bd-1d67325ea5c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911398727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1911398727
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3779674295
Short name T249
Test name
Test status
Simulation time 23534359 ps
CPU time 0.86 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 195608 kb
Host smart-022d37bb-8edf-4ff9-bf82-242039992597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779674295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3779674295
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.388701489
Short name T557
Test name
Test status
Simulation time 86004305 ps
CPU time 1.03 seconds
Started Mar 21 12:39:48 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 195884 kb
Host smart-654263d8-4f04-4f2c-8872-c8c948e89017
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388701489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.388701489
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1884524561
Short name T361
Test name
Test status
Simulation time 240889238 ps
CPU time 3.87 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:54 PM PDT 24
Peak memory 196988 kb
Host smart-29fbdafa-7fb5-4f0b-8fcf-3def96fc5965
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884524561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1884524561
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1269894962
Short name T609
Test name
Test status
Simulation time 45653376 ps
CPU time 1.21 seconds
Started Mar 21 12:39:58 PM PDT 24
Finished Mar 21 12:39:59 PM PDT 24
Peak memory 196764 kb
Host smart-3e9d7268-c70b-4b2f-b27e-0e73bf19e3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269894962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1269894962
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.583730546
Short name T230
Test name
Test status
Simulation time 82881629 ps
CPU time 0.91 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 195216 kb
Host smart-07784c23-b605-4f39-b9aa-e680f424d356
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583730546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.583730546
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2693959115
Short name T544
Test name
Test status
Simulation time 10871297648 ps
CPU time 74.44 seconds
Started Mar 21 12:39:48 PM PDT 24
Finished Mar 21 12:41:03 PM PDT 24
Peak memory 197984 kb
Host smart-84fb087e-905a-4933-a13d-85cd76c0c0f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693959115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2693959115
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.668268832
Short name T161
Test name
Test status
Simulation time 117089263 ps
CPU time 0.58 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 193636 kb
Host smart-517b912d-9c64-43f7-ae53-90648be7d559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668268832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.668268832
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2507139221
Short name T140
Test name
Test status
Simulation time 102240412 ps
CPU time 0.75 seconds
Started Mar 21 12:40:01 PM PDT 24
Finished Mar 21 12:40:02 PM PDT 24
Peak memory 195072 kb
Host smart-6ade2b5f-5bc3-4d2c-bb93-68ec6bb63db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507139221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2507139221
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.859524
Short name T573
Test name
Test status
Simulation time 983498439 ps
CPU time 16.43 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:40:07 PM PDT 24
Peak memory 196652 kb
Host smart-380b0fc0-6dd9-4c02-98c9-af89d658a8a8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_st
ress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stress.859524
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2655283563
Short name T543
Test name
Test status
Simulation time 1664853839 ps
CPU time 1.1 seconds
Started Mar 21 12:39:51 PM PDT 24
Finished Mar 21 12:39:52 PM PDT 24
Peak memory 196432 kb
Host smart-ee88124b-c8d2-4748-a8c6-93e5fb51e31c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655283563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2655283563
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2647619795
Short name T566
Test name
Test status
Simulation time 129979081 ps
CPU time 1.32 seconds
Started Mar 21 12:39:51 PM PDT 24
Finished Mar 21 12:39:52 PM PDT 24
Peak memory 196972 kb
Host smart-8884d093-6dcf-4829-9b4d-4a4961ae1731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647619795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2647619795
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2755831862
Short name T303
Test name
Test status
Simulation time 325438822 ps
CPU time 3.31 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:39:53 PM PDT 24
Peak memory 197904 kb
Host smart-5e549981-d932-47d2-a8c8-bc3f252742ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755831862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2755831862
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3286257519
Short name T11
Test name
Test status
Simulation time 548799149 ps
CPU time 3.02 seconds
Started Mar 21 12:39:56 PM PDT 24
Finished Mar 21 12:39:59 PM PDT 24
Peak memory 197888 kb
Host smart-af3c43a7-6026-4d26-862b-12a891a13144
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286257519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3286257519
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3446922622
Short name T319
Test name
Test status
Simulation time 239636813 ps
CPU time 1.21 seconds
Started Mar 21 12:39:59 PM PDT 24
Finished Mar 21 12:40:00 PM PDT 24
Peak memory 196708 kb
Host smart-7cce2532-300b-482c-bed6-1ab735cecbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446922622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3446922622
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1418711707
Short name T592
Test name
Test status
Simulation time 262526652 ps
CPU time 1.15 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:39:51 PM PDT 24
Peak memory 195984 kb
Host smart-a4d0df13-7ea7-4513-8d79-d949d3b8697e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418711707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1418711707
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.816325079
Short name T698
Test name
Test status
Simulation time 191517940 ps
CPU time 1.17 seconds
Started Mar 21 12:39:51 PM PDT 24
Finished Mar 21 12:39:52 PM PDT 24
Peak memory 196188 kb
Host smart-cbc28a9e-f79f-40ab-aab8-e2bf98fa64dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816325079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.816325079
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1578024042
Short name T667
Test name
Test status
Simulation time 136589558 ps
CPU time 0.84 seconds
Started Mar 21 12:39:48 PM PDT 24
Finished Mar 21 12:39:49 PM PDT 24
Peak memory 195224 kb
Host smart-b144a838-dbe0-45c5-ab3f-e9db63c97330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578024042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1578024042
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1145711058
Short name T370
Test name
Test status
Simulation time 71358229 ps
CPU time 0.9 seconds
Started Mar 21 12:39:57 PM PDT 24
Finished Mar 21 12:39:58 PM PDT 24
Peak memory 195808 kb
Host smart-bfc8ab5f-2cc3-456b-b47e-3c211fce4b10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145711058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1145711058
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1081934765
Short name T311
Test name
Test status
Simulation time 31736115858 ps
CPU time 113.16 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:41:42 PM PDT 24
Peak memory 197964 kb
Host smart-51026b21-d680-4837-b870-2870210cc4e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081934765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1081934765
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1554494614
Short name T391
Test name
Test status
Simulation time 56701379 ps
CPU time 0.61 seconds
Started Mar 21 12:39:59 PM PDT 24
Finished Mar 21 12:39:59 PM PDT 24
Peak memory 193816 kb
Host smart-2508fa9c-ff24-42c0-9b96-c29620b0d641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554494614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1554494614
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2908027156
Short name T586
Test name
Test status
Simulation time 150585982 ps
CPU time 0.83 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 195236 kb
Host smart-d85db938-3418-4857-b326-ce84d7914a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908027156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2908027156
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.724057479
Short name T598
Test name
Test status
Simulation time 788440709 ps
CPU time 25.08 seconds
Started Mar 21 12:39:48 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 196824 kb
Host smart-f64bbd08-2dcd-44c5-b134-080f86899496
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724057479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.724057479
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3348105518
Short name T535
Test name
Test status
Simulation time 91321455 ps
CPU time 1.01 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:39:52 PM PDT 24
Peak memory 197136 kb
Host smart-3f67e702-7ecf-4004-85b1-30cd289a93c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348105518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3348105518
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3614996311
Short name T169
Test name
Test status
Simulation time 160348584 ps
CPU time 1.39 seconds
Started Mar 21 12:39:54 PM PDT 24
Finished Mar 21 12:39:56 PM PDT 24
Peak memory 197920 kb
Host smart-9210e4e4-d907-4cb4-a71f-82363706ccc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614996311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3614996311
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2574300418
Short name T569
Test name
Test status
Simulation time 372528207 ps
CPU time 1.55 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 196644 kb
Host smart-bfdaacf4-599e-4d0c-95f2-4449546e80f6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574300418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2574300418
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3691086311
Short name T227
Test name
Test status
Simulation time 143066754 ps
CPU time 3.27 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:39:54 PM PDT 24
Peak memory 196372 kb
Host smart-8864f74d-f470-451a-880a-378dbcde9667
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691086311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3691086311
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.360155397
Short name T286
Test name
Test status
Simulation time 113569686 ps
CPU time 1.19 seconds
Started Mar 21 12:39:48 PM PDT 24
Finished Mar 21 12:39:49 PM PDT 24
Peak memory 195680 kb
Host smart-f47f1868-3a5c-43ca-808a-f478fe3cbda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360155397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.360155397
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1336133102
Short name T534
Test name
Test status
Simulation time 55433715 ps
CPU time 0.66 seconds
Started Mar 21 12:39:48 PM PDT 24
Finished Mar 21 12:39:48 PM PDT 24
Peak memory 194180 kb
Host smart-5ce94c33-26fb-4578-a597-4f24a92848b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336133102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1336133102
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2875948442
Short name T711
Test name
Test status
Simulation time 98265421 ps
CPU time 1.94 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:52 PM PDT 24
Peak memory 197448 kb
Host smart-22b762c8-25a1-4f9b-b629-4a00cc174c83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875948442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2875948442
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3742249223
Short name T274
Test name
Test status
Simulation time 67477536 ps
CPU time 0.9 seconds
Started Mar 21 12:39:52 PM PDT 24
Finished Mar 21 12:39:53 PM PDT 24
Peak memory 197112 kb
Host smart-f03c6b3c-35a2-4cb2-bf27-d14be72b3b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742249223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3742249223
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1709599971
Short name T579
Test name
Test status
Simulation time 21857801 ps
CPU time 0.71 seconds
Started Mar 21 12:39:46 PM PDT 24
Finished Mar 21 12:39:47 PM PDT 24
Peak memory 194032 kb
Host smart-71a6867e-ae02-437c-aebf-dd01e6b01a42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709599971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1709599971
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.530449973
Short name T6
Test name
Test status
Simulation time 44010928181 ps
CPU time 131.97 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:42:01 PM PDT 24
Peak memory 197984 kb
Host smart-a7e2fe7f-557b-4a9b-a7c1-cc82fda3d78a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530449973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.530449973
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.641662664
Short name T420
Test name
Test status
Simulation time 30117879 ps
CPU time 0.56 seconds
Started Mar 21 12:39:53 PM PDT 24
Finished Mar 21 12:39:53 PM PDT 24
Peak memory 193760 kb
Host smart-7f9aed0e-20bc-4f4b-b057-8c80d6e0fd15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641662664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.641662664
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.4228354847
Short name T204
Test name
Test status
Simulation time 78596722 ps
CPU time 0.84 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 195332 kb
Host smart-9ab23285-d453-4b53-bffd-3aa35846d9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228354847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.4228354847
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.688712547
Short name T652
Test name
Test status
Simulation time 858708875 ps
CPU time 22.39 seconds
Started Mar 21 12:39:51 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 196748 kb
Host smart-62359377-67c9-468f-9935-d6535f7fca3d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688712547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.688712547
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2834535152
Short name T157
Test name
Test status
Simulation time 45743827 ps
CPU time 0.88 seconds
Started Mar 21 12:39:51 PM PDT 24
Finished Mar 21 12:39:52 PM PDT 24
Peak memory 196880 kb
Host smart-fae97033-aff5-4567-9842-e4fe561b0249
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834535152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2834535152
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2137926709
Short name T123
Test name
Test status
Simulation time 40544044 ps
CPU time 1.14 seconds
Started Mar 21 12:39:52 PM PDT 24
Finished Mar 21 12:39:53 PM PDT 24
Peak memory 196644 kb
Host smart-06805879-9359-400e-9589-00f70efad449
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137926709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2137926709
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1588929270
Short name T670
Test name
Test status
Simulation time 94961257 ps
CPU time 3.49 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:39:54 PM PDT 24
Peak memory 197888 kb
Host smart-184dab32-db18-4458-8bd7-68bdce97d4c3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588929270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1588929270
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3520263382
Short name T372
Test name
Test status
Simulation time 147403529 ps
CPU time 3.19 seconds
Started Mar 21 12:40:05 PM PDT 24
Finished Mar 21 12:40:08 PM PDT 24
Peak memory 197968 kb
Host smart-a96afbf5-5c2e-4580-8644-6e139b820c04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520263382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3520263382
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3706642277
Short name T16
Test name
Test status
Simulation time 54787704 ps
CPU time 1.19 seconds
Started Mar 21 12:39:52 PM PDT 24
Finished Mar 21 12:39:53 PM PDT 24
Peak memory 196816 kb
Host smart-4b8addee-f4b7-40ce-b9da-7110d888df5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706642277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3706642277
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1741015775
Short name T396
Test name
Test status
Simulation time 58769845 ps
CPU time 1.22 seconds
Started Mar 21 12:40:12 PM PDT 24
Finished Mar 21 12:40:14 PM PDT 24
Peak memory 196884 kb
Host smart-9ab9d67e-ecd9-472a-99fe-89595f358092
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741015775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1741015775
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1844551112
Short name T3
Test name
Test status
Simulation time 820522212 ps
CPU time 5.53 seconds
Started Mar 21 12:40:05 PM PDT 24
Finished Mar 21 12:40:11 PM PDT 24
Peak memory 197808 kb
Host smart-c84403e2-10fe-4b12-a6b1-45ca04cdff46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844551112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1844551112
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.269424463
Short name T440
Test name
Test status
Simulation time 68070418 ps
CPU time 0.79 seconds
Started Mar 21 12:39:53 PM PDT 24
Finished Mar 21 12:39:54 PM PDT 24
Peak memory 195188 kb
Host smart-7b725b3a-1359-4a40-8557-c826ceba59c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269424463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.269424463
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.641640767
Short name T173
Test name
Test status
Simulation time 159204134 ps
CPU time 1.05 seconds
Started Mar 21 12:39:52 PM PDT 24
Finished Mar 21 12:39:53 PM PDT 24
Peak memory 195612 kb
Host smart-9930c62a-4c71-4754-8ca8-f68809816884
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641640767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.641640767
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3993954702
Short name T567
Test name
Test status
Simulation time 13489592229 ps
CPU time 91.38 seconds
Started Mar 21 12:39:46 PM PDT 24
Finished Mar 21 12:41:17 PM PDT 24
Peak memory 198028 kb
Host smart-98820927-4c8c-4c85-b569-569543ff5f7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993954702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3993954702
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2139113993
Short name T29
Test name
Test status
Simulation time 37036912 ps
CPU time 0.63 seconds
Started Mar 21 12:39:49 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 193960 kb
Host smart-885d9e01-86a2-4571-9c81-dfead75dd9fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139113993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2139113993
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1807673412
Short name T575
Test name
Test status
Simulation time 87877546 ps
CPU time 0.75 seconds
Started Mar 21 12:40:03 PM PDT 24
Finished Mar 21 12:40:04 PM PDT 24
Peak memory 193932 kb
Host smart-633c29eb-f41c-415a-8c7b-1cb01d9b28c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807673412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1807673412
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3456286455
Short name T493
Test name
Test status
Simulation time 997806424 ps
CPU time 25.66 seconds
Started Mar 21 12:40:02 PM PDT 24
Finished Mar 21 12:40:28 PM PDT 24
Peak memory 196972 kb
Host smart-3e5052fa-8981-418e-8116-d4eb5345fbb2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456286455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3456286455
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2340953671
Short name T578
Test name
Test status
Simulation time 74798302 ps
CPU time 1.07 seconds
Started Mar 21 12:40:00 PM PDT 24
Finished Mar 21 12:40:02 PM PDT 24
Peak memory 196460 kb
Host smart-92a25191-2768-46a8-bd06-4e5fad2ae963
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340953671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2340953671
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2622451633
Short name T327
Test name
Test status
Simulation time 328163306 ps
CPU time 1.41 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:39:51 PM PDT 24
Peak memory 197952 kb
Host smart-7020e697-f447-49a7-9339-919198815bf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622451633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2622451633
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.4265353367
Short name T637
Test name
Test status
Simulation time 244271257 ps
CPU time 3.29 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:39:54 PM PDT 24
Peak memory 197904 kb
Host smart-413b7f63-e3f0-4538-973b-e81235de1b59
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265353367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.4265353367
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2091387726
Short name T309
Test name
Test status
Simulation time 44856320 ps
CPU time 1.25 seconds
Started Mar 21 12:40:06 PM PDT 24
Finished Mar 21 12:40:09 PM PDT 24
Peak memory 195864 kb
Host smart-ea692d24-8486-4d05-a239-fb7bfb02eacd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091387726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2091387726
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2394368179
Short name T584
Test name
Test status
Simulation time 252058534 ps
CPU time 1.09 seconds
Started Mar 21 12:39:53 PM PDT 24
Finished Mar 21 12:39:54 PM PDT 24
Peak memory 195800 kb
Host smart-099f9626-86a9-4fd7-9966-5276d065944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394368179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2394368179
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.136832834
Short name T294
Test name
Test status
Simulation time 21311147 ps
CPU time 0.76 seconds
Started Mar 21 12:39:52 PM PDT 24
Finished Mar 21 12:39:53 PM PDT 24
Peak memory 195412 kb
Host smart-5fcbf731-cef5-4491-befc-8db20915edf9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136832834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.136832834
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2243701134
Short name T387
Test name
Test status
Simulation time 281992343 ps
CPU time 3.36 seconds
Started Mar 21 12:40:04 PM PDT 24
Finished Mar 21 12:40:07 PM PDT 24
Peak memory 197868 kb
Host smart-9bef1262-61ff-415a-bac0-90ebc3dbd36a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243701134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2243701134
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.420689167
Short name T701
Test name
Test status
Simulation time 73275037 ps
CPU time 1.05 seconds
Started Mar 21 12:39:57 PM PDT 24
Finished Mar 21 12:39:58 PM PDT 24
Peak memory 195576 kb
Host smart-9505569b-d458-44eb-9da3-ecebfe8ac71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420689167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.420689167
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.973904836
Short name T160
Test name
Test status
Simulation time 96407393 ps
CPU time 1 seconds
Started Mar 21 12:39:51 PM PDT 24
Finished Mar 21 12:39:52 PM PDT 24
Peak memory 195404 kb
Host smart-0aefad7f-2812-46cd-810f-4709c2ffc0d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973904836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.973904836
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.64228589
Short name T712
Test name
Test status
Simulation time 22854316114 ps
CPU time 146.39 seconds
Started Mar 21 12:40:04 PM PDT 24
Finished Mar 21 12:42:31 PM PDT 24
Peak memory 197952 kb
Host smart-ebc699e0-898e-4a8c-be89-493c847aa583
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64228589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gp
io_stress_all.64228589
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.4159916288
Short name T590
Test name
Test status
Simulation time 41007060 ps
CPU time 0.54 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:39:51 PM PDT 24
Peak memory 193776 kb
Host smart-1062cea6-bda2-4876-bc24-58be38e557de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159916288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.4159916288
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.248026990
Short name T437
Test name
Test status
Simulation time 112813723 ps
CPU time 0.7 seconds
Started Mar 21 12:39:55 PM PDT 24
Finished Mar 21 12:39:56 PM PDT 24
Peak memory 194024 kb
Host smart-bd601236-d585-499a-8542-bbc9196bdcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248026990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.248026990
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.881471305
Short name T197
Test name
Test status
Simulation time 384372697 ps
CPU time 11.21 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:40:01 PM PDT 24
Peak memory 197836 kb
Host smart-28992e46-14f2-4753-8754-e42bcaba963b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881471305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.881471305
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3109666295
Short name T499
Test name
Test status
Simulation time 55623464 ps
CPU time 0.84 seconds
Started Mar 21 12:40:01 PM PDT 24
Finished Mar 21 12:40:02 PM PDT 24
Peak memory 196708 kb
Host smart-d1e8626a-9ae5-44bf-b1d5-569f3f28c331
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109666295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3109666295
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.879292141
Short name T253
Test name
Test status
Simulation time 78348333 ps
CPU time 1.12 seconds
Started Mar 21 12:40:04 PM PDT 24
Finished Mar 21 12:40:05 PM PDT 24
Peak memory 196680 kb
Host smart-07a4956b-1d29-4d41-b369-c934a51256dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879292141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.879292141
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1610840848
Short name T496
Test name
Test status
Simulation time 97453776 ps
CPU time 3.94 seconds
Started Mar 21 12:40:03 PM PDT 24
Finished Mar 21 12:40:07 PM PDT 24
Peak memory 197972 kb
Host smart-e5342688-1037-4382-922b-af3ba431bcce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610840848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1610840848
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1089869986
Short name T643
Test name
Test status
Simulation time 142929148 ps
CPU time 3.09 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:39:53 PM PDT 24
Peak memory 196988 kb
Host smart-db614771-c9a5-4786-8611-6dcc4ea0af7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089869986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1089869986
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1108687017
Short name T325
Test name
Test status
Simulation time 110824785 ps
CPU time 1.2 seconds
Started Mar 21 12:40:03 PM PDT 24
Finished Mar 21 12:40:04 PM PDT 24
Peak memory 196688 kb
Host smart-08a97302-4b10-477d-9df0-d49c6ee92475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108687017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1108687017
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3205895706
Short name T446
Test name
Test status
Simulation time 126855419 ps
CPU time 0.87 seconds
Started Mar 21 12:40:12 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 196516 kb
Host smart-d6aec2b7-cf2b-425d-a072-2cb10c3d35f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205895706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3205895706
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.4250535488
Short name T31
Test name
Test status
Simulation time 111305643 ps
CPU time 4.97 seconds
Started Mar 21 12:40:03 PM PDT 24
Finished Mar 21 12:40:08 PM PDT 24
Peak memory 197840 kb
Host smart-16d41cc1-fac1-49a5-bb52-c6a611032d0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250535488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.4250535488
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1008520173
Short name T219
Test name
Test status
Simulation time 39021341 ps
CPU time 0.83 seconds
Started Mar 21 12:40:07 PM PDT 24
Finished Mar 21 12:40:10 PM PDT 24
Peak memory 196400 kb
Host smart-8e4b40cb-d47c-4b51-acc9-7b147a1923a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008520173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1008520173
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1114311899
Short name T78
Test name
Test status
Simulation time 213130991 ps
CPU time 1.17 seconds
Started Mar 21 12:40:03 PM PDT 24
Finished Mar 21 12:40:05 PM PDT 24
Peak memory 196276 kb
Host smart-fa659e76-e512-4cf4-9690-2fd70d295faa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114311899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1114311899
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3455859396
Short name T430
Test name
Test status
Simulation time 46069550052 ps
CPU time 196.45 seconds
Started Mar 21 12:39:52 PM PDT 24
Finished Mar 21 12:43:09 PM PDT 24
Peak memory 198088 kb
Host smart-fb24912c-82dd-4349-9e7f-f22e1ad99c1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455859396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3455859396
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2400569096
Short name T332
Test name
Test status
Simulation time 73787646 ps
CPU time 0.61 seconds
Started Mar 21 12:38:54 PM PDT 24
Finished Mar 21 12:38:56 PM PDT 24
Peak memory 193900 kb
Host smart-8f4096b0-5ae0-4032-b3dc-f0a4fbfc71c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400569096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2400569096
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3949095088
Short name T35
Test name
Test status
Simulation time 25179015 ps
CPU time 0.75 seconds
Started Mar 21 12:38:46 PM PDT 24
Finished Mar 21 12:38:47 PM PDT 24
Peak memory 193928 kb
Host smart-2a860225-4fd0-4474-991b-4c07161cb72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949095088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3949095088
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.4184115581
Short name T441
Test name
Test status
Simulation time 355481607 ps
CPU time 17.75 seconds
Started Mar 21 12:38:41 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 196772 kb
Host smart-e6ad2498-0bd4-4d63-9da3-f1deec7d84d6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184115581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.4184115581
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1728599804
Short name T114
Test name
Test status
Simulation time 654976160 ps
CPU time 1.03 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:38:55 PM PDT 24
Peak memory 197824 kb
Host smart-f1db12d1-f89a-4c22-8176-a996699ceaff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728599804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1728599804
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2488511901
Short name T428
Test name
Test status
Simulation time 113370314 ps
CPU time 1.35 seconds
Started Mar 21 12:38:51 PM PDT 24
Finished Mar 21 12:38:53 PM PDT 24
Peak memory 196844 kb
Host smart-0751d6f4-6660-4548-acc9-6b1756448c20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488511901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2488511901
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.195293185
Short name T690
Test name
Test status
Simulation time 50311833 ps
CPU time 1.16 seconds
Started Mar 21 12:38:42 PM PDT 24
Finished Mar 21 12:38:44 PM PDT 24
Peak memory 197588 kb
Host smart-eb553d47-6a8e-401d-99d9-410ebd2ac7ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195293185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.195293185
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.339034994
Short name T490
Test name
Test status
Simulation time 501063362 ps
CPU time 2.36 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:38:43 PM PDT 24
Peak memory 197884 kb
Host smart-65926333-a448-48f5-931d-c52d91e58ed4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339034994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.339034994
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2972661242
Short name T240
Test name
Test status
Simulation time 186225687 ps
CPU time 1.19 seconds
Started Mar 21 12:38:44 PM PDT 24
Finished Mar 21 12:38:45 PM PDT 24
Peak memory 196768 kb
Host smart-e5bf2f0f-b663-40bc-b90b-4e5247e1fbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972661242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2972661242
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1485559338
Short name T255
Test name
Test status
Simulation time 263258852 ps
CPU time 1.22 seconds
Started Mar 21 12:38:42 PM PDT 24
Finished Mar 21 12:38:44 PM PDT 24
Peak memory 196924 kb
Host smart-1540d9bb-6430-490b-a08c-64f940d80f69
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485559338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1485559338
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1120247277
Short name T300
Test name
Test status
Simulation time 311737497 ps
CPU time 4.81 seconds
Started Mar 21 12:38:52 PM PDT 24
Finished Mar 21 12:38:57 PM PDT 24
Peak memory 196952 kb
Host smart-c8e20e7c-ab4b-43d8-9d04-0a7dc27ca9a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120247277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1120247277
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2508405670
Short name T55
Test name
Test status
Simulation time 243039698 ps
CPU time 0.84 seconds
Started Mar 21 12:38:45 PM PDT 24
Finished Mar 21 12:38:46 PM PDT 24
Peak memory 213580 kb
Host smart-fdc6138c-528a-42bb-9f4e-3758a84c34f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508405670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2508405670
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.242024424
Short name T665
Test name
Test status
Simulation time 253015808 ps
CPU time 0.77 seconds
Started Mar 21 12:38:32 PM PDT 24
Finished Mar 21 12:38:34 PM PDT 24
Peak memory 194096 kb
Host smart-24917e99-1048-40d4-95c8-e238852adefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242024424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.242024424
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.276400768
Short name T529
Test name
Test status
Simulation time 26397019 ps
CPU time 0.82 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:38:57 PM PDT 24
Peak memory 195328 kb
Host smart-049c2964-52a1-4387-8a0b-50e04db295bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276400768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.276400768
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3309711816
Short name T616
Test name
Test status
Simulation time 35896865292 ps
CPU time 123.6 seconds
Started Mar 21 12:38:50 PM PDT 24
Finished Mar 21 12:40:54 PM PDT 24
Peak memory 198064 kb
Host smart-aff54953-4442-41e5-821c-e15a2b8ffd28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309711816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3309711816
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.502529517
Short name T271
Test name
Test status
Simulation time 45031513 ps
CPU time 0.62 seconds
Started Mar 21 12:40:06 PM PDT 24
Finished Mar 21 12:40:08 PM PDT 24
Peak memory 194024 kb
Host smart-a0d193ae-e5f3-403f-b513-2273b4846909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502529517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.502529517
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2953985285
Short name T318
Test name
Test status
Simulation time 56508166 ps
CPU time 0.71 seconds
Started Mar 21 12:39:58 PM PDT 24
Finished Mar 21 12:39:59 PM PDT 24
Peak memory 194108 kb
Host smart-4c907862-674b-455b-8b7d-0c06a9245022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953985285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2953985285
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.4140337504
Short name T226
Test name
Test status
Simulation time 432402714 ps
CPU time 21.73 seconds
Started Mar 21 12:39:57 PM PDT 24
Finished Mar 21 12:40:19 PM PDT 24
Peak memory 197952 kb
Host smart-94d64c14-f19a-4a07-a80a-f8eb0bd23958
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140337504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.4140337504
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.4077078154
Short name T563
Test name
Test status
Simulation time 782307850 ps
CPU time 1.01 seconds
Started Mar 21 12:40:09 PM PDT 24
Finished Mar 21 12:40:12 PM PDT 24
Peak memory 198036 kb
Host smart-356195d7-6992-40e9-b802-e375da8b4182
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077078154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.4077078154
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2868967396
Short name T131
Test name
Test status
Simulation time 25791914 ps
CPU time 0.69 seconds
Started Mar 21 12:39:55 PM PDT 24
Finished Mar 21 12:39:56 PM PDT 24
Peak memory 194296 kb
Host smart-9986d8d5-88e9-4f34-ba9e-abe777d93fd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868967396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2868967396
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.541235037
Short name T278
Test name
Test status
Simulation time 25928194 ps
CPU time 1.17 seconds
Started Mar 21 12:40:04 PM PDT 24
Finished Mar 21 12:40:16 PM PDT 24
Peak memory 197880 kb
Host smart-076535ab-faed-48cf-9e0c-a22b9f9ce62b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541235037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.541235037
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.239007648
Short name T181
Test name
Test status
Simulation time 57333010 ps
CPU time 1.38 seconds
Started Mar 21 12:39:54 PM PDT 24
Finished Mar 21 12:39:56 PM PDT 24
Peak memory 196000 kb
Host smart-fcf71c21-0d4b-469b-9b32-b8b9cafad60d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239007648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
239007648
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2389799080
Short name T570
Test name
Test status
Simulation time 268282779 ps
CPU time 1.31 seconds
Started Mar 21 12:40:07 PM PDT 24
Finished Mar 21 12:40:09 PM PDT 24
Peak memory 196948 kb
Host smart-406c09da-6d96-41b2-afb1-f11bc701b5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389799080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2389799080
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3388064119
Short name T254
Test name
Test status
Simulation time 61406214 ps
CPU time 1.24 seconds
Started Mar 21 12:39:58 PM PDT 24
Finished Mar 21 12:40:00 PM PDT 24
Peak memory 195772 kb
Host smart-7a0aeb3a-c2d3-45ce-accb-cb693d94c8f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388064119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3388064119
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2335259651
Short name T127
Test name
Test status
Simulation time 86059821 ps
CPU time 2.11 seconds
Started Mar 21 12:40:03 PM PDT 24
Finished Mar 21 12:40:06 PM PDT 24
Peak memory 197768 kb
Host smart-450581b8-bd07-478f-8065-5aa02bd0cb50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335259651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2335259651
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1882330695
Short name T368
Test name
Test status
Simulation time 170004130 ps
CPU time 1.49 seconds
Started Mar 21 12:39:58 PM PDT 24
Finished Mar 21 12:40:00 PM PDT 24
Peak memory 196716 kb
Host smart-91238cf5-c834-4e2d-8a88-aa491ab3186b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882330695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1882330695
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3768064515
Short name T273
Test name
Test status
Simulation time 66091209 ps
CPU time 1.13 seconds
Started Mar 21 12:40:05 PM PDT 24
Finished Mar 21 12:40:06 PM PDT 24
Peak memory 196304 kb
Host smart-9ab4efc1-5766-46bf-b062-0f4353129570
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768064515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3768064515
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2172215943
Short name T545
Test name
Test status
Simulation time 32789176680 ps
CPU time 199.94 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:43:10 PM PDT 24
Peak memory 197928 kb
Host smart-b9ff75f9-e6f6-4034-84ef-ba16839a33c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172215943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2172215943
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1443178405
Short name T406
Test name
Test status
Simulation time 19151162 ps
CPU time 0.6 seconds
Started Mar 21 12:40:04 PM PDT 24
Finished Mar 21 12:40:05 PM PDT 24
Peak memory 194064 kb
Host smart-badce49f-849a-4d9b-b0bc-9502fa61d378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443178405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1443178405
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1688681810
Short name T141
Test name
Test status
Simulation time 15227500 ps
CPU time 0.64 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:39:51 PM PDT 24
Peak memory 193736 kb
Host smart-920aac2b-2740-49cd-910e-809cf545914f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688681810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1688681810
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3145509623
Short name T263
Test name
Test status
Simulation time 1186362442 ps
CPU time 14.48 seconds
Started Mar 21 12:40:05 PM PDT 24
Finished Mar 21 12:40:21 PM PDT 24
Peak memory 197100 kb
Host smart-2b3f41c4-4345-4838-8192-c92d6a66c01e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145509623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3145509623
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3615421954
Short name T677
Test name
Test status
Simulation time 121019770 ps
CPU time 0.7 seconds
Started Mar 21 12:40:16 PM PDT 24
Finished Mar 21 12:40:16 PM PDT 24
Peak memory 194548 kb
Host smart-d6e2a880-6a32-4701-a392-b6c9ee64f57c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615421954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3615421954
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3712296415
Short name T281
Test name
Test status
Simulation time 79475080 ps
CPU time 0.7 seconds
Started Mar 21 12:40:05 PM PDT 24
Finished Mar 21 12:40:07 PM PDT 24
Peak memory 195168 kb
Host smart-4c248530-b16b-461d-8a92-b3d102445f35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712296415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3712296415
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.591338838
Short name T291
Test name
Test status
Simulation time 365998505 ps
CPU time 3.58 seconds
Started Mar 21 12:40:06 PM PDT 24
Finished Mar 21 12:40:10 PM PDT 24
Peak memory 196324 kb
Host smart-7eca1b72-4dba-429c-8648-616f40b76156
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591338838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.591338838
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2535950810
Short name T192
Test name
Test status
Simulation time 559787790 ps
CPU time 2.68 seconds
Started Mar 21 12:40:03 PM PDT 24
Finished Mar 21 12:40:06 PM PDT 24
Peak memory 197068 kb
Host smart-628d7b3d-550d-42bc-a455-db3e046854a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535950810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2535950810
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3306488845
Short name T555
Test name
Test status
Simulation time 114372995 ps
CPU time 0.86 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:39:51 PM PDT 24
Peak memory 196144 kb
Host smart-56367475-a089-4058-ba6d-301cbeca1853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306488845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3306488845
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2829552949
Short name T613
Test name
Test status
Simulation time 22208774 ps
CPU time 0.76 seconds
Started Mar 21 12:39:50 PM PDT 24
Finished Mar 21 12:39:51 PM PDT 24
Peak memory 195180 kb
Host smart-d8764bc7-fc8d-41b6-8bc9-3b934d2e392f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829552949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2829552949
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3677322372
Short name T307
Test name
Test status
Simulation time 309503600 ps
CPU time 5.15 seconds
Started Mar 21 12:40:08 PM PDT 24
Finished Mar 21 12:40:15 PM PDT 24
Peak memory 197836 kb
Host smart-b968fb8d-42d5-44ff-a4f7-45e63f1c16d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677322372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3677322372
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.4233824229
Short name T135
Test name
Test status
Simulation time 40827601 ps
CPU time 1.22 seconds
Started Mar 21 12:40:03 PM PDT 24
Finished Mar 21 12:40:05 PM PDT 24
Peak memory 196576 kb
Host smart-90768743-89b6-4d24-8e49-863f0b0961dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233824229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.4233824229
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2838274230
Short name T477
Test name
Test status
Simulation time 154422327 ps
CPU time 0.88 seconds
Started Mar 21 12:39:54 PM PDT 24
Finished Mar 21 12:39:55 PM PDT 24
Peak memory 195988 kb
Host smart-0838a4ea-b25b-4374-a33c-c9e1f7b5c23f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838274230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2838274230
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2411090483
Short name T525
Test name
Test status
Simulation time 61697263404 ps
CPU time 93.65 seconds
Started Mar 21 12:40:32 PM PDT 24
Finished Mar 21 12:42:07 PM PDT 24
Peak memory 198088 kb
Host smart-e93991e5-285c-4716-8e17-a1bd1079bbe5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411090483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2411090483
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.2110289492
Short name T38
Test name
Test status
Simulation time 213285732338 ps
CPU time 459.43 seconds
Started Mar 21 12:40:30 PM PDT 24
Finished Mar 21 12:48:09 PM PDT 24
Peak memory 198084 kb
Host smart-b51d592a-5a0d-4fa9-8ede-aa3acfbd9219
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2110289492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.2110289492
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.54501994
Short name T600
Test name
Test status
Simulation time 17192768 ps
CPU time 0.58 seconds
Started Mar 21 12:40:10 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 193732 kb
Host smart-792f08f2-138d-461b-9cbe-8f5811f0d828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54501994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.54501994
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3697752415
Short name T530
Test name
Test status
Simulation time 37957346 ps
CPU time 0.86 seconds
Started Mar 21 12:40:06 PM PDT 24
Finished Mar 21 12:40:08 PM PDT 24
Peak memory 195356 kb
Host smart-af594eb8-d593-46a2-bc98-a3b919cc6dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697752415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3697752415
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.4259589328
Short name T524
Test name
Test status
Simulation time 482701262 ps
CPU time 15.3 seconds
Started Mar 21 12:40:26 PM PDT 24
Finished Mar 21 12:40:41 PM PDT 24
Peak memory 197128 kb
Host smart-970b937e-0e06-4533-8667-b6ed10753890
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259589328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.4259589328
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1317184302
Short name T133
Test name
Test status
Simulation time 35699276 ps
CPU time 0.74 seconds
Started Mar 21 12:40:07 PM PDT 24
Finished Mar 21 12:40:09 PM PDT 24
Peak memory 195388 kb
Host smart-1edd66f2-db19-4323-8f98-b91b8db6d272
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317184302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1317184302
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3286688895
Short name T333
Test name
Test status
Simulation time 485868547 ps
CPU time 1.55 seconds
Started Mar 21 12:40:00 PM PDT 24
Finished Mar 21 12:40:01 PM PDT 24
Peak memory 196560 kb
Host smart-450d1245-b5dc-4395-a1e1-02777206565e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286688895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3286688895
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.393292101
Short name T264
Test name
Test status
Simulation time 64730238 ps
CPU time 1.31 seconds
Started Mar 21 12:40:09 PM PDT 24
Finished Mar 21 12:40:11 PM PDT 24
Peak memory 197864 kb
Host smart-c4e56434-d0e1-43d1-a062-5e3b96fc5f15
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393292101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.393292101
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.955346716
Short name T330
Test name
Test status
Simulation time 2279957043 ps
CPU time 2.47 seconds
Started Mar 21 12:40:15 PM PDT 24
Finished Mar 21 12:40:23 PM PDT 24
Peak memory 197040 kb
Host smart-06e74400-2766-42b7-86d4-4f83526d76ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955346716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
955346716
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.494824029
Short name T302
Test name
Test status
Simulation time 33351549 ps
CPU time 0.89 seconds
Started Mar 21 12:40:05 PM PDT 24
Finished Mar 21 12:40:07 PM PDT 24
Peak memory 197112 kb
Host smart-af13233b-4b30-4260-bfff-b953d5ef7b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494824029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.494824029
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.485331287
Short name T287
Test name
Test status
Simulation time 232641167 ps
CPU time 1.07 seconds
Started Mar 21 12:40:07 PM PDT 24
Finished Mar 21 12:40:10 PM PDT 24
Peak memory 195692 kb
Host smart-31d8d786-2712-4482-a7e2-a84621aecdf2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485331287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.485331287
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.212807917
Short name T120
Test name
Test status
Simulation time 63213431 ps
CPU time 1.41 seconds
Started Mar 21 12:40:10 PM PDT 24
Finished Mar 21 12:40:14 PM PDT 24
Peak memory 197940 kb
Host smart-2445e301-4fc1-4e4c-955a-821889ec1630
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212807917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.212807917
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.151549536
Short name T460
Test name
Test status
Simulation time 351957372 ps
CPU time 1.46 seconds
Started Mar 21 12:40:05 PM PDT 24
Finished Mar 21 12:40:06 PM PDT 24
Peak memory 196620 kb
Host smart-63e3befe-886c-45bf-ac98-fb3f39ca7fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151549536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.151549536
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3772971680
Short name T392
Test name
Test status
Simulation time 604160670 ps
CPU time 1.28 seconds
Started Mar 21 12:40:11 PM PDT 24
Finished Mar 21 12:40:14 PM PDT 24
Peak memory 196636 kb
Host smart-dc9d8c36-c8f8-4921-8aa2-88595def5d64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772971680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3772971680
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3906475601
Short name T664
Test name
Test status
Simulation time 29225347835 ps
CPU time 223.63 seconds
Started Mar 21 12:40:21 PM PDT 24
Finished Mar 21 12:44:05 PM PDT 24
Peak memory 198072 kb
Host smart-e8793aec-1b2d-41c3-950f-143fdb080a97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906475601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3906475601
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.1601356823
Short name T70
Test name
Test status
Simulation time 47942289492 ps
CPU time 771.19 seconds
Started Mar 21 12:40:09 PM PDT 24
Finished Mar 21 12:53:01 PM PDT 24
Peak memory 198012 kb
Host smart-37c59a3c-1f95-47d1-a76b-263e4b64a36c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1601356823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.1601356823
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.4192868113
Short name T229
Test name
Test status
Simulation time 43846469 ps
CPU time 0.56 seconds
Started Mar 21 12:40:09 PM PDT 24
Finished Mar 21 12:40:11 PM PDT 24
Peak memory 193992 kb
Host smart-a021d0aa-27ac-42cc-9395-d071eec276d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192868113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.4192868113
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3334724511
Short name T359
Test name
Test status
Simulation time 59020864 ps
CPU time 0.9 seconds
Started Mar 21 12:40:06 PM PDT 24
Finished Mar 21 12:40:09 PM PDT 24
Peak memory 195384 kb
Host smart-a06642bd-748e-42d6-a117-02bbed9075c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334724511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3334724511
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.319657881
Short name T658
Test name
Test status
Simulation time 5192496643 ps
CPU time 27.66 seconds
Started Mar 21 12:40:09 PM PDT 24
Finished Mar 21 12:40:38 PM PDT 24
Peak memory 196572 kb
Host smart-8efb2381-e596-4518-baa9-12e2303c320b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319657881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.319657881
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3028464776
Short name T624
Test name
Test status
Simulation time 135081970 ps
CPU time 0.72 seconds
Started Mar 21 12:40:10 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 195252 kb
Host smart-61495600-c20b-44d0-aeac-d9b8fb5b017a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028464776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3028464776
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3481489803
Short name T421
Test name
Test status
Simulation time 84507616 ps
CPU time 1.2 seconds
Started Mar 21 12:40:10 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 195988 kb
Host smart-3a55ffff-a074-4dcd-929a-4a9d5554da99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481489803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3481489803
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1202067546
Short name T130
Test name
Test status
Simulation time 351398646 ps
CPU time 1.64 seconds
Started Mar 21 12:39:58 PM PDT 24
Finished Mar 21 12:40:00 PM PDT 24
Peak memory 197912 kb
Host smart-7b77da6e-c9a7-4a78-bc6c-07636758df06
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202067546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1202067546
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1061318207
Short name T138
Test name
Test status
Simulation time 202549771 ps
CPU time 1.46 seconds
Started Mar 21 12:40:06 PM PDT 24
Finished Mar 21 12:40:09 PM PDT 24
Peak memory 196656 kb
Host smart-8e76880b-07e8-40d2-8ca1-ab30cefdb013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061318207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1061318207
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2038653822
Short name T153
Test name
Test status
Simulation time 65179742 ps
CPU time 1.16 seconds
Started Mar 21 12:40:13 PM PDT 24
Finished Mar 21 12:40:14 PM PDT 24
Peak memory 195944 kb
Host smart-495ef966-cfb4-4956-9656-73007c24dd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038653822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2038653822
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.4180347444
Short name T542
Test name
Test status
Simulation time 65374984 ps
CPU time 0.88 seconds
Started Mar 21 12:40:13 PM PDT 24
Finished Mar 21 12:40:14 PM PDT 24
Peak memory 195976 kb
Host smart-9e4357f2-158c-4fd9-998f-425cf6a9fc8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180347444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.4180347444
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.4059103490
Short name T412
Test name
Test status
Simulation time 274239617 ps
CPU time 3.91 seconds
Started Mar 21 12:40:00 PM PDT 24
Finished Mar 21 12:40:05 PM PDT 24
Peak memory 197872 kb
Host smart-94060f5c-c835-4dae-a82c-4ff243e6743f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059103490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.4059103490
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3049311762
Short name T267
Test name
Test status
Simulation time 98628531 ps
CPU time 0.97 seconds
Started Mar 21 12:40:06 PM PDT 24
Finished Mar 21 12:40:09 PM PDT 24
Peak memory 196436 kb
Host smart-3f2bd8b6-96d8-4f2d-9ed3-2aa415cc051c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049311762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3049311762
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.499664322
Short name T647
Test name
Test status
Simulation time 204445020 ps
CPU time 0.74 seconds
Started Mar 21 12:40:16 PM PDT 24
Finished Mar 21 12:40:17 PM PDT 24
Peak memory 195152 kb
Host smart-a67c761b-0cb8-4ec3-af6a-92a042d10ebe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499664322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.499664322
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2662240985
Short name T689
Test name
Test status
Simulation time 30197039182 ps
CPU time 127.68 seconds
Started Mar 21 12:40:05 PM PDT 24
Finished Mar 21 12:42:14 PM PDT 24
Peak memory 198128 kb
Host smart-ca935a50-9d35-49a6-ab05-5433edea06be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662240985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2662240985
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.4150760628
Short name T189
Test name
Test status
Simulation time 21481983 ps
CPU time 0.56 seconds
Started Mar 21 12:40:06 PM PDT 24
Finished Mar 21 12:40:08 PM PDT 24
Peak memory 193764 kb
Host smart-86cd0a2f-d726-45f5-99cd-cc9f33b89699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150760628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.4150760628
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2651452563
Short name T644
Test name
Test status
Simulation time 44297683 ps
CPU time 0.6 seconds
Started Mar 21 12:40:15 PM PDT 24
Finished Mar 21 12:40:16 PM PDT 24
Peak memory 193940 kb
Host smart-2af857da-a86d-4d0c-896b-447558308628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651452563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2651452563
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.657613460
Short name T252
Test name
Test status
Simulation time 1083965786 ps
CPU time 28.01 seconds
Started Mar 21 12:40:12 PM PDT 24
Finished Mar 21 12:40:40 PM PDT 24
Peak memory 196752 kb
Host smart-53faa5a9-3b40-4c3e-a3f1-0eac0e5e4f34
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657613460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.657613460
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.4066487147
Short name T301
Test name
Test status
Simulation time 256074745 ps
CPU time 0.78 seconds
Started Mar 21 12:40:09 PM PDT 24
Finished Mar 21 12:40:11 PM PDT 24
Peak memory 195964 kb
Host smart-8f5faa9a-59ad-4120-ac06-c8c3ab199bfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066487147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.4066487147
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2100136891
Short name T672
Test name
Test status
Simulation time 59951477 ps
CPU time 0.76 seconds
Started Mar 21 12:40:21 PM PDT 24
Finished Mar 21 12:40:22 PM PDT 24
Peak memory 196088 kb
Host smart-71747dbd-2a41-4ef6-bfa6-51c0e3b7aac9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100136891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2100136891
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3106012095
Short name T165
Test name
Test status
Simulation time 46730300 ps
CPU time 1.89 seconds
Started Mar 21 12:40:10 PM PDT 24
Finished Mar 21 12:40:14 PM PDT 24
Peak memory 197900 kb
Host smart-f8a7a3db-915f-4e5a-a759-f30eaed81fb1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106012095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3106012095
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.199389812
Short name T423
Test name
Test status
Simulation time 106414198 ps
CPU time 2.12 seconds
Started Mar 21 12:40:09 PM PDT 24
Finished Mar 21 12:40:14 PM PDT 24
Peak memory 195640 kb
Host smart-ca4275f6-06f3-47be-bc0e-af27ffa52856
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199389812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
199389812
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.4250391180
Short name T244
Test name
Test status
Simulation time 288182129 ps
CPU time 1.29 seconds
Started Mar 21 12:40:04 PM PDT 24
Finished Mar 21 12:40:05 PM PDT 24
Peak memory 196820 kb
Host smart-06369ad5-7c50-48c9-8ce8-a6d848c36535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250391180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.4250391180
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.441241665
Short name T671
Test name
Test status
Simulation time 52485296 ps
CPU time 1.11 seconds
Started Mar 21 12:40:05 PM PDT 24
Finished Mar 21 12:40:06 PM PDT 24
Peak memory 195892 kb
Host smart-d1e66daa-7d9c-453a-b160-76e1678a691d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441241665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.441241665
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1067729352
Short name T257
Test name
Test status
Simulation time 64742854 ps
CPU time 2.98 seconds
Started Mar 21 12:40:10 PM PDT 24
Finished Mar 21 12:40:15 PM PDT 24
Peak memory 197836 kb
Host smart-3c1b78d8-3377-4041-b621-8ac1fdebcd1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067729352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1067729352
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.111837486
Short name T191
Test name
Test status
Simulation time 284226443 ps
CPU time 1.18 seconds
Started Mar 21 12:40:04 PM PDT 24
Finished Mar 21 12:40:05 PM PDT 24
Peak memory 195628 kb
Host smart-2a800386-a2d3-4e3d-b13e-d6821b16c9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111837486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.111837486
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1580040758
Short name T350
Test name
Test status
Simulation time 100847147 ps
CPU time 0.97 seconds
Started Mar 21 12:40:10 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 195536 kb
Host smart-3cc6d25a-dd8e-4080-99c6-af2b83677cd8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580040758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1580040758
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.478414702
Short name T631
Test name
Test status
Simulation time 7183361719 ps
CPU time 38.98 seconds
Started Mar 21 12:40:13 PM PDT 24
Finished Mar 21 12:40:52 PM PDT 24
Peak memory 197980 kb
Host smart-b8d39e65-89c6-4c3d-a8de-19aa559548fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478414702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.478414702
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1040374346
Short name T564
Test name
Test status
Simulation time 32011150 ps
CPU time 0.57 seconds
Started Mar 21 12:40:10 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 194468 kb
Host smart-91493cb7-dacd-4269-8970-429f03d478cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040374346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1040374346
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2565229146
Short name T687
Test name
Test status
Simulation time 204209381 ps
CPU time 0.84 seconds
Started Mar 21 12:40:08 PM PDT 24
Finished Mar 21 12:40:10 PM PDT 24
Peak memory 196420 kb
Host smart-5217a25c-266f-4ce7-bdac-e863caa441c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565229146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2565229146
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1365068912
Short name T346
Test name
Test status
Simulation time 1935053169 ps
CPU time 14.74 seconds
Started Mar 21 12:40:04 PM PDT 24
Finished Mar 21 12:40:19 PM PDT 24
Peak memory 197772 kb
Host smart-48915c0a-0a17-4cbb-95be-a81ca5707363
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365068912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1365068912
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3185218434
Short name T556
Test name
Test status
Simulation time 108220115 ps
CPU time 0.9 seconds
Started Mar 21 12:40:03 PM PDT 24
Finished Mar 21 12:40:04 PM PDT 24
Peak memory 195924 kb
Host smart-7b9e0811-4cfa-4e36-bfe7-1b1cfd593ea3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185218434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3185218434
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.953406586
Short name T474
Test name
Test status
Simulation time 64664596 ps
CPU time 1.24 seconds
Started Mar 21 12:40:17 PM PDT 24
Finished Mar 21 12:40:19 PM PDT 24
Peak memory 196720 kb
Host smart-5d249781-4d17-4db8-98bf-4e0577cc214e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953406586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.953406586
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.637686619
Short name T317
Test name
Test status
Simulation time 38889461 ps
CPU time 0.99 seconds
Started Mar 21 12:40:14 PM PDT 24
Finished Mar 21 12:40:17 PM PDT 24
Peak memory 195912 kb
Host smart-9f81d14e-a52f-466b-851a-3dc29d73b148
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637686619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.637686619
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2148135529
Short name T553
Test name
Test status
Simulation time 781380231 ps
CPU time 3.24 seconds
Started Mar 21 12:40:13 PM PDT 24
Finished Mar 21 12:40:16 PM PDT 24
Peak memory 197016 kb
Host smart-e040e6b3-8803-488d-a8f5-4ad92e6def3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148135529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2148135529
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1815371236
Short name T201
Test name
Test status
Simulation time 182478981 ps
CPU time 1.16 seconds
Started Mar 21 12:40:14 PM PDT 24
Finished Mar 21 12:40:16 PM PDT 24
Peak memory 196868 kb
Host smart-6f9b168d-6785-4c04-99c8-cc808e275927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815371236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1815371236
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2462013223
Short name T248
Test name
Test status
Simulation time 50910789 ps
CPU time 1.08 seconds
Started Mar 21 12:40:04 PM PDT 24
Finished Mar 21 12:40:05 PM PDT 24
Peak memory 195900 kb
Host smart-ae07f505-6239-4915-b314-2ab06857561a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462013223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2462013223
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2049427038
Short name T10
Test name
Test status
Simulation time 2082069962 ps
CPU time 4.97 seconds
Started Mar 21 12:40:16 PM PDT 24
Finished Mar 21 12:40:21 PM PDT 24
Peak memory 197800 kb
Host smart-b0bc86eb-23a6-4c07-8ebc-02a2d91cb50e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049427038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2049427038
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2231076306
Short name T589
Test name
Test status
Simulation time 108503156 ps
CPU time 0.94 seconds
Started Mar 21 12:40:08 PM PDT 24
Finished Mar 21 12:40:11 PM PDT 24
Peak memory 195904 kb
Host smart-caed1448-e135-41d1-8857-0efc7473ea11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231076306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2231076306
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.594891192
Short name T326
Test name
Test status
Simulation time 42608627 ps
CPU time 1.12 seconds
Started Mar 21 12:40:07 PM PDT 24
Finished Mar 21 12:40:10 PM PDT 24
Peak memory 196168 kb
Host smart-61a368a2-df14-4d34-80f8-3b716ce7ba8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594891192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.594891192
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1156413852
Short name T576
Test name
Test status
Simulation time 21154452047 ps
CPU time 134.02 seconds
Started Mar 21 12:40:10 PM PDT 24
Finished Mar 21 12:42:26 PM PDT 24
Peak memory 198032 kb
Host smart-1cfb1aba-fb76-43b9-9e1a-5887cc7ea5c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156413852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1156413852
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2922920237
Short name T602
Test name
Test status
Simulation time 14705271 ps
CPU time 0.58 seconds
Started Mar 21 12:40:24 PM PDT 24
Finished Mar 21 12:40:25 PM PDT 24
Peak memory 193764 kb
Host smart-f1a2d9b0-2aff-415f-b2a1-bd12a1a17555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922920237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2922920237
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1424166803
Short name T357
Test name
Test status
Simulation time 55522744 ps
CPU time 0.78 seconds
Started Mar 21 12:40:09 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 195148 kb
Host smart-83ccff52-31d0-4788-829b-13f17e5f24a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424166803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1424166803
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.863798391
Short name T256
Test name
Test status
Simulation time 407199409 ps
CPU time 22.96 seconds
Started Mar 21 12:40:04 PM PDT 24
Finished Mar 21 12:40:27 PM PDT 24
Peak memory 197840 kb
Host smart-0e61590e-1fe2-430c-8148-16aba93fa946
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863798391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.863798391
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2303468067
Short name T384
Test name
Test status
Simulation time 72886171 ps
CPU time 0.94 seconds
Started Mar 21 12:40:09 PM PDT 24
Finished Mar 21 12:40:11 PM PDT 24
Peak memory 197004 kb
Host smart-44a62f83-95fc-4279-9c78-306404046301
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303468067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2303468067
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.873083921
Short name T582
Test name
Test status
Simulation time 1778353441 ps
CPU time 1.31 seconds
Started Mar 21 12:40:09 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 195672 kb
Host smart-b867f9ab-2c3a-403d-9ea0-fd3997877930
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873083921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.873083921
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3152716233
Short name T378
Test name
Test status
Simulation time 334610088 ps
CPU time 2.2 seconds
Started Mar 21 12:40:11 PM PDT 24
Finished Mar 21 12:40:14 PM PDT 24
Peak memory 196480 kb
Host smart-f5bb6c70-b18f-48c7-8698-da5e68680cdd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152716233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3152716233
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.4088783973
Short name T675
Test name
Test status
Simulation time 121945353 ps
CPU time 1.14 seconds
Started Mar 21 12:40:08 PM PDT 24
Finished Mar 21 12:40:11 PM PDT 24
Peak memory 196536 kb
Host smart-a4aaa75b-5a76-4019-adff-958eec45a6ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088783973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.4088783973
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3940530607
Short name T15
Test name
Test status
Simulation time 27159933 ps
CPU time 0.98 seconds
Started Mar 21 12:40:14 PM PDT 24
Finished Mar 21 12:40:15 PM PDT 24
Peak memory 195852 kb
Host smart-6a39f03b-76d9-4c4e-a7c6-952123cd7448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940530607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3940530607
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2385449755
Short name T376
Test name
Test status
Simulation time 136924751 ps
CPU time 0.8 seconds
Started Mar 21 12:40:08 PM PDT 24
Finished Mar 21 12:40:10 PM PDT 24
Peak memory 195500 kb
Host smart-ac09b6b0-30e4-4e77-a9b1-2337a954bd6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385449755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2385449755
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3687181227
Short name T213
Test name
Test status
Simulation time 607490535 ps
CPU time 2.94 seconds
Started Mar 21 12:40:07 PM PDT 24
Finished Mar 21 12:40:11 PM PDT 24
Peak memory 197896 kb
Host smart-78e3861c-7ecc-44fc-89a4-025418ef5f3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687181227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3687181227
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3106397466
Short name T383
Test name
Test status
Simulation time 284056943 ps
CPU time 1.17 seconds
Started Mar 21 12:40:23 PM PDT 24
Finished Mar 21 12:40:24 PM PDT 24
Peak memory 195328 kb
Host smart-c4d9e07b-8b79-498e-a705-7d05cfd0a240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106397466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3106397466
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3641885771
Short name T58
Test name
Test status
Simulation time 309345493 ps
CPU time 1.31 seconds
Started Mar 21 12:40:10 PM PDT 24
Finished Mar 21 12:40:14 PM PDT 24
Peak memory 196548 kb
Host smart-eb0aa27f-b3ff-43da-8da6-4b0872fabee6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641885771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3641885771
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2798594795
Short name T172
Test name
Test status
Simulation time 10265514386 ps
CPU time 131.62 seconds
Started Mar 21 12:40:10 PM PDT 24
Finished Mar 21 12:42:24 PM PDT 24
Peak memory 198072 kb
Host smart-03dccfd7-80d0-4a00-a7b8-8430bc13c19e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798594795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2798594795
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3750496396
Short name T599
Test name
Test status
Simulation time 57401435 ps
CPU time 0.59 seconds
Started Mar 21 12:40:03 PM PDT 24
Finished Mar 21 12:40:04 PM PDT 24
Peak memory 193728 kb
Host smart-11f1d73c-84a7-47f6-8586-72bcbdb031a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750496396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3750496396
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2586896134
Short name T568
Test name
Test status
Simulation time 16985910 ps
CPU time 0.63 seconds
Started Mar 21 12:40:14 PM PDT 24
Finished Mar 21 12:40:15 PM PDT 24
Peak memory 193936 kb
Host smart-4eaad212-e444-4517-b22f-11266763810d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586896134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2586896134
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3795895415
Short name T554
Test name
Test status
Simulation time 262249319 ps
CPU time 6.59 seconds
Started Mar 21 12:40:27 PM PDT 24
Finished Mar 21 12:40:33 PM PDT 24
Peak memory 195376 kb
Host smart-bc87b445-ab82-418a-9e3b-9729cd10898c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795895415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3795895415
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.879223151
Short name T268
Test name
Test status
Simulation time 29226010 ps
CPU time 0.78 seconds
Started Mar 21 12:40:13 PM PDT 24
Finished Mar 21 12:40:14 PM PDT 24
Peak memory 195784 kb
Host smart-843bb8af-c4a6-4a45-8097-ea0b2d624037
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879223151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.879223151
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3035092540
Short name T562
Test name
Test status
Simulation time 150045013 ps
CPU time 1.56 seconds
Started Mar 21 12:40:09 PM PDT 24
Finished Mar 21 12:40:12 PM PDT 24
Peak memory 197904 kb
Host smart-ffad2dd6-b43a-4b84-94b9-bba5fc269d42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035092540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3035092540
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3857103902
Short name T397
Test name
Test status
Simulation time 36502184 ps
CPU time 1.25 seconds
Started Mar 21 12:40:04 PM PDT 24
Finished Mar 21 12:40:05 PM PDT 24
Peak memory 196180 kb
Host smart-a7e7ce62-3d51-4c58-a617-97e1b9810b69
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857103902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3857103902
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3364553144
Short name T77
Test name
Test status
Simulation time 52591492 ps
CPU time 1.2 seconds
Started Mar 21 12:40:06 PM PDT 24
Finished Mar 21 12:40:09 PM PDT 24
Peak memory 197396 kb
Host smart-69f15670-de2c-4c77-984b-354a8b484c51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364553144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3364553144
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3569076017
Short name T199
Test name
Test status
Simulation time 32267742 ps
CPU time 1.13 seconds
Started Mar 21 12:40:16 PM PDT 24
Finished Mar 21 12:40:18 PM PDT 24
Peak memory 196936 kb
Host smart-77de32d8-beed-447b-9e15-0312239aadf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569076017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3569076017
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1793467596
Short name T683
Test name
Test status
Simulation time 46729908 ps
CPU time 1.02 seconds
Started Mar 21 12:40:11 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 195696 kb
Host smart-285d4e06-9658-48a2-8265-270eb14ce8d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793467596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1793467596
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1830868562
Short name T358
Test name
Test status
Simulation time 98252900 ps
CPU time 1.22 seconds
Started Mar 21 12:40:11 PM PDT 24
Finished Mar 21 12:40:14 PM PDT 24
Peak memory 197892 kb
Host smart-73faf696-6fb9-42a5-92e4-5cbac154a992
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830868562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1830868562
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2660343982
Short name T395
Test name
Test status
Simulation time 37914143 ps
CPU time 1.01 seconds
Started Mar 21 12:40:10 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 196380 kb
Host smart-0d43e164-8af5-4f2d-b477-4069c97bffb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660343982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2660343982
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1834884873
Short name T614
Test name
Test status
Simulation time 53566266 ps
CPU time 1.01 seconds
Started Mar 21 12:40:05 PM PDT 24
Finished Mar 21 12:40:08 PM PDT 24
Peak memory 196316 kb
Host smart-87f89749-4165-4a90-8a13-c7850ab2593f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834884873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1834884873
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1083613493
Short name T1
Test name
Test status
Simulation time 43428435096 ps
CPU time 133.44 seconds
Started Mar 21 12:40:11 PM PDT 24
Finished Mar 21 12:42:26 PM PDT 24
Peak memory 198020 kb
Host smart-04b9e214-055a-4ca8-84ba-fd483a8d5e55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083613493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1083613493
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1508479180
Short name T195
Test name
Test status
Simulation time 17883813 ps
CPU time 0.59 seconds
Started Mar 21 12:40:05 PM PDT 24
Finished Mar 21 12:40:05 PM PDT 24
Peak memory 193800 kb
Host smart-82946856-4565-453f-8246-4ed941557cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508479180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1508479180
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.443497204
Short name T137
Test name
Test status
Simulation time 92783695 ps
CPU time 0.78 seconds
Started Mar 21 12:40:10 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 195736 kb
Host smart-927550c4-0591-4892-9b5e-fdc6f56f6973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443497204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.443497204
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1739943625
Short name T585
Test name
Test status
Simulation time 268160722 ps
CPU time 8.95 seconds
Started Mar 21 12:40:28 PM PDT 24
Finished Mar 21 12:40:37 PM PDT 24
Peak memory 196472 kb
Host smart-cba418d4-e33b-4260-aa21-c03e53d43ddb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739943625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1739943625
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3389115267
Short name T605
Test name
Test status
Simulation time 180488240 ps
CPU time 1.07 seconds
Started Mar 21 12:40:10 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 197748 kb
Host smart-3188f342-6cfb-4df3-86cf-08ad9136184d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389115267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3389115267
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2374829314
Short name T640
Test name
Test status
Simulation time 104515822 ps
CPU time 1.45 seconds
Started Mar 21 12:40:12 PM PDT 24
Finished Mar 21 12:40:14 PM PDT 24
Peak memory 197044 kb
Host smart-db48ec9a-38a8-4da0-a462-8f90c4bf1624
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374829314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2374829314
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3831064746
Short name T375
Test name
Test status
Simulation time 22589095 ps
CPU time 0.89 seconds
Started Mar 21 12:40:03 PM PDT 24
Finished Mar 21 12:40:04 PM PDT 24
Peak memory 196092 kb
Host smart-1eb40eb3-903e-4b6a-a87d-6a254d4da979
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831064746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3831064746
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2318376168
Short name T648
Test name
Test status
Simulation time 317887371 ps
CPU time 2 seconds
Started Mar 21 12:40:14 PM PDT 24
Finished Mar 21 12:40:16 PM PDT 24
Peak memory 196016 kb
Host smart-1733d92f-108f-43c2-92b5-9bc20f3dfc10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318376168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2318376168
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1777181626
Short name T262
Test name
Test status
Simulation time 127142817 ps
CPU time 1.34 seconds
Started Mar 21 12:40:13 PM PDT 24
Finished Mar 21 12:40:14 PM PDT 24
Peak memory 197868 kb
Host smart-d7f24af5-e0fc-4a0d-92d3-e47f984aa16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777181626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1777181626
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3276482548
Short name T645
Test name
Test status
Simulation time 37537943 ps
CPU time 0.91 seconds
Started Mar 21 12:40:12 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 195648 kb
Host smart-61bb20b8-12cf-45ca-87b9-015e8f11df2e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276482548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3276482548
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2168339231
Short name T377
Test name
Test status
Simulation time 993510936 ps
CPU time 4.32 seconds
Started Mar 21 12:40:05 PM PDT 24
Finished Mar 21 12:40:09 PM PDT 24
Peak memory 197812 kb
Host smart-164ca4af-2dce-47d5-80c4-3cdef8f927df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168339231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2168339231
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.898089890
Short name T494
Test name
Test status
Simulation time 138302106 ps
CPU time 0.72 seconds
Started Mar 21 12:40:04 PM PDT 24
Finished Mar 21 12:40:05 PM PDT 24
Peak memory 194176 kb
Host smart-02d699d9-abdc-4c6c-99f3-45a163800698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898089890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.898089890
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1448637715
Short name T651
Test name
Test status
Simulation time 104395388 ps
CPU time 0.93 seconds
Started Mar 21 12:40:11 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 195564 kb
Host smart-34c3e595-fabe-4cc3-96f5-84aa9ef181bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448637715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1448637715
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2889759470
Short name T64
Test name
Test status
Simulation time 7682220962 ps
CPU time 158.4 seconds
Started Mar 21 12:40:13 PM PDT 24
Finished Mar 21 12:42:52 PM PDT 24
Peak memory 198104 kb
Host smart-60a24bb5-23f4-4d12-b5ca-e3a87dd96101
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889759470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2889759470
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3002393525
Short name T66
Test name
Test status
Simulation time 88576011428 ps
CPU time 899.49 seconds
Started Mar 21 12:40:16 PM PDT 24
Finished Mar 21 12:55:16 PM PDT 24
Peak memory 198120 kb
Host smart-da3ab07b-ca16-46c2-a759-a14496535574
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3002393525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3002393525
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1542428453
Short name T292
Test name
Test status
Simulation time 36733932 ps
CPU time 0.57 seconds
Started Mar 21 12:40:21 PM PDT 24
Finished Mar 21 12:40:22 PM PDT 24
Peak memory 193780 kb
Host smart-ce4f9e79-d579-4430-8502-2fd52e564752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542428453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1542428453
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3639934349
Short name T284
Test name
Test status
Simulation time 33201405 ps
CPU time 0.65 seconds
Started Mar 21 12:40:27 PM PDT 24
Finished Mar 21 12:40:28 PM PDT 24
Peak memory 194000 kb
Host smart-992d063c-8717-4d53-a77a-905fb0b5fb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639934349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3639934349
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.4077357817
Short name T473
Test name
Test status
Simulation time 750321367 ps
CPU time 27.83 seconds
Started Mar 21 12:40:35 PM PDT 24
Finished Mar 21 12:41:05 PM PDT 24
Peak memory 196732 kb
Host smart-e4ebe4a2-a3c2-4c76-a8d4-99b056b0bc6f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077357817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.4077357817
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3143961778
Short name T669
Test name
Test status
Simulation time 74619026 ps
CPU time 1.07 seconds
Started Mar 21 12:40:23 PM PDT 24
Finished Mar 21 12:40:25 PM PDT 24
Peak memory 197812 kb
Host smart-42e76c4a-aef2-4f96-bbf8-3c550af3f319
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143961778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3143961778
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1757770652
Short name T222
Test name
Test status
Simulation time 17044375 ps
CPU time 0.7 seconds
Started Mar 21 12:40:23 PM PDT 24
Finished Mar 21 12:40:25 PM PDT 24
Peak memory 194244 kb
Host smart-40749281-065a-4d90-aac3-fd1382f6dabc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757770652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1757770652
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.599740338
Short name T501
Test name
Test status
Simulation time 261432510 ps
CPU time 2.21 seconds
Started Mar 21 12:40:19 PM PDT 24
Finished Mar 21 12:40:22 PM PDT 24
Peak memory 196428 kb
Host smart-6ebfa1fb-bf3a-4054-8084-c1b78f51b532
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599740338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.599740338
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1674290154
Short name T275
Test name
Test status
Simulation time 121463715 ps
CPU time 1.17 seconds
Started Mar 21 12:40:35 PM PDT 24
Finished Mar 21 12:40:38 PM PDT 24
Peak memory 196612 kb
Host smart-a32cf1ed-67e9-4f36-9ff1-43e534fc9a7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674290154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1674290154
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2951570603
Short name T18
Test name
Test status
Simulation time 21917179 ps
CPU time 0.79 seconds
Started Mar 21 12:40:31 PM PDT 24
Finished Mar 21 12:40:32 PM PDT 24
Peak memory 196468 kb
Host smart-ddbb83fe-00c6-43ca-93da-8d2ddc5e088b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951570603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2951570603
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1288696029
Short name T158
Test name
Test status
Simulation time 53705589 ps
CPU time 0.66 seconds
Started Mar 21 12:40:37 PM PDT 24
Finished Mar 21 12:40:40 PM PDT 24
Peak memory 193912 kb
Host smart-da5b6856-1140-48ed-85cb-c6d047188f9c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288696029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1288696029
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.118152870
Short name T521
Test name
Test status
Simulation time 319726024 ps
CPU time 3.81 seconds
Started Mar 21 12:40:18 PM PDT 24
Finished Mar 21 12:40:22 PM PDT 24
Peak memory 197856 kb
Host smart-a88c2d16-487d-4832-8856-9726175556ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118152870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.118152870
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1954110929
Short name T548
Test name
Test status
Simulation time 70203462 ps
CPU time 0.93 seconds
Started Mar 21 12:40:06 PM PDT 24
Finished Mar 21 12:40:08 PM PDT 24
Peak memory 195972 kb
Host smart-3af7d7ec-d4c1-4576-a6eb-c3e62520499e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954110929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1954110929
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2984794145
Short name T691
Test name
Test status
Simulation time 84127105 ps
CPU time 0.84 seconds
Started Mar 21 12:40:08 PM PDT 24
Finished Mar 21 12:40:11 PM PDT 24
Peak memory 196000 kb
Host smart-ede239ee-d8c4-423b-bf10-c5c7820c3e14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984794145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2984794145
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2859737421
Short name T695
Test name
Test status
Simulation time 26991180488 ps
CPU time 96.52 seconds
Started Mar 21 12:40:35 PM PDT 24
Finished Mar 21 12:42:14 PM PDT 24
Peak memory 197980 kb
Host smart-fc1814fc-3ac7-4abb-89ef-e8595cadf274
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859737421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2859737421
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2668101335
Short name T193
Test name
Test status
Simulation time 36281331 ps
CPU time 0.57 seconds
Started Mar 21 12:38:51 PM PDT 24
Finished Mar 21 12:38:51 PM PDT 24
Peak memory 194464 kb
Host smart-85046184-e73f-4484-909c-f0fcdc003702
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668101335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2668101335
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2926463650
Short name T588
Test name
Test status
Simulation time 62342720 ps
CPU time 0.7 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:38:57 PM PDT 24
Peak memory 195104 kb
Host smart-8706fdc1-68d9-488c-a61b-d4ff7a1da1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926463650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2926463650
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2115591490
Short name T666
Test name
Test status
Simulation time 646941176 ps
CPU time 8.65 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:39:03 PM PDT 24
Peak memory 196616 kb
Host smart-2f1fd8bf-49b5-4b21-88fb-b12cc084e0c1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115591490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2115591490
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.614762649
Short name T442
Test name
Test status
Simulation time 60627278 ps
CPU time 0.78 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:38:41 PM PDT 24
Peak memory 195784 kb
Host smart-1f46af25-14de-4b39-beaf-5294b94148ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614762649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.614762649
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.551824925
Short name T285
Test name
Test status
Simulation time 84522616 ps
CPU time 0.94 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:38:58 PM PDT 24
Peak memory 196080 kb
Host smart-e4f05720-6f35-4c94-a788-8a63e620e0bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551824925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.551824925
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3473914962
Short name T429
Test name
Test status
Simulation time 115893304 ps
CPU time 2.39 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:38:58 PM PDT 24
Peak memory 198048 kb
Host smart-ee5325fd-c260-4736-b144-d627b1072095
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473914962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3473914962
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1972908889
Short name T427
Test name
Test status
Simulation time 148582550 ps
CPU time 1.87 seconds
Started Mar 21 12:38:45 PM PDT 24
Finished Mar 21 12:38:48 PM PDT 24
Peak memory 195644 kb
Host smart-ec625ca5-cb66-4a5f-a605-4d42a4fda7e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972908889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1972908889
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3328095517
Short name T703
Test name
Test status
Simulation time 69468364 ps
CPU time 0.94 seconds
Started Mar 21 12:38:46 PM PDT 24
Finished Mar 21 12:38:47 PM PDT 24
Peak memory 196504 kb
Host smart-dc3e3035-726f-4693-9e27-1074d2bd0c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328095517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3328095517
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1175677606
Short name T239
Test name
Test status
Simulation time 62705631 ps
CPU time 1.31 seconds
Started Mar 21 12:38:45 PM PDT 24
Finished Mar 21 12:38:47 PM PDT 24
Peak memory 197940 kb
Host smart-15776c03-617b-47cc-be58-80e81719c42b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175677606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1175677606
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1459655723
Short name T603
Test name
Test status
Simulation time 1596094285 ps
CPU time 3.03 seconds
Started Mar 21 12:38:52 PM PDT 24
Finished Mar 21 12:38:55 PM PDT 24
Peak memory 197892 kb
Host smart-86bd84b7-e11d-4cf4-9d6a-312fa9309110
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459655723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1459655723
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1345980807
Short name T296
Test name
Test status
Simulation time 29409563 ps
CPU time 0.72 seconds
Started Mar 21 12:38:46 PM PDT 24
Finished Mar 21 12:38:47 PM PDT 24
Peak memory 194892 kb
Host smart-17523873-16a9-42e3-b43e-1d83b204f32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345980807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1345980807
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.925659045
Short name T455
Test name
Test status
Simulation time 126257178 ps
CPU time 1.29 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 195696 kb
Host smart-709b7248-3e65-4a1b-98d1-9ca772029caa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925659045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.925659045
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1860296936
Short name T348
Test name
Test status
Simulation time 13122096197 ps
CPU time 43.01 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:39:37 PM PDT 24
Peak memory 198104 kb
Host smart-1403fb00-2b06-42d4-9f15-726a172a0d6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860296936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1860296936
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1721652073
Short name T411
Test name
Test status
Simulation time 54377894335 ps
CPU time 885.56 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:53:39 PM PDT 24
Peak memory 198084 kb
Host smart-9269c07a-effc-44f5-a7df-3297ea1a132f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1721652073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1721652073
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.998892950
Short name T634
Test name
Test status
Simulation time 35402290 ps
CPU time 0.57 seconds
Started Mar 21 12:38:54 PM PDT 24
Finished Mar 21 12:38:56 PM PDT 24
Peak memory 193832 kb
Host smart-a8137108-e801-4418-b769-881ff5a7e43a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998892950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.998892950
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2918993468
Short name T363
Test name
Test status
Simulation time 27393802 ps
CPU time 0.76 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 195152 kb
Host smart-0f6b7442-1dc1-4780-bb89-44101d8da449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918993468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2918993468
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2478683263
Short name T235
Test name
Test status
Simulation time 163140216 ps
CPU time 7.2 seconds
Started Mar 21 12:38:46 PM PDT 24
Finished Mar 21 12:38:53 PM PDT 24
Peak memory 196972 kb
Host smart-9f10eb18-776e-4ae6-bae5-e0f5c4e7465c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478683263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2478683263
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.645151838
Short name T236
Test name
Test status
Simulation time 185004124 ps
CPU time 1.04 seconds
Started Mar 21 12:38:45 PM PDT 24
Finished Mar 21 12:38:47 PM PDT 24
Peak memory 196568 kb
Host smart-3e3b0c94-d748-45c2-99c5-607c0d79bafd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645151838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.645151838
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1956111205
Short name T559
Test name
Test status
Simulation time 89756896 ps
CPU time 0.78 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:38:41 PM PDT 24
Peak memory 196204 kb
Host smart-baf735f4-3150-497e-bda4-189b17bd0b88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956111205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1956111205
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.351731233
Short name T351
Test name
Test status
Simulation time 24244970 ps
CPU time 1.06 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:38:41 PM PDT 24
Peak memory 195932 kb
Host smart-8d6981e9-7bbf-4277-817f-2bc38c2d870c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351731233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.351731233
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3083832742
Short name T136
Test name
Test status
Simulation time 158435159 ps
CPU time 1.41 seconds
Started Mar 21 12:38:45 PM PDT 24
Finished Mar 21 12:38:47 PM PDT 24
Peak memory 196580 kb
Host smart-f1279ef4-93dc-439f-8e09-b495c3a43828
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083832742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3083832742
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3325846662
Short name T59
Test name
Test status
Simulation time 143112419 ps
CPU time 1.27 seconds
Started Mar 21 12:38:48 PM PDT 24
Finished Mar 21 12:38:49 PM PDT 24
Peak memory 196716 kb
Host smart-76c42e9f-663d-4b60-8ed4-e6664f66547d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325846662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3325846662
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3620949038
Short name T367
Test name
Test status
Simulation time 27445124 ps
CPU time 0.78 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:38:41 PM PDT 24
Peak memory 196148 kb
Host smart-8d3466a1-6d27-4f24-a568-e53d6fc795d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620949038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3620949038
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1346051873
Short name T706
Test name
Test status
Simulation time 72905278 ps
CPU time 1.8 seconds
Started Mar 21 12:38:51 PM PDT 24
Finished Mar 21 12:39:03 PM PDT 24
Peak memory 197856 kb
Host smart-6fd00aa4-28b7-43a6-a738-ecae335bcc04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346051873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1346051873
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3719442950
Short name T115
Test name
Test status
Simulation time 60967475 ps
CPU time 0.77 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:38:58 PM PDT 24
Peak memory 195164 kb
Host smart-dc412364-e14b-4a31-baf9-54350f9185a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719442950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3719442950
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.791359288
Short name T60
Test name
Test status
Simulation time 67675420 ps
CPU time 1.3 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 197824 kb
Host smart-e0339d62-cd41-4324-9760-37f4617da099
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791359288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.791359288
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.4225692102
Short name T708
Test name
Test status
Simulation time 7261738852 ps
CPU time 176.74 seconds
Started Mar 21 12:38:41 PM PDT 24
Finished Mar 21 12:41:39 PM PDT 24
Peak memory 198000 kb
Host smart-f4c286f8-5f68-4832-ae58-d35f6b0466b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225692102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.4225692102
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2824585041
Short name T407
Test name
Test status
Simulation time 13083586 ps
CPU time 0.59 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:38:55 PM PDT 24
Peak memory 192632 kb
Host smart-2e69c54e-4f44-4d87-b2b6-9ea1d4311213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824585041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2824585041
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3408949026
Short name T174
Test name
Test status
Simulation time 265804992 ps
CPU time 0.85 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:38:58 PM PDT 24
Peak memory 197232 kb
Host smart-d1919e67-7ebb-44d2-9473-f0cdaa2bcfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408949026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3408949026
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1664551533
Short name T162
Test name
Test status
Simulation time 784098521 ps
CPU time 19.55 seconds
Started Mar 21 12:38:54 PM PDT 24
Finished Mar 21 12:39:15 PM PDT 24
Peak memory 195380 kb
Host smart-48b8be09-bd64-456f-b94c-9c7e0785747f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664551533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1664551533
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2760655833
Short name T242
Test name
Test status
Simulation time 129106174 ps
CPU time 1.05 seconds
Started Mar 21 12:38:54 PM PDT 24
Finished Mar 21 12:38:56 PM PDT 24
Peak memory 196476 kb
Host smart-eff1b40b-9692-44f7-8f0b-fe78d696a444
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760655833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2760655833
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.265546263
Short name T118
Test name
Test status
Simulation time 71379612 ps
CPU time 1.14 seconds
Started Mar 21 12:38:39 PM PDT 24
Finished Mar 21 12:38:40 PM PDT 24
Peak memory 196480 kb
Host smart-eb44eb4d-ecb8-4e80-893e-154530301ef0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265546263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.265546263
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3248519060
Short name T517
Test name
Test status
Simulation time 176576606 ps
CPU time 3.28 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:38:57 PM PDT 24
Peak memory 197936 kb
Host smart-0b9f8dc2-af35-4ef3-8d2b-b31d9c4cb77d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248519060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3248519060
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2476082324
Short name T360
Test name
Test status
Simulation time 296789744 ps
CPU time 3.12 seconds
Started Mar 21 12:38:50 PM PDT 24
Finished Mar 21 12:38:53 PM PDT 24
Peak memory 197876 kb
Host smart-e269798b-7034-4f46-9e2c-682fdfee1f26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476082324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2476082324
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.4192398106
Short name T320
Test name
Test status
Simulation time 20870014 ps
CPU time 0.82 seconds
Started Mar 21 12:38:41 PM PDT 24
Finished Mar 21 12:38:43 PM PDT 24
Peak memory 196500 kb
Host smart-d1428698-ff50-4fb1-8a5b-bdb975e40e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192398106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.4192398106
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.304911837
Short name T516
Test name
Test status
Simulation time 24627270 ps
CPU time 0.99 seconds
Started Mar 21 12:38:52 PM PDT 24
Finished Mar 21 12:38:53 PM PDT 24
Peak memory 196564 kb
Host smart-7d3fd91c-6ea0-4901-8903-d769d742f114
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304911837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.304911837
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2447401654
Short name T532
Test name
Test status
Simulation time 85301080 ps
CPU time 1.71 seconds
Started Mar 21 12:38:52 PM PDT 24
Finished Mar 21 12:38:55 PM PDT 24
Peak memory 197748 kb
Host smart-f42bf590-bfc2-4063-804c-3e095f67b706
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447401654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2447401654
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1124237099
Short name T215
Test name
Test status
Simulation time 527577233 ps
CPU time 1.21 seconds
Started Mar 21 12:38:49 PM PDT 24
Finished Mar 21 12:38:51 PM PDT 24
Peak memory 196096 kb
Host smart-358ff1d9-2ad9-4f47-96a3-f2a507892d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124237099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1124237099
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2931217863
Short name T355
Test name
Test status
Simulation time 43075896 ps
CPU time 1 seconds
Started Mar 21 12:38:46 PM PDT 24
Finished Mar 21 12:38:47 PM PDT 24
Peak memory 195360 kb
Host smart-6a3d8e1f-59c2-4304-90c2-db32ebfe93f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931217863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2931217863
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1605825025
Short name T194
Test name
Test status
Simulation time 17534327789 ps
CPU time 125.35 seconds
Started Mar 21 12:38:49 PM PDT 24
Finished Mar 21 12:40:54 PM PDT 24
Peak memory 198004 kb
Host smart-f8236813-913c-48b9-9c62-231e855a067c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605825025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1605825025
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.3432739226
Short name T67
Test name
Test status
Simulation time 33173141191 ps
CPU time 774.39 seconds
Started Mar 21 12:38:48 PM PDT 24
Finished Mar 21 12:51:43 PM PDT 24
Peak memory 198092 kb
Host smart-3e092449-4966-44a3-99c2-0b523699c52d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3432739226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.3432739226
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2570272952
Short name T662
Test name
Test status
Simulation time 37221290 ps
CPU time 0.56 seconds
Started Mar 21 12:38:50 PM PDT 24
Finished Mar 21 12:38:51 PM PDT 24
Peak memory 193964 kb
Host smart-13cd596e-1088-4f12-8959-dd7dffd317b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570272952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2570272952
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1645974147
Short name T251
Test name
Test status
Simulation time 74349084 ps
CPU time 0.63 seconds
Started Mar 21 12:39:00 PM PDT 24
Finished Mar 21 12:39:01 PM PDT 24
Peak memory 194008 kb
Host smart-a0883056-ac9e-457d-ad4f-5d1efd6d4c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645974147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1645974147
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3391422980
Short name T37
Test name
Test status
Simulation time 187954007 ps
CPU time 3 seconds
Started Mar 21 12:38:46 PM PDT 24
Finished Mar 21 12:38:49 PM PDT 24
Peak memory 195564 kb
Host smart-fd9e52c7-720a-45dc-a71d-1fb7732c3b33
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391422980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3391422980
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1505271994
Short name T461
Test name
Test status
Simulation time 67459338 ps
CPU time 0.99 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:38:55 PM PDT 24
Peak memory 197712 kb
Host smart-71fc35c7-2aca-40c8-8bd0-81f7abb955b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505271994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1505271994
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2248950680
Short name T531
Test name
Test status
Simulation time 278924933 ps
CPU time 1.15 seconds
Started Mar 21 12:38:51 PM PDT 24
Finished Mar 21 12:38:52 PM PDT 24
Peak memory 196648 kb
Host smart-cf8dc2e8-5d27-41bf-9b86-a5743434e54f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248950680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2248950680
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3656898025
Short name T538
Test name
Test status
Simulation time 72807384 ps
CPU time 0.91 seconds
Started Mar 21 12:38:46 PM PDT 24
Finished Mar 21 12:38:47 PM PDT 24
Peak memory 196012 kb
Host smart-bba9772b-a27b-4ab7-8ac4-058109f717e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656898025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3656898025
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2414347541
Short name T611
Test name
Test status
Simulation time 1683329847 ps
CPU time 2.71 seconds
Started Mar 21 12:38:45 PM PDT 24
Finished Mar 21 12:38:48 PM PDT 24
Peak memory 196984 kb
Host smart-8fb0fd41-3a3e-441b-a41f-559952092fbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414347541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2414347541
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1953858262
Short name T203
Test name
Test status
Simulation time 348588343 ps
CPU time 0.92 seconds
Started Mar 21 12:38:41 PM PDT 24
Finished Mar 21 12:38:43 PM PDT 24
Peak memory 196464 kb
Host smart-278a708d-69b9-408e-879b-112689ee3772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953858262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1953858262
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1742277632
Short name T625
Test name
Test status
Simulation time 62787375 ps
CPU time 0.65 seconds
Started Mar 21 12:38:47 PM PDT 24
Finished Mar 21 12:38:48 PM PDT 24
Peak memory 194144 kb
Host smart-d05d8548-ef25-418f-9167-aa9f50d839ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742277632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1742277632
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.302072115
Short name T515
Test name
Test status
Simulation time 358165827 ps
CPU time 4.23 seconds
Started Mar 21 12:38:52 PM PDT 24
Finished Mar 21 12:38:57 PM PDT 24
Peak memory 197800 kb
Host smart-d2ba3664-4115-4e72-bed6-ad23b028ff08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302072115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.302072115
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1265665508
Short name T674
Test name
Test status
Simulation time 467697563 ps
CPU time 1.16 seconds
Started Mar 21 12:38:41 PM PDT 24
Finished Mar 21 12:38:43 PM PDT 24
Peak memory 195664 kb
Host smart-95586ef4-35b5-40a6-b264-46bae6c89e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265665508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1265665508
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.4021078977
Short name T121
Test name
Test status
Simulation time 69997356 ps
CPU time 0.77 seconds
Started Mar 21 12:38:47 PM PDT 24
Finished Mar 21 12:38:48 PM PDT 24
Peak memory 194388 kb
Host smart-c08dc934-b69c-43a5-b79b-b49f1dd8d23f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021078977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.4021078977
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.388389675
Short name T693
Test name
Test status
Simulation time 15013312949 ps
CPU time 195.19 seconds
Started Mar 21 12:38:48 PM PDT 24
Finished Mar 21 12:42:03 PM PDT 24
Peak memory 198080 kb
Host smart-3df0c94e-964c-46f4-bd5f-f113ced8629f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388389675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.388389675
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3669439398
Short name T68
Test name
Test status
Simulation time 403550999674 ps
CPU time 1857.29 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 01:09:58 PM PDT 24
Peak memory 198160 kb
Host smart-338e17bf-218f-4592-b4c9-7b8c576782b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3669439398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3669439398
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1846134686
Short name T414
Test name
Test status
Simulation time 46768509 ps
CPU time 0.55 seconds
Started Mar 21 12:38:48 PM PDT 24
Finished Mar 21 12:38:49 PM PDT 24
Peak memory 193712 kb
Host smart-7016a1c0-f769-47cf-9018-dea6f6d3c44e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846134686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1846134686
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1539899158
Short name T34
Test name
Test status
Simulation time 46135910 ps
CPU time 0.89 seconds
Started Mar 21 12:38:52 PM PDT 24
Finished Mar 21 12:38:53 PM PDT 24
Peak memory 196248 kb
Host smart-bd26f323-ff7c-47b6-9a87-7fc4ad7e3550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539899158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1539899158
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2911707657
Short name T175
Test name
Test status
Simulation time 2533502825 ps
CPU time 22.13 seconds
Started Mar 21 12:38:56 PM PDT 24
Finished Mar 21 12:39:21 PM PDT 24
Peak memory 197968 kb
Host smart-df6b29a5-c43e-44bc-bcb0-d47e827ea54b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911707657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2911707657
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.83572102
Short name T261
Test name
Test status
Simulation time 43913565 ps
CPU time 0.65 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:38:54 PM PDT 24
Peak memory 195092 kb
Host smart-9adb2b67-c36f-4d88-a20b-b4cbc6d750cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83572102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.83572102
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1005116556
Short name T622
Test name
Test status
Simulation time 398876722 ps
CPU time 1.41 seconds
Started Mar 21 12:38:41 PM PDT 24
Finished Mar 21 12:38:44 PM PDT 24
Peak memory 195736 kb
Host smart-3f1388dc-3824-437d-9f04-965b5e4ba40a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005116556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1005116556
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2585820352
Short name T72
Test name
Test status
Simulation time 101052825 ps
CPU time 3.82 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:38:57 PM PDT 24
Peak memory 197984 kb
Host smart-db524b23-3b95-40c6-a857-9a32974f6777
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585820352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2585820352
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3624990435
Short name T19
Test name
Test status
Simulation time 89212069 ps
CPU time 2.59 seconds
Started Mar 21 12:38:50 PM PDT 24
Finished Mar 21 12:38:53 PM PDT 24
Peak memory 197872 kb
Host smart-f5875682-5a49-449a-995a-ef9c74fc1bd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624990435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3624990435
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1789362595
Short name T526
Test name
Test status
Simulation time 47131830 ps
CPU time 1.01 seconds
Started Mar 21 12:38:41 PM PDT 24
Finished Mar 21 12:38:43 PM PDT 24
Peak memory 196556 kb
Host smart-43bb2914-0aa6-40a5-a68f-a7f553e65c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789362595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1789362595
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.212300865
Short name T508
Test name
Test status
Simulation time 78350868 ps
CPU time 0.97 seconds
Started Mar 21 12:38:56 PM PDT 24
Finished Mar 21 12:38:59 PM PDT 24
Peak memory 195656 kb
Host smart-1dbef6e0-29e5-4dae-b2a2-6bbc3c124799
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212300865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.212300865
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.594876098
Short name T269
Test name
Test status
Simulation time 94558736 ps
CPU time 1.94 seconds
Started Mar 21 12:38:54 PM PDT 24
Finished Mar 21 12:38:58 PM PDT 24
Peak memory 197852 kb
Host smart-8c9e0213-68a5-4561-8597-1e7a3e1d93ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594876098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.594876098
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2877054075
Short name T308
Test name
Test status
Simulation time 148607704 ps
CPU time 1.37 seconds
Started Mar 21 12:38:53 PM PDT 24
Finished Mar 21 12:38:55 PM PDT 24
Peak memory 197916 kb
Host smart-22cae471-3cbb-4aff-a84f-62ea84807983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877054075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2877054075
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.4060892472
Short name T335
Test name
Test status
Simulation time 148736704 ps
CPU time 0.82 seconds
Started Mar 21 12:38:57 PM PDT 24
Finished Mar 21 12:39:00 PM PDT 24
Peak memory 195272 kb
Host smart-3bbb127a-f575-4633-87f7-811dffedf2a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060892472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.4060892472
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1092204007
Short name T500
Test name
Test status
Simulation time 77536000839 ps
CPU time 139.72 seconds
Started Mar 21 12:38:55 PM PDT 24
Finished Mar 21 12:41:15 PM PDT 24
Peak memory 197984 kb
Host smart-7d6e1727-8f2b-403b-bf15-d956080356b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092204007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1092204007
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1929217643
Short name T893
Test name
Test status
Simulation time 404338173 ps
CPU time 1.03 seconds
Started Mar 21 02:35:30 PM PDT 24
Finished Mar 21 02:35:31 PM PDT 24
Peak memory 198640 kb
Host smart-1504ddbd-3e1c-48ab-ba43-a18d4c4a1cc1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1929217643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1929217643
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4117411051
Short name T871
Test name
Test status
Simulation time 191042416 ps
CPU time 1.07 seconds
Started Mar 21 02:35:41 PM PDT 24
Finished Mar 21 02:35:42 PM PDT 24
Peak memory 192340 kb
Host smart-c520dbed-1e01-40d7-9506-ed1c2b3a2c26
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117411051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4117411051
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.179449976
Short name T906
Test name
Test status
Simulation time 270589746 ps
CPU time 1.52 seconds
Started Mar 21 02:35:42 PM PDT 24
Finished Mar 21 02:35:44 PM PDT 24
Peak memory 192328 kb
Host smart-311fb0f2-8839-4f3f-a9c5-742148ef1aa2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=179449976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.179449976
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3272355590
Short name T839
Test name
Test status
Simulation time 77544418 ps
CPU time 1.19 seconds
Started Mar 21 02:35:43 PM PDT 24
Finished Mar 21 02:35:44 PM PDT 24
Peak memory 198616 kb
Host smart-18210f00-36fc-4cef-8d33-933969769107
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272355590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3272355590
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.444706233
Short name T877
Test name
Test status
Simulation time 246031841 ps
CPU time 1.41 seconds
Started Mar 21 02:35:44 PM PDT 24
Finished Mar 21 02:35:45 PM PDT 24
Peak memory 198212 kb
Host smart-53387c51-e4c1-4a28-8daa-2c5738c159a8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=444706233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.444706233
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.730488838
Short name T891
Test name
Test status
Simulation time 86458491 ps
CPU time 1.25 seconds
Started Mar 21 02:35:45 PM PDT 24
Finished Mar 21 02:35:46 PM PDT 24
Peak memory 192332 kb
Host smart-3576cda7-e78b-4140-a50a-1e6b3f43b7ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730488838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.730488838
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3747426727
Short name T926
Test name
Test status
Simulation time 381195982 ps
CPU time 1.46 seconds
Started Mar 21 02:35:42 PM PDT 24
Finished Mar 21 02:35:44 PM PDT 24
Peak memory 198600 kb
Host smart-d0940e87-4a4e-4692-9c7c-6935b9497218
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3747426727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3747426727
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2735918225
Short name T838
Test name
Test status
Simulation time 197691225 ps
CPU time 0.97 seconds
Started Mar 21 02:35:41 PM PDT 24
Finished Mar 21 02:35:42 PM PDT 24
Peak memory 192180 kb
Host smart-d9e399a3-8b95-4985-b3be-ad39b762b7e4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735918225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2735918225
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2927535749
Short name T870
Test name
Test status
Simulation time 70649307 ps
CPU time 1.28 seconds
Started Mar 21 02:35:49 PM PDT 24
Finished Mar 21 02:35:51 PM PDT 24
Peak memory 192328 kb
Host smart-3ce82b0f-9be4-4bdf-bf70-5ceccb4f181e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2927535749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2927535749
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4272987785
Short name T874
Test name
Test status
Simulation time 225596226 ps
CPU time 1.5 seconds
Started Mar 21 02:35:45 PM PDT 24
Finished Mar 21 02:35:46 PM PDT 24
Peak memory 197996 kb
Host smart-88146999-610c-4bb1-96a9-0fcb91a9963d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272987785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4272987785
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2553222175
Short name T933
Test name
Test status
Simulation time 35051063 ps
CPU time 1.27 seconds
Started Mar 21 02:35:49 PM PDT 24
Finished Mar 21 02:35:51 PM PDT 24
Peak memory 198612 kb
Host smart-54a55b5d-c985-4eb4-bbd6-a73551a59289
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2553222175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2553222175
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1265980473
Short name T844
Test name
Test status
Simulation time 38685170 ps
CPU time 1.1 seconds
Started Mar 21 02:35:43 PM PDT 24
Finished Mar 21 02:35:44 PM PDT 24
Peak memory 192364 kb
Host smart-54bff5ea-3b11-4f39-b3b7-f38173075b00
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265980473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1265980473
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1382766843
Short name T897
Test name
Test status
Simulation time 441977997 ps
CPU time 1.14 seconds
Started Mar 21 02:35:43 PM PDT 24
Finished Mar 21 02:35:44 PM PDT 24
Peak memory 198664 kb
Host smart-b2da0220-2301-405f-8904-bce6bca63474
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1382766843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1382766843
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2329117019
Short name T903
Test name
Test status
Simulation time 762763081 ps
CPU time 1.13 seconds
Started Mar 21 02:35:45 PM PDT 24
Finished Mar 21 02:35:46 PM PDT 24
Peak memory 192352 kb
Host smart-a648fcd5-7d79-4c36-a254-bc1dac0a10da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329117019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2329117019
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.886356091
Short name T847
Test name
Test status
Simulation time 112376211 ps
CPU time 0.85 seconds
Started Mar 21 02:35:45 PM PDT 24
Finished Mar 21 02:35:46 PM PDT 24
Peak memory 192156 kb
Host smart-4558ed58-41a1-4332-a03b-451f27255a96
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=886356091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.886356091
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2032973342
Short name T912
Test name
Test status
Simulation time 40947973 ps
CPU time 1.21 seconds
Started Mar 21 02:35:44 PM PDT 24
Finished Mar 21 02:35:45 PM PDT 24
Peak memory 192304 kb
Host smart-d084d48d-bdc8-4481-b09b-da997761eb86
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032973342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2032973342
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4192403109
Short name T853
Test name
Test status
Simulation time 76568635 ps
CPU time 1.2 seconds
Started Mar 21 02:35:45 PM PDT 24
Finished Mar 21 02:35:46 PM PDT 24
Peak memory 192320 kb
Host smart-ab60783a-afd8-4850-94c3-140e4b829295
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4192403109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.4192403109
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3678850297
Short name T905
Test name
Test status
Simulation time 310330659 ps
CPU time 1.06 seconds
Started Mar 21 02:35:44 PM PDT 24
Finished Mar 21 02:35:45 PM PDT 24
Peak memory 192312 kb
Host smart-93847642-6bf7-411f-a82d-dbfeafd709ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678850297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3678850297
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.983472582
Short name T908
Test name
Test status
Simulation time 55376130 ps
CPU time 1.27 seconds
Started Mar 21 02:35:42 PM PDT 24
Finished Mar 21 02:35:43 PM PDT 24
Peak memory 192328 kb
Host smart-22acb228-b014-495a-ae71-deba38abaa89
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=983472582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.983472582
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.538657309
Short name T846
Test name
Test status
Simulation time 49398013 ps
CPU time 1.01 seconds
Started Mar 21 02:35:44 PM PDT 24
Finished Mar 21 02:35:45 PM PDT 24
Peak memory 192168 kb
Host smart-495151fb-c2bc-48ca-b284-9a2a8b715caf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538657309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.538657309
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.4117892442
Short name T841
Test name
Test status
Simulation time 151908289 ps
CPU time 1.27 seconds
Started Mar 21 02:35:43 PM PDT 24
Finished Mar 21 02:35:44 PM PDT 24
Peak memory 192364 kb
Host smart-bfde41e4-8cb2-4ae4-95a3-7836d2788a50
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4117892442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.4117892442
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3409922006
Short name T876
Test name
Test status
Simulation time 42414105 ps
CPU time 1.38 seconds
Started Mar 21 02:35:41 PM PDT 24
Finished Mar 21 02:35:43 PM PDT 24
Peak memory 192332 kb
Host smart-1b77c6b5-fe02-4d46-ac4f-ba3395f8e5fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409922006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3409922006
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3741434036
Short name T923
Test name
Test status
Simulation time 99371580 ps
CPU time 1.51 seconds
Started Mar 21 02:35:55 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 192296 kb
Host smart-ee85f3a6-8071-4775-9c14-d6c6342a60ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3741434036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3741434036
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2712495363
Short name T855
Test name
Test status
Simulation time 75117043 ps
CPU time 1.12 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 192384 kb
Host smart-cc534f91-27c8-403a-881e-0e2f81ac18a9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712495363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2712495363
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1457916973
Short name T918
Test name
Test status
Simulation time 194957569 ps
CPU time 1.62 seconds
Started Mar 21 02:35:42 PM PDT 24
Finished Mar 21 02:35:43 PM PDT 24
Peak memory 192308 kb
Host smart-b507030f-1cd5-4790-8271-f61a59669977
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1457916973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1457916973
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2788896552
Short name T925
Test name
Test status
Simulation time 187763186 ps
CPU time 0.99 seconds
Started Mar 21 02:35:45 PM PDT 24
Finished Mar 21 02:35:46 PM PDT 24
Peak memory 192356 kb
Host smart-51fa8d2e-7379-492f-bddc-c4f321a40de0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788896552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2788896552
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3370509126
Short name T863
Test name
Test status
Simulation time 75471698 ps
CPU time 0.91 seconds
Started Mar 21 02:36:00 PM PDT 24
Finished Mar 21 02:36:01 PM PDT 24
Peak memory 196712 kb
Host smart-2124d8e2-a3fe-4e87-a53f-22a99a2ba5d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3370509126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3370509126
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4060190319
Short name T849
Test name
Test status
Simulation time 46893215 ps
CPU time 1.39 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:58 PM PDT 24
Peak memory 192332 kb
Host smart-98c6c5d3-0171-4638-8c8e-f1a439312b45
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060190319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4060190319
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3201551488
Short name T851
Test name
Test status
Simulation time 411777223 ps
CPU time 1.37 seconds
Started Mar 21 02:35:54 PM PDT 24
Finished Mar 21 02:35:55 PM PDT 24
Peak memory 192232 kb
Host smart-8f21abbe-8c67-4f1c-ad1b-0a6cb87a1ba3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3201551488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3201551488
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3287141495
Short name T879
Test name
Test status
Simulation time 190739579 ps
CPU time 0.97 seconds
Started Mar 21 02:35:54 PM PDT 24
Finished Mar 21 02:35:55 PM PDT 24
Peak memory 192120 kb
Host smart-3de5d521-fe38-432c-ab5f-7cd392cc0cfd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287141495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3287141495
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.4178582663
Short name T894
Test name
Test status
Simulation time 45693697 ps
CPU time 0.97 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 196888 kb
Host smart-57819626-1d7d-4c64-971d-ecf170b98f90
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4178582663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.4178582663
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.67824874
Short name T901
Test name
Test status
Simulation time 212368754 ps
CPU time 1.24 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 192308 kb
Host smart-101ec371-b4ae-4f37-b663-9e999a196d5f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67824874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.67824874
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3928099069
Short name T898
Test name
Test status
Simulation time 94479071 ps
CPU time 0.79 seconds
Started Mar 21 02:36:00 PM PDT 24
Finished Mar 21 02:36:01 PM PDT 24
Peak memory 196724 kb
Host smart-96046a56-e471-47e5-aaee-d2c2295a0360
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3928099069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3928099069
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1924156039
Short name T913
Test name
Test status
Simulation time 102269067 ps
CPU time 1.5 seconds
Started Mar 21 02:35:57 PM PDT 24
Finished Mar 21 02:35:59 PM PDT 24
Peak memory 192308 kb
Host smart-e6210c61-fd7b-48d4-b020-31bdcfc85281
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924156039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1924156039
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.4178103226
Short name T854
Test name
Test status
Simulation time 67821556 ps
CPU time 1.31 seconds
Started Mar 21 02:35:55 PM PDT 24
Finished Mar 21 02:35:56 PM PDT 24
Peak memory 192296 kb
Host smart-cc5f14fb-96d1-4b27-b627-3d16ae8040fb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4178103226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.4178103226
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3268697705
Short name T899
Test name
Test status
Simulation time 173636964 ps
CPU time 1.07 seconds
Started Mar 21 02:36:07 PM PDT 24
Finished Mar 21 02:36:09 PM PDT 24
Peak memory 192360 kb
Host smart-65a515f2-4845-4c8c-931e-36dbed6f6d52
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268697705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3268697705
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.260776879
Short name T858
Test name
Test status
Simulation time 68691306 ps
CPU time 1.43 seconds
Started Mar 21 02:35:55 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 192332 kb
Host smart-0b1be3dd-5885-41fe-aa87-ba6b0d5aa3c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=260776879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.260776879
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2120134388
Short name T882
Test name
Test status
Simulation time 125385281 ps
CPU time 1.39 seconds
Started Mar 21 02:35:57 PM PDT 24
Finished Mar 21 02:35:59 PM PDT 24
Peak memory 192380 kb
Host smart-c74233e5-3ec6-4c05-9ad8-014a9c2fe397
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120134388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2120134388
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.333564157
Short name T896
Test name
Test status
Simulation time 357891801 ps
CPU time 1.4 seconds
Started Mar 21 02:36:00 PM PDT 24
Finished Mar 21 02:36:02 PM PDT 24
Peak memory 192320 kb
Host smart-412eb09c-524b-4cdd-be04-1a2e7c62904b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=333564157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.333564157
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3951734986
Short name T862
Test name
Test status
Simulation time 88922276 ps
CPU time 1.03 seconds
Started Mar 21 02:35:57 PM PDT 24
Finished Mar 21 02:35:58 PM PDT 24
Peak memory 192124 kb
Host smart-9ffa3a6e-5dae-4263-bc6b-4566afaa43b6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951734986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3951734986
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3352560977
Short name T885
Test name
Test status
Simulation time 100362116 ps
CPU time 1.49 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 192304 kb
Host smart-a19a2df7-bda0-4366-ba15-0cbdcaca8fd3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3352560977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3352560977
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3467862821
Short name T864
Test name
Test status
Simulation time 320821418 ps
CPU time 1.51 seconds
Started Mar 21 02:36:00 PM PDT 24
Finished Mar 21 02:36:02 PM PDT 24
Peak memory 198628 kb
Host smart-38df35a5-1540-48a5-bdb6-42c8fff906ed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467862821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3467862821
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.229591808
Short name T852
Test name
Test status
Simulation time 37435716 ps
CPU time 1.2 seconds
Started Mar 21 02:36:01 PM PDT 24
Finished Mar 21 02:36:03 PM PDT 24
Peak memory 192324 kb
Host smart-e5c05e62-f162-4b19-86db-8a531161403e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=229591808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.229591808
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2836062836
Short name T880
Test name
Test status
Simulation time 210207498 ps
CPU time 1.58 seconds
Started Mar 21 02:35:54 PM PDT 24
Finished Mar 21 02:35:56 PM PDT 24
Peak memory 198632 kb
Host smart-3245e286-38f2-4e59-ac2f-378a2b368ae4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836062836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2836062836
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1436644654
Short name T859
Test name
Test status
Simulation time 237292433 ps
CPU time 1.2 seconds
Started Mar 21 02:35:57 PM PDT 24
Finished Mar 21 02:35:58 PM PDT 24
Peak memory 192316 kb
Host smart-12287c9e-e40a-431d-8e90-f81293ff0cdc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1436644654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1436644654
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1420769649
Short name T866
Test name
Test status
Simulation time 50083671 ps
CPU time 1.46 seconds
Started Mar 21 02:35:54 PM PDT 24
Finished Mar 21 02:35:56 PM PDT 24
Peak memory 192284 kb
Host smart-ac350839-9f48-4b87-a4d3-adcdab9537a6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420769649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1420769649
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3773737154
Short name T873
Test name
Test status
Simulation time 38356204 ps
CPU time 1.24 seconds
Started Mar 21 02:35:43 PM PDT 24
Finished Mar 21 02:35:44 PM PDT 24
Peak memory 191812 kb
Host smart-e9522937-4828-412e-bf6a-7e2cb41f0d28
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3773737154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3773737154
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3359438868
Short name T842
Test name
Test status
Simulation time 59460649 ps
CPU time 1.21 seconds
Started Mar 21 02:35:44 PM PDT 24
Finished Mar 21 02:35:46 PM PDT 24
Peak memory 198688 kb
Host smart-39915a08-e862-45d2-aa9f-6179a73df2c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359438868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3359438868
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2111319342
Short name T904
Test name
Test status
Simulation time 284284743 ps
CPU time 0.89 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 198456 kb
Host smart-9a46b910-9c49-4bce-9836-a893422b01e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2111319342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2111319342
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4182375443
Short name T857
Test name
Test status
Simulation time 148998507 ps
CPU time 1.52 seconds
Started Mar 21 02:35:55 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 192320 kb
Host smart-b4af435d-8056-4cd5-b6e8-1ca7e163b6d8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182375443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4182375443
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3349548633
Short name T916
Test name
Test status
Simulation time 189848017 ps
CPU time 1.07 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 192336 kb
Host smart-49bde894-7340-4948-8ec5-77481f7a640c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3349548633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3349548633
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2909624061
Short name T861
Test name
Test status
Simulation time 62046461 ps
CPU time 1.05 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 192256 kb
Host smart-49b95444-e8a9-4ec1-bfc8-4e3ec54b1a4c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909624061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2909624061
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.591942937
Short name T878
Test name
Test status
Simulation time 287472561 ps
CPU time 1.4 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 192256 kb
Host smart-289c7c24-f53b-468a-b996-115de9ff5b01
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=591942937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.591942937
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4007784236
Short name T845
Test name
Test status
Simulation time 48117447 ps
CPU time 1.1 seconds
Started Mar 21 02:36:01 PM PDT 24
Finished Mar 21 02:36:02 PM PDT 24
Peak memory 198392 kb
Host smart-ef973ab6-bc34-4019-ac7e-9c44e845ccb0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007784236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4007784236
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1848831503
Short name T924
Test name
Test status
Simulation time 36943814 ps
CPU time 0.86 seconds
Started Mar 21 02:36:00 PM PDT 24
Finished Mar 21 02:36:02 PM PDT 24
Peak memory 191832 kb
Host smart-29eef56f-09a4-4fe7-955d-454128f241e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1848831503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1848831503
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2696363629
Short name T931
Test name
Test status
Simulation time 97022160 ps
CPU time 1.6 seconds
Started Mar 21 02:35:57 PM PDT 24
Finished Mar 21 02:35:59 PM PDT 24
Peak memory 192360 kb
Host smart-d3fa8c69-3dac-4fe3-a8e5-6ce932e76e05
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696363629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2696363629
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2264452878
Short name T919
Test name
Test status
Simulation time 75715486 ps
CPU time 0.9 seconds
Started Mar 21 02:36:01 PM PDT 24
Finished Mar 21 02:36:02 PM PDT 24
Peak memory 192156 kb
Host smart-5930fe7e-941b-4f7d-9f00-aeb15d8763eb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2264452878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2264452878
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1451683085
Short name T917
Test name
Test status
Simulation time 186755471 ps
CPU time 1.11 seconds
Started Mar 21 02:36:00 PM PDT 24
Finished Mar 21 02:36:01 PM PDT 24
Peak memory 197980 kb
Host smart-787976c9-e609-4123-ad4d-368ba7bb75f4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451683085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1451683085
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1561816826
Short name T875
Test name
Test status
Simulation time 64270896 ps
CPU time 0.73 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 192100 kb
Host smart-e0e85f3d-b9d9-419d-a0f1-3456ebeffaed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1561816826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1561816826
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3237096622
Short name T929
Test name
Test status
Simulation time 61922261 ps
CPU time 1.32 seconds
Started Mar 21 02:35:57 PM PDT 24
Finished Mar 21 02:35:59 PM PDT 24
Peak memory 192312 kb
Host smart-79e25b2c-0bdd-4a3e-b221-b1bd640df052
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237096622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3237096622
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3419842784
Short name T914
Test name
Test status
Simulation time 80884008 ps
CPU time 1.33 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:58 PM PDT 24
Peak memory 192284 kb
Host smart-72ea70bc-e56b-4a9a-834e-7a8f650bfed5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3419842784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3419842784
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3196861478
Short name T927
Test name
Test status
Simulation time 328731390 ps
CPU time 1.24 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:58 PM PDT 24
Peak memory 198080 kb
Host smart-d1654c22-f69c-4941-bb9c-14e86c5cdb50
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196861478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3196861478
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.849009045
Short name T850
Test name
Test status
Simulation time 76479964 ps
CPU time 1.26 seconds
Started Mar 21 02:35:59 PM PDT 24
Finished Mar 21 02:36:00 PM PDT 24
Peak memory 192372 kb
Host smart-15b66d7c-5381-4586-856d-4b43841460b5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=849009045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.849009045
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1255859240
Short name T910
Test name
Test status
Simulation time 56356613 ps
CPU time 1.01 seconds
Started Mar 21 02:36:06 PM PDT 24
Finished Mar 21 02:36:07 PM PDT 24
Peak memory 192272 kb
Host smart-157e387c-c83d-4480-8b9f-c5789db604f1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255859240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1255859240
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2924450838
Short name T890
Test name
Test status
Simulation time 61216065 ps
CPU time 1.21 seconds
Started Mar 21 02:35:57 PM PDT 24
Finished Mar 21 02:35:58 PM PDT 24
Peak memory 192336 kb
Host smart-ecca72b0-f21e-4ff2-9aaf-a80404690b70
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2924450838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2924450838
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.248226213
Short name T840
Test name
Test status
Simulation time 181314525 ps
CPU time 1.09 seconds
Started Mar 21 02:36:07 PM PDT 24
Finished Mar 21 02:36:09 PM PDT 24
Peak memory 192364 kb
Host smart-15939fe0-08cb-433f-9c26-0a45ae07799e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248226213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.248226213
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.856396715
Short name T884
Test name
Test status
Simulation time 120508383 ps
CPU time 0.85 seconds
Started Mar 21 02:35:57 PM PDT 24
Finished Mar 21 02:35:58 PM PDT 24
Peak memory 196800 kb
Host smart-4c29d736-6b62-452c-b99a-d2aeccc9c06d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=856396715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.856396715
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1487827950
Short name T887
Test name
Test status
Simulation time 231994327 ps
CPU time 1.36 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 197032 kb
Host smart-fa211e91-336a-4162-a40c-6f68efe8e850
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487827950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1487827950
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1140114542
Short name T902
Test name
Test status
Simulation time 225322210 ps
CPU time 1.16 seconds
Started Mar 21 02:35:44 PM PDT 24
Finished Mar 21 02:35:45 PM PDT 24
Peak memory 192336 kb
Host smart-72d4977e-e725-4bc7-9537-8553965073ed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1140114542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1140114542
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4274339363
Short name T895
Test name
Test status
Simulation time 67423162 ps
CPU time 1.4 seconds
Started Mar 21 02:35:49 PM PDT 24
Finished Mar 21 02:35:51 PM PDT 24
Peak memory 192360 kb
Host smart-e0d6945c-c293-4bd4-9403-1d04df09ac6f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274339363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4274339363
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1193072072
Short name T835
Test name
Test status
Simulation time 93796638 ps
CPU time 0.95 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 196784 kb
Host smart-2aec0030-cacf-453f-aae4-5c9c56ceeba3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1193072072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1193072072
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.465974016
Short name T915
Test name
Test status
Simulation time 226344911 ps
CPU time 1.56 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:58 PM PDT 24
Peak memory 198652 kb
Host smart-6fcf3ecd-b68f-4fc1-9258-df91c1ae670c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465974016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.465974016
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.14850769
Short name T865
Test name
Test status
Simulation time 53214861 ps
CPU time 1.1 seconds
Started Mar 21 02:35:59 PM PDT 24
Finished Mar 21 02:36:00 PM PDT 24
Peak memory 192156 kb
Host smart-2a1583aa-0228-44bc-b815-87bad3194fd0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=14850769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.14850769
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.948286814
Short name T911
Test name
Test status
Simulation time 165040961 ps
CPU time 1.36 seconds
Started Mar 21 02:35:56 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 192328 kb
Host smart-f4a5ce26-b628-4003-b444-2137cbb783f4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948286814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.948286814
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1064349595
Short name T836
Test name
Test status
Simulation time 165776949 ps
CPU time 0.95 seconds
Started Mar 21 02:35:58 PM PDT 24
Finished Mar 21 02:35:59 PM PDT 24
Peak memory 192156 kb
Host smart-1dabe65b-0742-49a9-9890-b57fedcf0056
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1064349595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1064349595
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.567403958
Short name T928
Test name
Test status
Simulation time 58289271 ps
CPU time 1.03 seconds
Started Mar 21 02:36:00 PM PDT 24
Finished Mar 21 02:36:01 PM PDT 24
Peak memory 192356 kb
Host smart-24f7be29-8cc8-4e34-acac-10ba0087544c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567403958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.567403958
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1554375317
Short name T843
Test name
Test status
Simulation time 58381769 ps
CPU time 1.31 seconds
Started Mar 21 02:35:59 PM PDT 24
Finished Mar 21 02:36:01 PM PDT 24
Peak memory 192320 kb
Host smart-9da20b61-bf98-4f55-bbe3-8e124d15101e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1554375317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1554375317
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4261845140
Short name T883
Test name
Test status
Simulation time 54969770 ps
CPU time 1.27 seconds
Started Mar 21 02:36:06 PM PDT 24
Finished Mar 21 02:36:09 PM PDT 24
Peak memory 198136 kb
Host smart-3b32b853-3cb5-4a56-9038-a1988a7b94d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261845140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4261845140
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3813121079
Short name T909
Test name
Test status
Simulation time 200120863 ps
CPU time 1.52 seconds
Started Mar 21 02:35:59 PM PDT 24
Finished Mar 21 02:36:01 PM PDT 24
Peak memory 198684 kb
Host smart-e62ca768-cbca-4bc5-a8c5-87d3fab30b0b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3813121079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3813121079
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3640439509
Short name T848
Test name
Test status
Simulation time 51275213 ps
CPU time 1.28 seconds
Started Mar 21 02:36:00 PM PDT 24
Finished Mar 21 02:36:01 PM PDT 24
Peak memory 198652 kb
Host smart-e40cda25-cb12-43c6-b357-8f57281eeeff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640439509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3640439509
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1102233381
Short name T920
Test name
Test status
Simulation time 27943155 ps
CPU time 1.01 seconds
Started Mar 21 02:36:00 PM PDT 24
Finished Mar 21 02:36:01 PM PDT 24
Peak memory 192116 kb
Host smart-35c64496-299e-4f1f-b7c3-5c587ae727fb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1102233381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1102233381
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1453887529
Short name T867
Test name
Test status
Simulation time 66649337 ps
CPU time 1.36 seconds
Started Mar 21 02:35:58 PM PDT 24
Finished Mar 21 02:35:59 PM PDT 24
Peak memory 192276 kb
Host smart-64e08aec-c404-480a-8b28-c96d6a15b760
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453887529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1453887529
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1272441338
Short name T872
Test name
Test status
Simulation time 53252156 ps
CPU time 1.23 seconds
Started Mar 21 02:36:01 PM PDT 24
Finished Mar 21 02:36:03 PM PDT 24
Peak memory 198676 kb
Host smart-13a3b9f4-82cc-429f-be02-a7603b1cb466
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1272441338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1272441338
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1878974128
Short name T892
Test name
Test status
Simulation time 157299107 ps
CPU time 0.83 seconds
Started Mar 21 02:35:57 PM PDT 24
Finished Mar 21 02:35:58 PM PDT 24
Peak memory 196688 kb
Host smart-c1ba1aaf-4a7b-41ce-b06a-925fb1e40eae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878974128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1878974128
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4294356219
Short name T837
Test name
Test status
Simulation time 34949822 ps
CPU time 1.13 seconds
Started Mar 21 02:35:55 PM PDT 24
Finished Mar 21 02:35:57 PM PDT 24
Peak memory 192344 kb
Host smart-05e2fd29-7313-4608-bac0-b0b41406aa92
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4294356219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.4294356219
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2946331347
Short name T900
Test name
Test status
Simulation time 94578762 ps
CPU time 0.82 seconds
Started Mar 21 02:36:04 PM PDT 24
Finished Mar 21 02:36:05 PM PDT 24
Peak memory 196672 kb
Host smart-47d34a17-b485-43b7-a038-f6d145a2dec5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946331347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2946331347
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1943595026
Short name T888
Test name
Test status
Simulation time 118600158 ps
CPU time 1.17 seconds
Started Mar 21 02:35:57 PM PDT 24
Finished Mar 21 02:35:58 PM PDT 24
Peak memory 192276 kb
Host smart-9633ae9a-a1ad-42ef-8a9c-91a2bf19dc10
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1943595026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1943595026
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2103352087
Short name T934
Test name
Test status
Simulation time 55968620 ps
CPU time 1.14 seconds
Started Mar 21 02:36:06 PM PDT 24
Finished Mar 21 02:36:09 PM PDT 24
Peak memory 192128 kb
Host smart-412908ed-b639-46fd-ba42-bc767dd3c3d1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103352087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2103352087
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2034553267
Short name T922
Test name
Test status
Simulation time 44951866 ps
CPU time 0.91 seconds
Started Mar 21 02:36:13 PM PDT 24
Finished Mar 21 02:36:14 PM PDT 24
Peak memory 192112 kb
Host smart-b1f2e0ef-4b4e-417a-b596-9222acbd3288
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2034553267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2034553267
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3966699929
Short name T932
Test name
Test status
Simulation time 45106403 ps
CPU time 0.84 seconds
Started Mar 21 02:36:10 PM PDT 24
Finished Mar 21 02:36:11 PM PDT 24
Peak memory 192200 kb
Host smart-0e0da951-8338-4f0c-9862-c452b822660b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966699929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3966699929
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1502295788
Short name T930
Test name
Test status
Simulation time 177289285 ps
CPU time 1.02 seconds
Started Mar 21 02:35:41 PM PDT 24
Finished Mar 21 02:35:42 PM PDT 24
Peak memory 192344 kb
Host smart-dd07520a-bc4b-4114-b2b1-170e672207f3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1502295788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1502295788
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2850068580
Short name T886
Test name
Test status
Simulation time 68470868 ps
CPU time 1.11 seconds
Started Mar 21 02:35:44 PM PDT 24
Finished Mar 21 02:35:45 PM PDT 24
Peak memory 198624 kb
Host smart-404c123e-57ca-48e8-a1e3-50c84b1e658f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850068580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2850068580
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.4062061426
Short name T889
Test name
Test status
Simulation time 37938207 ps
CPU time 0.89 seconds
Started Mar 21 02:35:43 PM PDT 24
Finished Mar 21 02:35:43 PM PDT 24
Peak memory 192108 kb
Host smart-03655740-77c8-4433-9b4e-5d19398a5315
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4062061426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.4062061426
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.492940781
Short name T907
Test name
Test status
Simulation time 74779942 ps
CPU time 1.26 seconds
Started Mar 21 02:35:43 PM PDT 24
Finished Mar 21 02:35:44 PM PDT 24
Peak memory 191732 kb
Host smart-bbdfd129-567b-4d60-851f-39f764c20b97
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492940781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.492940781
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.513793313
Short name T881
Test name
Test status
Simulation time 457052223 ps
CPU time 1.59 seconds
Started Mar 21 02:35:44 PM PDT 24
Finished Mar 21 02:35:46 PM PDT 24
Peak memory 192348 kb
Host smart-dfde379b-44f1-4383-bf59-5c24e49e01a2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=513793313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.513793313
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1186966168
Short name T869
Test name
Test status
Simulation time 40175785 ps
CPU time 1.18 seconds
Started Mar 21 02:35:41 PM PDT 24
Finished Mar 21 02:35:42 PM PDT 24
Peak memory 192316 kb
Host smart-b8dcb364-79bd-42cf-93e0-ac7854903fc9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186966168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1186966168
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3162288053
Short name T921
Test name
Test status
Simulation time 129852745 ps
CPU time 1.32 seconds
Started Mar 21 02:35:45 PM PDT 24
Finished Mar 21 02:35:46 PM PDT 24
Peak memory 192336 kb
Host smart-40d2ae62-943c-4543-b588-b58bce69d66e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3162288053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3162288053
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3248237817
Short name T856
Test name
Test status
Simulation time 51363870 ps
CPU time 1.15 seconds
Started Mar 21 02:35:41 PM PDT 24
Finished Mar 21 02:35:42 PM PDT 24
Peak memory 198676 kb
Host smart-fee7cb1d-293f-4278-a9ff-71a91d5dd682
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248237817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3248237817
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1491593819
Short name T868
Test name
Test status
Simulation time 532219718 ps
CPU time 1.09 seconds
Started Mar 21 02:35:43 PM PDT 24
Finished Mar 21 02:35:44 PM PDT 24
Peak memory 192272 kb
Host smart-a686c61c-ae00-4516-aa49-9abd05ecd404
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1491593819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1491593819
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2058211301
Short name T860
Test name
Test status
Simulation time 128824457 ps
CPU time 0.87 seconds
Started Mar 21 02:35:42 PM PDT 24
Finished Mar 21 02:35:43 PM PDT 24
Peak memory 192164 kb
Host smart-e5e07b1a-6887-491d-bf82-afd5640017dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058211301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2058211301
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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