Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5082093	1			T20	70		T22	1		T23	141382
all_pins[1]	5082093	1			T20	70		T22	1		T23	141382
all_pins[2]	5082093	1			T20	70		T22	1		T23	141382
all_pins[3]	5082093	1			T20	70		T22	1		T23	141382
all_pins[4]	5082093	1			T20	70		T22	1		T23	141382
all_pins[5]	5082093	1			T20	70		T22	1		T23	141382
all_pins[6]	5082093	1			T20	70		T22	1		T23	141382
all_pins[7]	5082093	1			T20	70		T22	1		T23	141382
all_pins[8]	5082093	1			T20	70		T22	1		T23	141382
all_pins[9]	5082093	1			T20	70		T22	1		T23	141382
all_pins[10]	5082093	1			T20	70		T22	1		T23	141382
all_pins[11]	5082093	1			T20	70		T22	1		T23	141382
all_pins[12]	5082093	1			T20	70		T22	1		T23	141382
all_pins[13]	5082093	1			T20	70		T22	1		T23	141382
all_pins[14]	5082093	1			T20	70		T22	1		T23	141382
all_pins[15]	5082093	1			T20	70		T22	1		T23	141382
all_pins[16]	5082093	1			T20	70		T22	1		T23	141382
all_pins[17]	5082093	1			T20	70		T22	1		T23	141382
all_pins[18]	5082093	1			T20	70		T22	1		T23	141382
all_pins[19]	5082093	1			T20	70		T22	1		T23	141382
all_pins[20]	5082093	1			T20	70		T22	1		T23	141382
all_pins[21]	5082093	1			T20	70		T22	1		T23	141382
all_pins[22]	5082093	1			T20	70		T22	1		T23	141382
all_pins[23]	5082093	1			T20	70		T22	1		T23	141382
all_pins[24]	5082093	1			T20	70		T22	1		T23	141382
all_pins[25]	5082093	1			T20	70		T22	1		T23	141382
all_pins[26]	5082093	1			T20	70		T22	1		T23	141382
all_pins[27]	5082093	1			T20	70		T22	1		T23	141382
all_pins[28]	5082093	1			T20	70		T22	1		T23	141382
all_pins[29]	5082093	1			T20	70		T22	1		T23	141382
all_pins[30]	5082093	1			T20	70		T22	1		T23	141382
all_pins[31]	5082093	1			T20	70		T22	1		T23	141382

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	100975954	1			T20	1672		T22	32		T23	280813
values[0x1]	61651022	1			T20	568		T23	171608		T25	2212
transitions[0x0=>0x1]	36930085	1			T20	375		T23	102686		T25	1368
transitions[0x1=>0x0]	36929931	1			T20	374		T23	102686		T25	1367

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3158075	1			T20	52		T22	1		T23	88438
all_pins[0]	values[0x1]	1924018	1			T20	18		T23	52944		T25	75
all_pins[0]	transitions[0x0=>0x1]	1192721	1			T20	9		T23	33056		T25	32
all_pins[0]	transitions[0x1=>0x0]	1188563	1			T20	8		T23	33033		T25	44
all_pins[1]	values[0x0]	3150969	1			T20	61		T22	1		T23	86665
all_pins[1]	values[0x1]	1931124	1			T20	9		T23	54717		T25	65
all_pins[1]	transitions[0x0=>0x1]	1159548	1			T20	4		T23	33080		T25	42
all_pins[1]	transitions[0x1=>0x0]	1152442	1			T20	13		T23	31307		T25	52
all_pins[2]	values[0x0]	3157717	1			T20	55		T22	1		T23	87988
all_pins[2]	values[0x1]	1924376	1			T20	15		T23	53394		T25	44
all_pins[2]	transitions[0x0=>0x1]	1148894	1			T20	14		T23	31243		T25	28
all_pins[2]	transitions[0x1=>0x0]	1155642	1			T20	8		T23	32566		T25	49
all_pins[3]	values[0x0]	3157868	1			T20	54		T22	1		T23	88344
all_pins[3]	values[0x1]	1924225	1			T20	16		T23	53038		T25	66
all_pins[3]	transitions[0x0=>0x1]	1153802	1			T20	11		T23	31414		T25	47
all_pins[3]	transitions[0x1=>0x0]	1153953	1			T20	10		T23	31770		T25	25
all_pins[4]	values[0x0]	3159775	1			T20	56		T22	1		T23	88415
all_pins[4]	values[0x1]	1922318	1			T20	14		T23	52967		T25	64
all_pins[4]	transitions[0x0=>0x1]	1151086	1			T20	12		T23	32329		T25	35
all_pins[4]	transitions[0x1=>0x0]	1152993	1			T20	14		T23	32400		T25	37
all_pins[5]	values[0x0]	3154995	1			T20	48		T22	1		T23	87979
all_pins[5]	values[0x1]	1927098	1			T20	22		T23	53403		T25	85
all_pins[5]	transitions[0x0=>0x1]	1152562	1			T20	17		T23	32015		T25	69
all_pins[5]	transitions[0x1=>0x0]	1147782	1			T20	9		T23	31579		T25	48
all_pins[6]	values[0x0]	3155647	1			T20	53		T22	1		T23	87141
all_pins[6]	values[0x1]	1926446	1			T20	17		T23	54241		T25	58
all_pins[6]	transitions[0x0=>0x1]	1150796	1			T20	10		T23	32145		T25	30
all_pins[6]	transitions[0x1=>0x0]	1151448	1			T20	15		T23	31307		T25	57
all_pins[7]	values[0x0]	3151834	1			T20	50		T22	1		T23	88044
all_pins[7]	values[0x1]	1930259	1			T20	20		T23	53338		T25	53
all_pins[7]	transitions[0x0=>0x1]	1156622	1			T20	20		T23	31291		T25	46
all_pins[7]	transitions[0x1=>0x0]	1152809	1			T20	17		T23	32194		T25	51
all_pins[8]	values[0x0]	3158011	1			T20	48		T22	1		T23	87434
all_pins[8]	values[0x1]	1924082	1			T20	22		T23	53948		T25	56
all_pins[8]	transitions[0x0=>0x1]	1149794	1			T20	17		T23	32147		T25	36
all_pins[8]	transitions[0x1=>0x0]	1155971	1			T20	15		T23	31537		T25	33
all_pins[9]	values[0x0]	3161237	1			T20	39		T22	1		T23	87558
all_pins[9]	values[0x1]	1920856	1			T20	31		T23	53824		T25	77
all_pins[9]	transitions[0x0=>0x1]	1151815	1			T20	17		T23	32426		T25	52
all_pins[9]	transitions[0x1=>0x0]	1155041	1			T20	8		T23	32550		T25	31
all_pins[10]	values[0x0]	3153427	1			T20	59		T22	1		T23	87867
all_pins[10]	values[0x1]	1928666	1			T20	11		T23	53515		T25	98
all_pins[10]	transitions[0x0=>0x1]	1156714	1			T23	31674		T25	62		T27	14
all_pins[10]	transitions[0x1=>0x0]	1148904	1			T20	20		T23	31983		T25	41
all_pins[11]	values[0x0]	3153663	1			T20	41		T22	1		T23	86888
all_pins[11]	values[0x1]	1928430	1			T20	29		T23	54494		T25	83
all_pins[11]	transitions[0x0=>0x1]	1154318	1			T20	20		T23	32572		T25	37
all_pins[11]	transitions[0x1=>0x0]	1154554	1			T20	2		T23	31593		T25	52
all_pins[12]	values[0x0]	3157886	1			T20	45		T22	1		T23	88916
all_pins[12]	values[0x1]	1924207	1			T20	25		T23	52466		T25	78
all_pins[12]	transitions[0x0=>0x1]	1150406	1			T20	8		T23	30864		T25	40
all_pins[12]	transitions[0x1=>0x0]	1154629	1			T20	12		T23	32892		T25	45
all_pins[13]	values[0x0]	3144140	1			T20	60		T22	1		T23	86600
all_pins[13]	values[0x1]	1937953	1			T20	10		T23	54782		T25	74
all_pins[13]	transitions[0x0=>0x1]	1160541	1			T20	10		T23	33579		T25	32
all_pins[13]	transitions[0x1=>0x0]	1146795	1			T20	25		T23	31263		T25	36
all_pins[14]	values[0x0]	3154617	1			T20	58		T22	1		T23	87103
all_pins[14]	values[0x1]	1927476	1			T20	12		T23	54279		T25	41
all_pins[14]	transitions[0x0=>0x1]	1149464	1			T20	8		T23	32118		T25	11
all_pins[14]	transitions[0x1=>0x0]	1159941	1			T20	6		T23	32621		T25	44
all_pins[15]	values[0x0]	3152343	1			T20	36		T22	1		T23	87108
all_pins[15]	values[0x1]	1929750	1			T20	34		T23	54274		T25	100
all_pins[15]	transitions[0x0=>0x1]	1153123	1			T20	24		T23	32264		T25	86
all_pins[15]	transitions[0x1=>0x0]	1150849	1			T20	2		T23	32269		T25	27
all_pins[16]	values[0x0]	3155237	1			T20	33		T22	1		T23	87796
all_pins[16]	values[0x1]	1926856	1			T20	37		T23	53586		T25	83
all_pins[16]	transitions[0x0=>0x1]	1149839	1			T20	9		T23	31998		T25	41
all_pins[16]	transitions[0x1=>0x0]	1152733	1			T20	6		T23	32686		T25	58
all_pins[17]	values[0x0]	3156048	1			T20	53		T22	1		T23	87499
all_pins[17]	values[0x1]	1926045	1			T20	17		T23	53883		T25	91
all_pins[17]	transitions[0x0=>0x1]	1152258	1			T20	9		T23	31899		T25	48
all_pins[17]	transitions[0x1=>0x0]	1153069	1			T20	29		T23	31602		T25	40
all_pins[18]	values[0x0]	3152445	1			T20	57		T22	1		T23	87394
all_pins[18]	values[0x1]	1929648	1			T20	13		T23	53988		T25	64
all_pins[18]	transitions[0x0=>0x1]	1158320	1			T20	11		T23	32466		T25	26
all_pins[18]	transitions[0x1=>0x0]	1154717	1			T20	15		T23	32361		T25	53
all_pins[19]	values[0x0]	3159299	1			T20	39		T22	1		T23	89627
all_pins[19]	values[0x1]	1922794	1			T20	31		T23	51755		T25	87
all_pins[19]	transitions[0x0=>0x1]	1149924	1			T20	24		T23	30870		T25	58
all_pins[19]	transitions[0x1=>0x0]	1156778	1			T20	6		T23	33103		T25	35
all_pins[20]	values[0x0]	3157464	1			T20	53		T22	1		T23	87378
all_pins[20]	values[0x1]	1924629	1			T20	17		T23	54004		T25	71
all_pins[20]	transitions[0x0=>0x1]	1153543	1			T20	9		T23	33098		T25	38
all_pins[20]	transitions[0x1=>0x0]	1151708	1			T20	23		T23	30849		T25	54
all_pins[21]	values[0x0]	3158343	1			T20	49		T22	1		T23	88063
all_pins[21]	values[0x1]	1923750	1			T20	21		T23	53319		T25	56
all_pins[21]	transitions[0x0=>0x1]	1148929	1			T20	10		T23	31779		T25	34
all_pins[21]	transitions[0x1=>0x0]	1149808	1			T20	6		T23	32464		T25	49
all_pins[22]	values[0x0]	3156631	1			T20	52		T22	1		T23	87667
all_pins[22]	values[0x1]	1925462	1			T20	18		T23	53715		T25	53
all_pins[22]	transitions[0x0=>0x1]	1152765	1			T20	13		T23	31902		T25	29
all_pins[22]	transitions[0x1=>0x0]	1151053	1			T20	16		T23	31506		T25	32
all_pins[23]	values[0x0]	3161371	1			T20	67		T22	1		T23	87090
all_pins[23]	values[0x1]	1920722	1			T20	3		T23	54292		T25	62
all_pins[23]	transitions[0x0=>0x1]	1148497	1			T20	1		T23	32638		T25	38
all_pins[23]	transitions[0x1=>0x0]	1153237	1			T20	16		T23	32061		T25	29
all_pins[24]	values[0x0]	3155681	1			T20	66		T22	1		T23	88985
all_pins[24]	values[0x1]	1926412	1			T20	4		T23	52397		T25	39
all_pins[24]	transitions[0x0=>0x1]	1156331	1			T20	4		T23	31214		T25	23
all_pins[24]	transitions[0x1=>0x0]	1150641	1			T20	3		T23	33109		T25	46
all_pins[25]	values[0x0]	3150035	1			T20	52		T22	1		T23	88580
all_pins[25]	values[0x1]	1932058	1			T20	18		T23	52802		T25	60
all_pins[25]	transitions[0x0=>0x1]	1155264	1			T20	18		T23	31972		T25	48
all_pins[25]	transitions[0x1=>0x0]	1149618	1			T20	4		T23	31567		T25	27
all_pins[26]	values[0x0]	3149899	1			T20	53		T22	1		T23	86558
all_pins[26]	values[0x1]	1932194	1			T20	17		T23	54824		T25	83
all_pins[26]	transitions[0x0=>0x1]	1154648	1			T20	9		T23	33330		T25	61
all_pins[26]	transitions[0x1=>0x0]	1154512	1			T20	10		T23	31308		T25	38
all_pins[27]	values[0x0]	3160213	1			T20	58		T22	1		T23	87566
all_pins[27]	values[0x1]	1921880	1			T20	12		T23	53816		T25	56
all_pins[27]	transitions[0x0=>0x1]	1146787	1			T20	11		T23	31364		T25	35
all_pins[27]	transitions[0x1=>0x0]	1157101	1			T20	16		T23	32372		T25	62
all_pins[28]	values[0x0]	3155862	1			T20	58		T22	1		T23	88545
all_pins[28]	values[0x1]	1926231	1			T20	12		T23	52837		T25	62
all_pins[28]	transitions[0x0=>0x1]	1155429	1			T20	12		T23	32194		T25	47
all_pins[28]	transitions[0x1=>0x0]	1151078	1			T20	12		T23	33173		T25	41
all_pins[29]	values[0x0]	3149091	1			T20	53		T22	1		T23	86946
all_pins[29]	values[0x1]	1933002	1			T20	17		T23	54436		T25	105
all_pins[29]	transitions[0x0=>0x1]	1156715	1			T20	15		T23	32791		T25	67
all_pins[29]	transitions[0x1=>0x0]	1149944	1			T20	10		T23	31192		T25	24
all_pins[30]	values[0x0]	3154052	1			T20	62		T22	1		T23	87496
all_pins[30]	values[0x1]	1928041	1			T20	8		T23	53886		T25	35
all_pins[30]	transitions[0x0=>0x1]	1153914	1			T20	4		T23	31838		T25	14
all_pins[30]	transitions[0x1=>0x0]	1158875	1			T20	13		T23	32388		T25	84
all_pins[31]	values[0x0]	3162079	1			T20	52		T22	1		T23	88461
all_pins[31]	values[0x1]	1920014	1			T20	18		T23	52921		T25	88
all_pins[31]	transitions[0x0=>0x1]	1144716	1			T20	15		T23	31297		T25	76
all_pins[31]	transitions[0x1=>0x0]	1152743	1			T20	5		T23	32262		T25	23