Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[1]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[2]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[3]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[4]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[5]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[6]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[7]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[8]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[9]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[10]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[11]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[12]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[13]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[14]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[15]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[16]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[17]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[18]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[19]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[20]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[21]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[22]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[23]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[24]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[25]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[26]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[27]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[28]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[29]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[30]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[31]	16332491	1			T20	122		T22	408		T23	370246

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

317095513

1

T20

2038

T22

10133

T23

763890

auto[1]

205544199

1

T20

1866

T22

2923

T23

420896

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

417238312

1

T20

3618

T22

9689

T23

936948

auto[1]

105401400

1

T20

286

T22

3367

T23

247838

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

386317395

1

T20

3028

T22

6163

T23

868740

auto[1]

136322317

1

T20

876

T22

6893

T23

316046

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	6071792	1			T20	60		T22	138		T23	143847
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4333348	1			T20	34		T22	26		T23	89000
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1659110	1			T20	5		T22	82		T23	38584
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2165060	1			T20	11		T22	97		T23	55865
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	456107	1			T20	12		T22	19		T23	3756
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1647074	1			T22	46		T23	39194		T24	78
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	6081630	1			T20	45		T22	151		T23	142898
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4333914	1			T20	42		T22	19		T23	88929
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1648827	1			T20	1		T22	57		T23	39626
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2167908	1			T22	108		T23	56174		T24	181
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	455544	1			T20	14		T22	18		T23	3908
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1644668	1			T20	20		T22	55		T23	38711
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	6085049	1			T20	50		T22	129		T23	143641
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4333766	1			T20	55		T22	15		T23	89229
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1649500	1			T22	80		T23	38589		T24	109
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2163465	1			T20	7		T22	128		T23	56535
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	455336	1			T20	10		T22	28		T23	3865
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1645375	1			T22	28		T23	38387		T24	88
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	6094754	1			T20	38		T22	100		T23	143870
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4325688	1			T20	70		T22	14		T23	89539
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1654251	1			T22	90		T23	39070		T24	70
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2155894	1			T22	126		T23	55641		T24	224
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	455117	1			T20	11		T22	31		T23	3655
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1646787	1			T20	3		T22	47		T23	38471
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	6089092	1			T20	31		T22	129		T23	142413
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4328332	1			T20	54		T22	10		T23	89081
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1659335	1			T22	22		T23	39368		T24	87
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2159641	1			T20	12		T22	159		T23	56682
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	455605	1			T20	11		T22	26		T23	3990
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1640486	1			T20	14		T22	62		T23	38712
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	6096228	1			T20	46		T22	87		T23	142406
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4324680	1			T20	43		T22	17		T23	88956
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1654702	1			T20	1		T22	42		T23	39485
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2158349	1			T20	9		T22	151		T23	56287
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	455769	1			T20	9		T22	31		T23	3957
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1642763	1			T20	14		T22	80		T23	39155
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	6099415	1			T20	65		T22	136		T23	142868
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4314939	1			T20	18		T22	12		T23	89425
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1657748	1			T20	2		T22	31		T23	39035
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2164087	1			T20	35		T22	160		T23	56451
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	455587	1			T20	1		T22	26		T23	3736
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1640715	1			T20	1		T22	43		T23	38731
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	6089783	1			T20	53		T22	141		T23	143802
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4326761	1			T20	32		T22	10		T23	88906
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1662192	1			T22	49		T23	39470		T24	108
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2156731	1			T20	26		T22	129		T23	56025
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	454077	1			T20	11		T22	20		T23	3669
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1642947	1			T22	59		T23	38374		T24	95
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	6084598	1			T20	42		T22	196		T23	142516
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4327906	1			T20	37		T22	24		T23	88640
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1656740	1			T22	50		T23	38725		T24	86
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2164120	1			T20	30		T22	105		T23	57224
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	457134	1			T20	4		T22	12		T23	3961
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1641993	1			T20	9		T22	21		T23	39180
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	6091188	1			T20	23		T22	128		T23	142954
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4328510	1			T20	56		T22	14		T23	89111
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1656522	1			T22	53		T23	38030		T24	51
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2163197	1			T20	10		T22	154		T23	57495
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	451776	1			T20	17		T22	23		T23	3924
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1641298	1			T20	16		T22	36		T23	38732
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	6089408	1			T20	27		T22	115		T23	144744
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4323716	1			T20	51		T22	34		T23	88994
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1653481	1			T22	48		T23	38644		T24	107
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2165760	1			T20	6		T22	154		T23	55998
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	457509	1			T20	20		T22	9		T23	3711
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1642617	1			T20	18		T22	48		T23	38155
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	6083256	1			T20	56		T22	76		T23	143305
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4329064	1			T20	41		T22	10		T23	89140
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1656401	1			T20	6		T22	65		T23	38935
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2164368	1			T20	19		T22	142		T23	56368
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	452295	1			T22	25		T23	3777		T24	20
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1647107	1			T22	90		T23	38721		T24	55
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	6086786	1			T20	34		T22	128		T23	143582
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4327162	1			T20	69		T22	15		T23	89483
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1657734	1			T22	56		T23	38691		T24	110
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2160825	1			T20	8		T22	130		T23	56425
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	454446	1			T20	6		T22	18		T23	3618
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1645538	1			T20	5		T22	61		T23	38447
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	6096854	1			T20	36		T22	104		T23	143055
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4321841	1			T20	63		T22	25		T23	89177
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1657997	1			T22	57		T23	38431		T24	102
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2159243	1			T20	7		T22	151		T23	56368
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	454128	1			T20	11		T22	23		T23	3787
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1642428	1			T20	5		T22	48		T23	39428
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	6085065	1			T20	44		T22	145		T23	143191
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4333220	1			T20	71		T22	20		T23	88848
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1655592	1			T20	1		T22	68		T23	38799
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2161416	1			T22	108		T23	56433		T24	179
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	454825	1			T20	3		T22	19		T23	3673
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1642373	1			T20	3		T22	48		T23	39302
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	6085804	1			T20	55		T22	134		T23	143543
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4330530	1			T20	38		T22	18		T23	88929
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1652026	1			T20	7		T22	30		T23	39047
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2167428	1			T20	18		T22	159		T23	56085
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	453767	1			T20	4		T22	22		T23	3828
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1642936	1			T22	45		T23	38814		T24	90
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	6089157	1			T20	70		T22	114		T23	144239
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4335645	1			T20	33		T22	9		T23	89637
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1644631	1			T20	7		T22	14		T23	39325
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2168697	1			T20	12		T22	171		T23	55337
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	455406	1			T22	35		T23	3576		T24	24
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1638955	1			T22	65		T23	38132		T24	86
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	6092650	1			T20	46		T22	109		T23	143016
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4330588	1			T20	33		T22	18		T23	89214
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1652383	1			T22	52		T23	39576		T24	71
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2165713	1			T20	3		T22	158		T23	56193
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	454930	1			T20	18		T22	22		T23	3645
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1636227	1			T20	22		T22	49		T23	38602
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	6094198	1			T20	43		T22	99		T23	143386
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4327086	1			T20	59		T22	11		T23	89121
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1645664	1			T20	1		T22	42		T23	39089
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2171937	1			T20	2		T22	176		T23	56748
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	454443	1			T20	11		T22	22		T23	3793
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1639163	1			T20	6		T22	58		T23	38109
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	6095702	1			T20	24		T22	106		T23	142775
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4330119	1			T20	55		T22	15		T23	89095
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1654683	1			T20	13		T22	84		T23	38155
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2167067	1			T20	23		T22	127		T23	58396
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	453739	1			T20	6		T22	25		T23	3939
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1631181	1			T20	1		T22	51		T23	37886
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	6090483	1			T20	48		T22	88		T23	144198
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4331974	1			T20	52		T22	12		T23	89185
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1649462	1			T20	2		T22	55		T23	38189
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2166206	1			T20	9		T22	158		T23	56520
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	456469	1			T20	2		T22	30		T23	3706
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1637897	1			T20	9		T22	65		T23	38448
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	6093829	1			T20	40		T22	117		T23	145188
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4325252	1			T20	45		T22	16		T23	89067
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1648851	1			T22	39		T23	39129		T24	95
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2171831	1			T20	2		T22	135		T23	55101
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	454693	1			T20	16		T22	21		T23	3767
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1638035	1			T20	19		T22	80		T23	37994
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	6084840	1			T20	54		T22	111		T23	143823
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4332500	1			T20	32		T22	9		T23	89261
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1653044	1			T20	4		T22	72		T23	38642
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2172452	1			T20	13		T22	148		T23	56771
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	452952	1			T20	11		T22	35		T23	3870
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1636703	1			T20	8		T22	33		T23	37879
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	6096673	1			T20	53		T22	129		T23	142346
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4326498	1			T20	31		T22	16		T23	89586
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1653435	1			T20	6		T22	72		T23	38488
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2165448	1			T20	22		T22	124		T23	57390
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	452701	1			T20	8		T22	8		T23	3957
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1637736	1			T20	2		T22	59		T23	38479
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	6084186	1			T20	30		T22	118		T23	143360
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4331352	1			T20	60		T22	17		T23	89194
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1655622	1			T20	8		T22	51		T23	39185
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2169134	1			T20	14		T22	136		T23	56965
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	454963	1			T20	6		T22	27		T23	3757
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1637234	1			T20	4		T22	59		T23	37785
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	6101456	1			T20	59		T22	126		T23	143586
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4321583	1			T20	35		T22	21		T23	89357
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1650920	1			T20	1		T22	40		T23	38588
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2167220	1			T20	24		T22	154		T23	56286
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	453748	1			T20	2		T22	22		T23	3679
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1637564	1			T20	1		T22	45		T23	38750
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	6113339	1			T20	80		T22	149		T23	142790
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4321551	1			T20	19		T22	12		T23	89310
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1650461	1			T20	3		T22	81		T23	38922
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2159444	1			T20	16		T22	93		T23	56914
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	453534	1			T20	3		T22	31		T23	3799
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1634162	1			T20	1		T22	42		T23	38511
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	6100444	1			T20	63		T22	159		T23	143539
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4323567	1			T20	20		T22	25		T23	89165
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1654548	1			T22	27		T23	38736		T24	87
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2161416	1			T20	18		T22	161		T23	56335
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	454985	1			T20	12		T22	12		T23	3864
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1637531	1			T20	9		T22	24		T23	38607
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	6085104	1			T20	66		T22	153		T23	143582
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4333318	1			T20	30		T22	15		T23	89433
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1645915	1			T20	2		T22	37		T23	39002
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2173997	1			T20	23		T22	141		T23	56097
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	456513	1			T20	1		T22	26		T23	3734
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1637644	1			T22	36		T23	38398		T24	142
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	6085140	1			T20	53		T22	108		T23	143411
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4329440	1			T20	49		T22	11		T23	89391
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1651895	1			T20	2		T22	69		T23	38944
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2167318	1			T20	7		T22	136		T23	56274
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	457490	1			T20	2		T22	21		T23	3752
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1641208	1			T20	9		T22	63		T23	38474
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	6091705	1			T20	58		T22	92		T23	142992
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4326649	1			T20	35		T22	13		T23	89285
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1650307	1			T22	66		T23	38944		T24	79
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2172359	1			T20	11		T22	144		T23	56122
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	455980	1			T20	9		T22	24		T23	3787
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1635491	1			T20	9		T22	69		T23	39116
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	6091738	1			T20	57		T22	131		T23	143506
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4332478	1			T20	40		T22	19		T23	89632
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1659093	1			T20	5		T22	14		T23	39273
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2163364	1			T20	15		T22	169		T23	56311
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	451326	1			T20	4		T22	18		T23	3538
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1634492	1			T20	1		T22	57		T23	37986

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal