Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[1]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[2]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[3]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[4]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[5]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[6]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[7]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[8]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[9]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[10]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[11]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[12]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[13]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[14]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[15]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[16]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[17]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[18]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[19]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[20]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[21]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[22]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[23]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[24]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[25]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[26]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[27]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[28]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[29]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[30]	16332491	1			T20	122		T22	408		T23	370246
bins_for_gpio_bits[31]	16332491	1			T20	122		T22	408		T23	370246

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

317095513

1

T20

2038

T22

10133

T23

763890

auto[1]

205544199

1

T20

1866

T22

2923

T23

420896

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

317087595

1

T20

2039

T22

10124

T23

763889

auto[1]

205552117

1

T20

1865

T22

2932

T23

420897

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	9601885	1			T20	76		T22	309		T23	231595
bins_for_gpio_bits[0]	auto[0]	auto[1]	293798	1			T22	8		T23	6701		T24	16
bins_for_gpio_bits[0]	auto[1]	auto[0]	294077	1			T22	8		T23	6701		T24	16
bins_for_gpio_bits[0]	auto[1]	auto[1]	6142731	1			T20	46		T22	83		T23	125249
bins_for_gpio_bits[1]	auto[0]	auto[0]	9604445	1			T20	46		T22	309		T23	231953
bins_for_gpio_bits[1]	auto[0]	auto[1]	293644	1			T22	6		T23	6745		T24	12
bins_for_gpio_bits[1]	auto[1]	auto[0]	293920	1			T22	7		T23	6745		T24	13
bins_for_gpio_bits[1]	auto[1]	auto[1]	6140482	1			T20	76		T22	86		T23	124803
bins_for_gpio_bits[2]	auto[0]	auto[0]	9603906	1			T20	57		T22	331		T23	232016
bins_for_gpio_bits[2]	auto[0]	auto[1]	293879	1			T22	6		T23	6749		T24	13
bins_for_gpio_bits[2]	auto[1]	auto[0]	294108	1			T22	6		T23	6749		T24	13
bins_for_gpio_bits[2]	auto[1]	auto[1]	6140598	1			T20	65		T22	65		T23	124732
bins_for_gpio_bits[3]	auto[0]	auto[0]	9610815	1			T20	38		T22	305		T23	231881
bins_for_gpio_bits[3]	auto[0]	auto[1]	293865	1			T22	11		T23	6700		T24	11
bins_for_gpio_bits[3]	auto[1]	auto[0]	294084	1			T22	11		T23	6700		T24	11
bins_for_gpio_bits[3]	auto[1]	auto[1]	6133727	1			T20	84		T22	81		T23	124965
bins_for_gpio_bits[4]	auto[0]	auto[0]	9614579	1			T20	43		T22	300		T23	231770
bins_for_gpio_bits[4]	auto[0]	auto[1]	293271	1			T22	10		T23	6693		T24	12
bins_for_gpio_bits[4]	auto[1]	auto[0]	293489	1			T22	10		T23	6693		T24	12
bins_for_gpio_bits[4]	auto[1]	auto[1]	6131152	1			T20	79		T22	88		T23	125090
bins_for_gpio_bits[5]	auto[0]	auto[0]	9615371	1			T20	56		T22	270		T23	231391
bins_for_gpio_bits[5]	auto[0]	auto[1]	293671	1			T22	10		T23	6786		T24	17
bins_for_gpio_bits[5]	auto[1]	auto[0]	293908	1			T22	10		T23	6787		T24	17
bins_for_gpio_bits[5]	auto[1]	auto[1]	6129541	1			T20	66		T22	118		T23	125282
bins_for_gpio_bits[6]	auto[0]	auto[0]	9627207	1			T20	102		T22	320		T23	231580
bins_for_gpio_bits[6]	auto[0]	auto[1]	293814	1			T22	7		T23	6774		T24	17
bins_for_gpio_bits[6]	auto[1]	auto[0]	294043	1			T22	7		T23	6774		T24	18
bins_for_gpio_bits[6]	auto[1]	auto[1]	6117427	1			T20	20		T22	74		T23	125118
bins_for_gpio_bits[7]	auto[0]	auto[0]	9614497	1			T20	79		T22	310		T23	232550
bins_for_gpio_bits[7]	auto[0]	auto[1]	293912	1			T22	9		T23	6747		T24	17
bins_for_gpio_bits[7]	auto[1]	auto[0]	294209	1			T22	9		T23	6747		T24	17
bins_for_gpio_bits[7]	auto[1]	auto[1]	6129873	1			T20	43		T22	80		T23	124202
bins_for_gpio_bits[8]	auto[0]	auto[0]	9611258	1			T20	72		T22	345		T23	231671
bins_for_gpio_bits[8]	auto[0]	auto[1]	293948	1			T22	6		T23	6794		T24	16
bins_for_gpio_bits[8]	auto[1]	auto[0]	294200	1			T22	6		T23	6794		T24	16
bins_for_gpio_bits[8]	auto[1]	auto[1]	6133085	1			T20	50		T22	51		T23	124987
bins_for_gpio_bits[9]	auto[0]	auto[0]	9616856	1			T20	33		T22	330		T23	231637
bins_for_gpio_bits[9]	auto[0]	auto[1]	293820	1			T22	4		T23	6841		T24	14
bins_for_gpio_bits[9]	auto[1]	auto[0]	294051	1			T22	5		T23	6842		T24	14
bins_for_gpio_bits[9]	auto[1]	auto[1]	6127764	1			T20	89		T22	69		T23	124926
bins_for_gpio_bits[10]	auto[0]	auto[0]	9614214	1			T20	33		T22	308		T23	232648
bins_for_gpio_bits[10]	auto[0]	auto[1]	294192	1			T22	9		T23	6738		T24	11
bins_for_gpio_bits[10]	auto[1]	auto[0]	294435	1			T22	9		T23	6738		T24	11
bins_for_gpio_bits[10]	auto[1]	auto[1]	6129650	1			T20	89		T22	82		T23	124122
bins_for_gpio_bits[11]	auto[0]	auto[0]	9609045	1			T20	81		T22	268		T23	231802
bins_for_gpio_bits[11]	auto[0]	auto[1]	294701	1			T22	14		T23	6806		T24	10
bins_for_gpio_bits[11]	auto[1]	auto[0]	294980	1			T22	15		T23	6806		T24	10
bins_for_gpio_bits[11]	auto[1]	auto[1]	6133765	1			T20	41		T22	111		T23	124832
bins_for_gpio_bits[12]	auto[0]	auto[0]	9611004	1			T20	42		T22	305		T23	231989
bins_for_gpio_bits[12]	auto[0]	auto[1]	294097	1			T22	9		T23	6709		T24	18
bins_for_gpio_bits[12]	auto[1]	auto[0]	294341	1			T22	9		T23	6709		T24	18
bins_for_gpio_bits[12]	auto[1]	auto[1]	6133049	1			T20	80		T22	85		T23	124839
bins_for_gpio_bits[13]	auto[0]	auto[0]	9620685	1			T20	43		T22	302		T23	231096
bins_for_gpio_bits[13]	auto[0]	auto[1]	293166	1			T22	10		T23	6758		T24	15
bins_for_gpio_bits[13]	auto[1]	auto[0]	293409	1			T22	10		T23	6758		T24	16
bins_for_gpio_bits[13]	auto[1]	auto[1]	6125231	1			T20	79		T22	86		T23	125634
bins_for_gpio_bits[14]	auto[0]	auto[0]	9607756	1			T20	45		T22	313		T23	231591
bins_for_gpio_bits[14]	auto[0]	auto[1]	294063	1			T22	8		T23	6831		T24	11
bins_for_gpio_bits[14]	auto[1]	auto[0]	294317	1			T22	8		T23	6832		T24	11
bins_for_gpio_bits[14]	auto[1]	auto[1]	6136355	1			T20	77		T22	79		T23	124992
bins_for_gpio_bits[15]	auto[0]	auto[0]	9611267	1			T20	80		T22	314		T23	231892
bins_for_gpio_bits[15]	auto[0]	auto[1]	293735	1			T22	9		T23	6782		T24	16
bins_for_gpio_bits[15]	auto[1]	auto[0]	293991	1			T22	9		T23	6783		T24	16
bins_for_gpio_bits[15]	auto[1]	auto[1]	6133498	1			T20	42		T22	76		T23	124789
bins_for_gpio_bits[16]	auto[0]	auto[0]	9608189	1			T20	89		T22	287		T23	232234
bins_for_gpio_bits[16]	auto[0]	auto[1]	294050	1			T22	12		T23	6667		T24	13
bins_for_gpio_bits[16]	auto[1]	auto[0]	294296	1			T22	12		T23	6667		T24	13
bins_for_gpio_bits[16]	auto[1]	auto[1]	6135956	1			T20	33		T22	97		T23	124678
bins_for_gpio_bits[17]	auto[0]	auto[0]	9615992	1			T20	49		T22	314		T23	232017
bins_for_gpio_bits[17]	auto[0]	auto[1]	294477	1			T22	4		T23	6768		T24	17
bins_for_gpio_bits[17]	auto[1]	auto[0]	294754	1			T22	5		T23	6768		T24	17
bins_for_gpio_bits[17]	auto[1]	auto[1]	6127268	1			T20	73		T22	85		T23	124693
bins_for_gpio_bits[18]	auto[0]	auto[0]	9617836	1			T20	46		T22	306		T23	232454
bins_for_gpio_bits[18]	auto[0]	auto[1]	293772	1			T22	10		T23	6769		T24	13
bins_for_gpio_bits[18]	auto[1]	auto[0]	293963	1			T22	11		T23	6769		T24	13
bins_for_gpio_bits[18]	auto[1]	auto[1]	6126920	1			T20	76		T22	81		T23	124254
bins_for_gpio_bits[19]	auto[0]	auto[0]	9623647	1			T20	60		T22	312		T23	232608
bins_for_gpio_bits[19]	auto[0]	auto[1]	293555	1			T22	5		T23	6717		T24	13
bins_for_gpio_bits[19]	auto[1]	auto[0]	293805	1			T22	5		T23	6718		T24	13
bins_for_gpio_bits[19]	auto[1]	auto[1]	6121484	1			T20	62		T22	86		T23	124203
bins_for_gpio_bits[20]	auto[0]	auto[0]	9612084	1			T20	59		T22	290		T23	232140
bins_for_gpio_bits[20]	auto[0]	auto[1]	293855	1			T22	11		T23	6767		T24	17
bins_for_gpio_bits[20]	auto[1]	auto[0]	294067	1			T22	11		T23	6767		T24	17
bins_for_gpio_bits[20]	auto[1]	auto[1]	6132485	1			T20	63		T22	96		T23	124572
bins_for_gpio_bits[21]	auto[0]	auto[0]	9620718	1			T20	42		T22	278		T23	232684
bins_for_gpio_bits[21]	auto[0]	auto[1]	293541	1			T22	12		T23	6734		T24	17
bins_for_gpio_bits[21]	auto[1]	auto[0]	293793	1			T22	13		T23	6734		T24	17
bins_for_gpio_bits[21]	auto[1]	auto[1]	6124439	1			T20	80		T22	105		T23	124094
bins_for_gpio_bits[22]	auto[0]	auto[0]	9616322	1			T20	71		T22	324		T23	232542
bins_for_gpio_bits[22]	auto[0]	auto[1]	293772	1			T22	6		T23	6694		T24	15
bins_for_gpio_bits[22]	auto[1]	auto[0]	294014	1			T22	7		T23	6694		T24	15
bins_for_gpio_bits[22]	auto[1]	auto[1]	6128383	1			T20	51		T22	71		T23	124316
bins_for_gpio_bits[23]	auto[0]	auto[0]	9621284	1			T20	81		T22	317		T23	231477
bins_for_gpio_bits[23]	auto[0]	auto[1]	294017	1			T22	8		T23	6746		T24	13
bins_for_gpio_bits[23]	auto[1]	auto[0]	294272	1			T22	8		T23	6747		T24	13
bins_for_gpio_bits[23]	auto[1]	auto[1]	6122918	1			T20	41		T22	75		T23	125276
bins_for_gpio_bits[24]	auto[0]	auto[0]	9614825	1			T20	52		T22	297		T23	232766
bins_for_gpio_bits[24]	auto[0]	auto[1]	293898	1			T20	1		T22	7		T23	6744
bins_for_gpio_bits[24]	auto[1]	auto[0]	294117	1			T22	8		T23	6744		T24	14
bins_for_gpio_bits[24]	auto[1]	auto[1]	6129651	1			T20	69		T22	96		T23	123992
bins_for_gpio_bits[25]	auto[0]	auto[0]	9625534	1			T20	84		T22	312		T23	231626
bins_for_gpio_bits[25]	auto[0]	auto[1]	293839	1			T22	8		T23	6834		T24	15
bins_for_gpio_bits[25]	auto[1]	auto[0]	294062	1			T22	8		T23	6834		T24	15
bins_for_gpio_bits[25]	auto[1]	auto[1]	6119056	1			T20	38		T22	80		T23	124952
bins_for_gpio_bits[26]	auto[0]	auto[0]	9629722	1			T20	99		T22	315		T23	231820
bins_for_gpio_bits[26]	auto[0]	auto[1]	293288	1			T22	8		T23	6806		T24	17
bins_for_gpio_bits[26]	auto[1]	auto[0]	293522	1			T22	8		T23	6806		T24	17
bins_for_gpio_bits[26]	auto[1]	auto[1]	6115959	1			T20	23		T22	77		T23	124814
bins_for_gpio_bits[27]	auto[0]	auto[0]	9622034	1			T20	81		T22	341		T23	231824
bins_for_gpio_bits[27]	auto[0]	auto[1]	294079	1			T22	6		T23	6786		T24	12
bins_for_gpio_bits[27]	auto[1]	auto[0]	294374	1			T22	6		T23	6786		T24	12
bins_for_gpio_bits[27]	auto[1]	auto[1]	6122004	1			T20	41		T22	55		T23	124850
bins_for_gpio_bits[28]	auto[0]	auto[0]	9610745	1			T20	91		T22	324		T23	231930
bins_for_gpio_bits[28]	auto[0]	auto[1]	293996	1			T22	7		T23	6751		T24	18
bins_for_gpio_bits[28]	auto[1]	auto[0]	294271	1			T22	7		T23	6751		T24	18
bins_for_gpio_bits[28]	auto[1]	auto[1]	6133479	1			T20	31		T22	70		T23	124814
bins_for_gpio_bits[29]	auto[0]	auto[0]	9610208	1			T20	62		T22	299		T23	231846
bins_for_gpio_bits[29]	auto[0]	auto[1]	293900	1			T22	13		T23	6783		T24	15
bins_for_gpio_bits[29]	auto[1]	auto[0]	294145	1			T22	14		T23	6783		T24	15
bins_for_gpio_bits[29]	auto[1]	auto[1]	6134238	1			T20	60		T22	82		T23	124834
bins_for_gpio_bits[30]	auto[0]	auto[0]	9620092	1			T20	69		T22	292		T23	231257
bins_for_gpio_bits[30]	auto[0]	auto[1]	294032	1			T22	10		T23	6801		T24	12
bins_for_gpio_bits[30]	auto[1]	auto[0]	294279	1			T22	10		T23	6801		T24	12
bins_for_gpio_bits[30]	auto[1]	auto[1]	6124088	1			T20	53		T22	96		T23	125387
bins_for_gpio_bits[31]	auto[0]	auto[0]	9620666	1			T20	77		T22	307		T23	232403
bins_for_gpio_bits[31]	auto[0]	auto[1]	293260	1			T22	7		T23	6686		T24	15
bins_for_gpio_bits[31]	auto[1]	auto[0]	293529	1			T22	7		T23	6687		T24	15
bins_for_gpio_bits[31]	auto[1]	auto[1]	6125036	1			T20	45		T22	87		T23	124470