Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9418267 |
1 |
|
|
T20 |
69 |
|
T22 |
209 |
|
T23 |
201397 |
| auto[1] |
7188103 |
1 |
|
|
T20 |
36 |
|
T23 |
190483 |
|
T25 |
146 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15688988 |
1 |
|
|
T20 |
103 |
|
T22 |
209 |
|
T23 |
365957 |
| auto[1] |
917382 |
1 |
|
|
T20 |
2 |
|
T23 |
25923 |
|
T25 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9432713 |
1 |
|
|
T20 |
63 |
|
T22 |
209 |
|
T23 |
197085 |
| auto[1] |
7173657 |
1 |
|
|
T20 |
42 |
|
T23 |
194795 |
|
T25 |
197 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3152637 |
1 |
|
|
T20 |
31 |
|
T23 |
86368 |
|
T25 |
98 |
| auto[1] |
auto[0] |
auto[1] |
462975 |
1 |
|
|
T20 |
2 |
|
T23 |
13130 |
|
T25 |
6 |
| auto[1] |
auto[1] |
auto[0] |
3103638 |
1 |
|
|
T20 |
9 |
|
T23 |
82504 |
|
T25 |
87 |
| auto[1] |
auto[1] |
auto[1] |
454407 |
1 |
|
|
T23 |
12793 |
|
T25 |
6 |
|
T27 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9376290 |
1 |
|
|
T20 |
91 |
|
T22 |
209 |
|
T23 |
195887 |
| auto[1] |
7230080 |
1 |
|
|
T20 |
14 |
|
T23 |
195993 |
|
T25 |
160 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15675988 |
1 |
|
|
T20 |
105 |
|
T22 |
209 |
|
T23 |
365061 |
| auto[1] |
930382 |
1 |
|
|
T23 |
26819 |
|
T25 |
9 |
|
T27 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9366246 |
1 |
|
|
T20 |
70 |
|
T22 |
209 |
|
T23 |
192082 |
| auto[1] |
7240124 |
1 |
|
|
T20 |
35 |
|
T23 |
199798 |
|
T25 |
131 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3141864 |
1 |
|
|
T20 |
31 |
|
T23 |
86503 |
|
T25 |
58 |
| auto[1] |
auto[0] |
auto[1] |
462993 |
1 |
|
|
T23 |
13523 |
|
T25 |
5 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[0] |
3167878 |
1 |
|
|
T20 |
4 |
|
T23 |
86476 |
|
T25 |
64 |
| auto[1] |
auto[1] |
auto[1] |
467389 |
1 |
|
|
T23 |
13296 |
|
T25 |
4 |
|
T28 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9373176 |
1 |
|
|
T20 |
64 |
|
T22 |
209 |
|
T23 |
193515 |
| auto[1] |
7233194 |
1 |
|
|
T20 |
41 |
|
T23 |
198365 |
|
T25 |
199 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15676898 |
1 |
|
|
T20 |
104 |
|
T22 |
209 |
|
T23 |
365726 |
| auto[1] |
929472 |
1 |
|
|
T20 |
1 |
|
T23 |
26154 |
|
T25 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9361459 |
1 |
|
|
T20 |
72 |
|
T22 |
209 |
|
T23 |
196334 |
| auto[1] |
7244911 |
1 |
|
|
T20 |
33 |
|
T23 |
195546 |
|
T25 |
155 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3150466 |
1 |
|
|
T20 |
16 |
|
T23 |
84262 |
|
T25 |
45 |
| auto[1] |
auto[0] |
auto[1] |
463433 |
1 |
|
|
T23 |
12987 |
|
T25 |
4 |
|
T27 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3164973 |
1 |
|
|
T20 |
16 |
|
T23 |
85130 |
|
T25 |
97 |
| auto[1] |
auto[1] |
auto[1] |
466039 |
1 |
|
|
T20 |
1 |
|
T23 |
13167 |
|
T25 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9386568 |
1 |
|
|
T20 |
37 |
|
T22 |
209 |
|
T23 |
192441 |
| auto[1] |
7219802 |
1 |
|
|
T20 |
68 |
|
T23 |
199439 |
|
T25 |
185 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15677221 |
1 |
|
|
T20 |
104 |
|
T22 |
209 |
|
T23 |
364998 |
| auto[1] |
929149 |
1 |
|
|
T20 |
1 |
|
T23 |
26882 |
|
T25 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9372583 |
1 |
|
|
T20 |
71 |
|
T22 |
209 |
|
T23 |
190537 |
| auto[1] |
7233787 |
1 |
|
|
T20 |
34 |
|
T23 |
201343 |
|
T25 |
124 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3159808 |
1 |
|
|
T20 |
10 |
|
T23 |
83596 |
|
T25 |
56 |
| auto[1] |
auto[0] |
auto[1] |
465689 |
1 |
|
|
T20 |
1 |
|
T23 |
12865 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3144830 |
1 |
|
|
T20 |
23 |
|
T23 |
90865 |
|
T25 |
61 |
| auto[1] |
auto[1] |
auto[1] |
463460 |
1 |
|
|
T23 |
14017 |
|
T25 |
5 |
|
T27 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9388993 |
1 |
|
|
T20 |
49 |
|
T22 |
209 |
|
T23 |
202245 |
| auto[1] |
7217377 |
1 |
|
|
T20 |
56 |
|
T23 |
189635 |
|
T25 |
159 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15678351 |
1 |
|
|
T20 |
105 |
|
T22 |
209 |
|
T23 |
366372 |
| auto[1] |
928019 |
1 |
|
|
T23 |
25508 |
|
T25 |
4 |
|
T27 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9378043 |
1 |
|
|
T20 |
86 |
|
T22 |
209 |
|
T23 |
198021 |
| auto[1] |
7228327 |
1 |
|
|
T20 |
19 |
|
T23 |
193859 |
|
T25 |
122 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3158639 |
1 |
|
|
T20 |
3 |
|
T23 |
86277 |
|
T25 |
48 |
| auto[1] |
auto[0] |
auto[1] |
464549 |
1 |
|
|
T23 |
13049 |
|
T25 |
2 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[0] |
3141669 |
1 |
|
|
T20 |
16 |
|
T23 |
82074 |
|
T25 |
70 |
| auto[1] |
auto[1] |
auto[1] |
463470 |
1 |
|
|
T23 |
12459 |
|
T25 |
2 |
|
T28 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9338904 |
1 |
|
|
T20 |
88 |
|
T22 |
209 |
|
T23 |
188927 |
| auto[1] |
7267466 |
1 |
|
|
T20 |
17 |
|
T23 |
202953 |
|
T25 |
159 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15672025 |
1 |
|
|
T20 |
104 |
|
T22 |
209 |
|
T23 |
365694 |
| auto[1] |
934345 |
1 |
|
|
T20 |
1 |
|
T23 |
26186 |
|
T25 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9339412 |
1 |
|
|
T20 |
77 |
|
T22 |
209 |
|
T23 |
196352 |
| auto[1] |
7266958 |
1 |
|
|
T20 |
28 |
|
T23 |
195528 |
|
T25 |
175 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3143930 |
1 |
|
|
T20 |
17 |
|
T23 |
81546 |
|
T25 |
73 |
| auto[1] |
auto[0] |
auto[1] |
462714 |
1 |
|
|
T23 |
12491 |
|
T25 |
2 |
|
T28 |
4 |
| auto[1] |
auto[1] |
auto[0] |
3188683 |
1 |
|
|
T20 |
10 |
|
T23 |
87796 |
|
T25 |
94 |
| auto[1] |
auto[1] |
auto[1] |
471631 |
1 |
|
|
T20 |
1 |
|
T23 |
13695 |
|
T25 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9388683 |
1 |
|
|
T20 |
58 |
|
T22 |
209 |
|
T23 |
194754 |
| auto[1] |
7217687 |
1 |
|
|
T20 |
47 |
|
T23 |
197126 |
|
T25 |
82 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15678253 |
1 |
|
|
T20 |
104 |
|
T22 |
209 |
|
T23 |
364938 |
| auto[1] |
928117 |
1 |
|
|
T20 |
1 |
|
T23 |
26942 |
|
T25 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9384815 |
1 |
|
|
T20 |
70 |
|
T22 |
209 |
|
T23 |
189915 |
| auto[1] |
7221555 |
1 |
|
|
T20 |
35 |
|
T23 |
201965 |
|
T25 |
161 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3170313 |
1 |
|
|
T20 |
13 |
|
T23 |
88175 |
|
T25 |
109 |
| auto[1] |
auto[0] |
auto[1] |
468311 |
1 |
|
|
T23 |
13589 |
|
T25 |
9 |
|
T27 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3123125 |
1 |
|
|
T20 |
21 |
|
T23 |
86848 |
|
T25 |
40 |
| auto[1] |
auto[1] |
auto[1] |
459806 |
1 |
|
|
T20 |
1 |
|
T23 |
13353 |
|
T25 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9377275 |
1 |
|
|
T20 |
29 |
|
T22 |
209 |
|
T23 |
195852 |
| auto[1] |
7229095 |
1 |
|
|
T20 |
76 |
|
T23 |
196028 |
|
T25 |
184 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15670112 |
1 |
|
|
T20 |
103 |
|
T22 |
209 |
|
T23 |
365456 |
| auto[1] |
936258 |
1 |
|
|
T20 |
2 |
|
T23 |
26424 |
|
T25 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9324585 |
1 |
|
|
T20 |
65 |
|
T22 |
209 |
|
T23 |
194710 |
| auto[1] |
7281785 |
1 |
|
|
T20 |
40 |
|
T23 |
197170 |
|
T25 |
104 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3177234 |
1 |
|
|
T20 |
4 |
|
T23 |
83946 |
|
T25 |
27 |
| auto[1] |
auto[0] |
auto[1] |
468129 |
1 |
|
|
T23 |
12940 |
|
T25 |
2 |
|
T27 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3168293 |
1 |
|
|
T20 |
34 |
|
T23 |
86800 |
|
T25 |
71 |
| auto[1] |
auto[1] |
auto[1] |
468129 |
1 |
|
|
T20 |
2 |
|
T23 |
13484 |
|
T25 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9392327 |
1 |
|
|
T20 |
35 |
|
T22 |
209 |
|
T23 |
197410 |
| auto[1] |
7214043 |
1 |
|
|
T20 |
70 |
|
T23 |
194470 |
|
T25 |
168 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15676648 |
1 |
|
|
T20 |
104 |
|
T22 |
209 |
|
T23 |
365780 |
| auto[1] |
929722 |
1 |
|
|
T20 |
1 |
|
T23 |
26100 |
|
T25 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9363769 |
1 |
|
|
T20 |
78 |
|
T22 |
209 |
|
T23 |
194084 |
| auto[1] |
7242601 |
1 |
|
|
T20 |
27 |
|
T23 |
197796 |
|
T25 |
173 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3169266 |
1 |
|
|
T20 |
4 |
|
T23 |
87979 |
|
T25 |
82 |
| auto[1] |
auto[0] |
auto[1] |
467136 |
1 |
|
|
T23 |
13367 |
|
T25 |
5 |
|
T28 |
8 |
| auto[1] |
auto[1] |
auto[0] |
3143613 |
1 |
|
|
T20 |
22 |
|
T23 |
83717 |
|
T25 |
79 |
| auto[1] |
auto[1] |
auto[1] |
462586 |
1 |
|
|
T20 |
1 |
|
T23 |
12733 |
|
T25 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9391705 |
1 |
|
|
T20 |
71 |
|
T22 |
209 |
|
T23 |
194345 |
| auto[1] |
7214665 |
1 |
|
|
T20 |
34 |
|
T23 |
197535 |
|
T25 |
171 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15676366 |
1 |
|
|
T20 |
105 |
|
T22 |
209 |
|
T23 |
366671 |
| auto[1] |
930004 |
1 |
|
|
T23 |
25209 |
|
T25 |
9 |
|
T28 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9360264 |
1 |
|
|
T20 |
85 |
|
T22 |
209 |
|
T23 |
199409 |
| auto[1] |
7246106 |
1 |
|
|
T20 |
20 |
|
T23 |
192471 |
|
T25 |
153 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3161445 |
1 |
|
|
T20 |
10 |
|
T23 |
82353 |
|
T25 |
56 |
| auto[1] |
auto[0] |
auto[1] |
464955 |
1 |
|
|
T23 |
12580 |
|
T25 |
4 |
|
T28 |
7 |
| auto[1] |
auto[1] |
auto[0] |
3154657 |
1 |
|
|
T20 |
10 |
|
T23 |
84909 |
|
T25 |
88 |
| auto[1] |
auto[1] |
auto[1] |
465049 |
1 |
|
|
T23 |
12629 |
|
T25 |
5 |
|
T28 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9372941 |
1 |
|
|
T20 |
81 |
|
T22 |
209 |
|
T23 |
193317 |
| auto[1] |
7233429 |
1 |
|
|
T20 |
24 |
|
T23 |
198563 |
|
T25 |
145 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15680547 |
1 |
|
|
T20 |
104 |
|
T22 |
209 |
|
T23 |
366190 |
| auto[1] |
925823 |
1 |
|
|
T20 |
1 |
|
T23 |
25690 |
|
T25 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9387736 |
1 |
|
|
T20 |
76 |
|
T22 |
209 |
|
T23 |
197747 |
| auto[1] |
7218634 |
1 |
|
|
T20 |
29 |
|
T23 |
194133 |
|
T25 |
144 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3156161 |
1 |
|
|
T20 |
14 |
|
T23 |
83408 |
|
T25 |
62 |
| auto[1] |
auto[0] |
auto[1] |
464295 |
1 |
|
|
T20 |
1 |
|
T23 |
12707 |
|
T25 |
6 |
| auto[1] |
auto[1] |
auto[0] |
3136650 |
1 |
|
|
T20 |
14 |
|
T23 |
85035 |
|
T25 |
72 |
| auto[1] |
auto[1] |
auto[1] |
461528 |
1 |
|
|
T23 |
12983 |
|
T25 |
4 |
|
T27 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9416996 |
1 |
|
|
T20 |
39 |
|
T22 |
209 |
|
T23 |
207616 |
| auto[1] |
7189374 |
1 |
|
|
T20 |
66 |
|
T23 |
184264 |
|
T25 |
173 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15678149 |
1 |
|
|
T20 |
104 |
|
T22 |
209 |
|
T23 |
366244 |
| auto[1] |
928221 |
1 |
|
|
T20 |
1 |
|
T23 |
25636 |
|
T25 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9369937 |
1 |
|
|
T20 |
71 |
|
T22 |
209 |
|
T23 |
197467 |
| auto[1] |
7236433 |
1 |
|
|
T20 |
34 |
|
T23 |
194413 |
|
T25 |
74 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3167489 |
1 |
|
|
T20 |
5 |
|
T23 |
89342 |
|
T25 |
30 |
| auto[1] |
auto[0] |
auto[1] |
466416 |
1 |
|
|
T23 |
13742 |
|
T25 |
1 |
|
T28 |
6 |
| auto[1] |
auto[1] |
auto[0] |
3140723 |
1 |
|
|
T20 |
28 |
|
T23 |
79435 |
|
T25 |
42 |
| auto[1] |
auto[1] |
auto[1] |
461805 |
1 |
|
|
T20 |
1 |
|
T23 |
11894 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9377427 |
1 |
|
|
T20 |
68 |
|
T22 |
209 |
|
T23 |
193759 |
| auto[1] |
7228943 |
1 |
|
|
T20 |
37 |
|
T23 |
198121 |
|
T25 |
92 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15684296 |
1 |
|
|
T20 |
104 |
|
T22 |
209 |
|
T23 |
365666 |
| auto[1] |
922074 |
1 |
|
|
T20 |
1 |
|
T23 |
26214 |
|
T25 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9411333 |
1 |
|
|
T20 |
75 |
|
T22 |
209 |
|
T23 |
193845 |
| auto[1] |
7195037 |
1 |
|
|
T20 |
30 |
|
T23 |
198035 |
|
T25 |
204 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3148488 |
1 |
|
|
T20 |
24 |
|
T23 |
84247 |
|
T25 |
129 |
| auto[1] |
auto[0] |
auto[1] |
462546 |
1 |
|
|
T20 |
1 |
|
T23 |
12787 |
|
T25 |
9 |
| auto[1] |
auto[1] |
auto[0] |
3124475 |
1 |
|
|
T20 |
5 |
|
T23 |
87574 |
|
T25 |
63 |
| auto[1] |
auto[1] |
auto[1] |
459528 |
1 |
|
|
T23 |
13427 |
|
T25 |
3 |
|
T28 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9356964 |
1 |
|
|
T20 |
62 |
|
T22 |
209 |
|
T23 |
190868 |
| auto[1] |
7249406 |
1 |
|
|
T20 |
43 |
|
T23 |
201012 |
|
T25 |
183 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15675472 |
1 |
|
|
T20 |
103 |
|
T22 |
209 |
|
T23 |
365519 |
| auto[1] |
930898 |
1 |
|
|
T20 |
2 |
|
T23 |
26361 |
|
T25 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9361706 |
1 |
|
|
T20 |
59 |
|
T22 |
209 |
|
T23 |
194847 |
| auto[1] |
7244664 |
1 |
|
|
T20 |
46 |
|
T23 |
197033 |
|
T25 |
131 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3158101 |
1 |
|
|
T20 |
22 |
|
T23 |
83068 |
|
T25 |
50 |
| auto[1] |
auto[0] |
auto[1] |
465291 |
1 |
|
|
T20 |
1 |
|
T23 |
12581 |
|
T25 |
4 |
| auto[1] |
auto[1] |
auto[0] |
3155665 |
1 |
|
|
T20 |
22 |
|
T23 |
87604 |
|
T25 |
74 |
| auto[1] |
auto[1] |
auto[1] |
465607 |
1 |
|
|
T20 |
1 |
|
T23 |
13780 |
|
T25 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9383410 |
1 |
|
|
T20 |
69 |
|
T22 |
209 |
|
T23 |
197980 |
| auto[1] |
7222960 |
1 |
|
|
T20 |
36 |
|
T23 |
193900 |
|
T25 |
134 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15688756 |
1 |
|
|
T20 |
103 |
|
T22 |
209 |
|
T23 |
366255 |
| auto[1] |
917614 |
1 |
|
|
T20 |
2 |
|
T23 |
25625 |
|
T25 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9431745 |
1 |
|
|
T20 |
47 |
|
T22 |
209 |
|
T23 |
197828 |
| auto[1] |
7174625 |
1 |
|
|
T20 |
58 |
|
T23 |
194052 |
|
T25 |
108 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3125106 |
1 |
|
|
T20 |
27 |
|
T23 |
82783 |
|
T25 |
45 |
| auto[1] |
auto[0] |
auto[1] |
458314 |
1 |
|
|
T20 |
1 |
|
T23 |
12395 |
|
T25 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3131905 |
1 |
|
|
T20 |
29 |
|
T23 |
85644 |
|
T25 |
57 |
| auto[1] |
auto[1] |
auto[1] |
459300 |
1 |
|
|
T20 |
1 |
|
T23 |
13230 |
|
T25 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9394485 |
1 |
|
|
T20 |
69 |
|
T22 |
209 |
|
T23 |
189802 |
| auto[1] |
7211885 |
1 |
|
|
T20 |
36 |
|
T23 |
202078 |
|
T25 |
109 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15682942 |
1 |
|
|
T20 |
104 |
|
T22 |
209 |
|
T23 |
366629 |
| auto[1] |
923428 |
1 |
|
|
T20 |
1 |
|
T23 |
25251 |
|
T25 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9392993 |
1 |
|
|
T20 |
75 |
|
T22 |
209 |
|
T23 |
199976 |
| auto[1] |
7213377 |
1 |
|
|
T20 |
30 |
|
T23 |
191904 |
|
T25 |
104 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3147119 |
1 |
|
|
T20 |
25 |
|
T23 |
81007 |
|
T25 |
56 |
| auto[1] |
auto[0] |
auto[1] |
462774 |
1 |
|
|
T20 |
1 |
|
T23 |
12349 |
|
T25 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3142830 |
1 |
|
|
T20 |
4 |
|
T23 |
85646 |
|
T25 |
44 |
| auto[1] |
auto[1] |
auto[1] |
460654 |
1 |
|
|
T23 |
12902 |
|
T25 |
1 |
|
T27 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9394366 |
1 |
|
|
T20 |
81 |
|
T22 |
209 |
|
T23 |
191400 |
| auto[1] |
7212004 |
1 |
|
|
T20 |
24 |
|
T23 |
200480 |
|
T25 |
143 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15677515 |
1 |
|
|
T20 |
105 |
|
T22 |
209 |
|
T23 |
364437 |
| auto[1] |
928855 |
1 |
|
|
T23 |
27443 |
|
T25 |
11 |
|
T27 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9375849 |
1 |
|
|
T20 |
73 |
|
T22 |
209 |
|
T23 |
187679 |
| auto[1] |
7230521 |
1 |
|
|
T20 |
32 |
|
T23 |
204201 |
|
T25 |
189 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3161619 |
1 |
|
|
T20 |
27 |
|
T23 |
85995 |
|
T25 |
87 |
| auto[1] |
auto[0] |
auto[1] |
466708 |
1 |
|
|
T23 |
13284 |
|
T25 |
5 |
|
T27 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3140047 |
1 |
|
|
T20 |
5 |
|
T23 |
90763 |
|
T25 |
91 |
| auto[1] |
auto[1] |
auto[1] |
462147 |
1 |
|
|
T23 |
14159 |
|
T25 |
6 |
|
T28 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9366290 |
1 |
|
|
T20 |
88 |
|
T22 |
209 |
|
T23 |
198971 |
| auto[1] |
7240080 |
1 |
|
|
T20 |
17 |
|
T23 |
192909 |
|
T25 |
90 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15678352 |
1 |
|
|
T20 |
104 |
|
T22 |
209 |
|
T23 |
365608 |
| auto[1] |
928018 |
1 |
|
|
T20 |
1 |
|
T23 |
26272 |
|
T25 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9385066 |
1 |
|
|
T20 |
63 |
|
T22 |
209 |
|
T23 |
195453 |
| auto[1] |
7221304 |
1 |
|
|
T20 |
42 |
|
T23 |
196427 |
|
T25 |
199 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3136769 |
1 |
|
|
T20 |
31 |
|
T23 |
87655 |
|
T25 |
122 |
| auto[1] |
auto[0] |
auto[1] |
462230 |
1 |
|
|
T23 |
13561 |
|
T25 |
10 |
|
T27 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3156517 |
1 |
|
|
T20 |
10 |
|
T23 |
82500 |
|
T25 |
64 |
| auto[1] |
auto[1] |
auto[1] |
465788 |
1 |
|
|
T20 |
1 |
|
T23 |
12711 |
|
T25 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9362278 |
1 |
|
|
T20 |
71 |
|
T22 |
209 |
|
T23 |
198675 |
| auto[1] |
7244092 |
1 |
|
|
T20 |
34 |
|
T23 |
193205 |
|
T25 |
123 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15675315 |
1 |
|
|
T20 |
105 |
|
T22 |
209 |
|
T23 |
365673 |
| auto[1] |
931055 |
1 |
|
|
T23 |
26207 |
|
T25 |
17 |
|
T27 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9360687 |
1 |
|
|
T20 |
77 |
|
T22 |
209 |
|
T23 |
195555 |
| auto[1] |
7245683 |
1 |
|
|
T20 |
28 |
|
T23 |
196325 |
|
T25 |
263 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3149696 |
1 |
|
|
T20 |
22 |
|
T23 |
87376 |
|
T25 |
142 |
| auto[1] |
auto[0] |
auto[1] |
464890 |
1 |
|
|
T23 |
13385 |
|
T25 |
11 |
|
T27 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3164932 |
1 |
|
|
T20 |
6 |
|
T23 |
82742 |
|
T25 |
104 |
| auto[1] |
auto[1] |
auto[1] |
466165 |
1 |
|
|
T23 |
12822 |
|
T25 |
6 |
|
T27 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9349026 |
1 |
|
|
T20 |
68 |
|
T22 |
209 |
|
T23 |
195643 |
| auto[1] |
7257344 |
1 |
|
|
T20 |
37 |
|
T23 |
196237 |
|
T25 |
189 |