Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9377775 |
1 |
|
|
T20 |
32 |
|
T22 |
209 |
|
T23 |
196798 |
| auto[1] |
7228595 |
1 |
|
|
T20 |
73 |
|
T23 |
195082 |
|
T25 |
151 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15680878 |
1 |
|
|
T20 |
104 |
|
T22 |
209 |
|
T23 |
365244 |
| auto[1] |
925492 |
1 |
|
|
T20 |
1 |
|
T23 |
26636 |
|
T25 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9397943 |
1 |
|
|
T20 |
76 |
|
T22 |
209 |
|
T23 |
194312 |
| auto[1] |
7208427 |
1 |
|
|
T20 |
29 |
|
T23 |
197568 |
|
T25 |
136 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3140314 |
1 |
|
|
T20 |
3 |
|
T23 |
82436 |
|
T25 |
69 |
| auto[1] |
auto[0] |
auto[1] |
462323 |
1 |
|
|
T23 |
12823 |
|
T25 |
3 |
|
T27 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3142621 |
1 |
|
|
T20 |
25 |
|
T23 |
88496 |
|
T25 |
60 |
| auto[1] |
auto[1] |
auto[1] |
463169 |
1 |
|
|
T20 |
1 |
|
T23 |
13813 |
|
T25 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |