Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9365188 |
1 |
|
|
T20 |
67 |
|
T22 |
209 |
|
T23 |
196129 |
| auto[1] |
7241182 |
1 |
|
|
T20 |
38 |
|
T23 |
195751 |
|
T25 |
107 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15681501 |
1 |
|
|
T20 |
104 |
|
T22 |
209 |
|
T23 |
366860 |
| auto[1] |
924869 |
1 |
|
|
T20 |
1 |
|
T23 |
25020 |
|
T25 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9389239 |
1 |
|
|
T20 |
76 |
|
T22 |
209 |
|
T23 |
200710 |
| auto[1] |
7217131 |
1 |
|
|
T20 |
29 |
|
T23 |
191170 |
|
T25 |
115 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3151130 |
1 |
|
|
T20 |
8 |
|
T23 |
82060 |
|
T25 |
72 |
| auto[1] |
auto[0] |
auto[1] |
462568 |
1 |
|
|
T23 |
12321 |
|
T25 |
7 |
|
T27 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3141132 |
1 |
|
|
T20 |
20 |
|
T23 |
84090 |
|
T25 |
35 |
| auto[1] |
auto[1] |
auto[1] |
462301 |
1 |
|
|
T20 |
1 |
|
T23 |
12699 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |