Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9366248 |
1 |
|
|
T20 |
56 |
|
T22 |
209 |
|
T23 |
198329 |
| auto[1] |
7240122 |
1 |
|
|
T20 |
49 |
|
T23 |
193551 |
|
T25 |
123 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15681350 |
1 |
|
|
T20 |
105 |
|
T22 |
209 |
|
T23 |
365687 |
| auto[1] |
925020 |
1 |
|
|
T23 |
26193 |
|
T25 |
10 |
|
T27 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9389592 |
1 |
|
|
T20 |
73 |
|
T22 |
209 |
|
T23 |
195530 |
| auto[1] |
7216778 |
1 |
|
|
T20 |
32 |
|
T23 |
196350 |
|
T25 |
141 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3147992 |
1 |
|
|
T20 |
8 |
|
T23 |
85933 |
|
T25 |
47 |
| auto[1] |
auto[0] |
auto[1] |
462868 |
1 |
|
|
T23 |
13229 |
|
T25 |
6 |
|
T28 |
6 |
| auto[1] |
auto[1] |
auto[0] |
3143766 |
1 |
|
|
T20 |
24 |
|
T23 |
84224 |
|
T25 |
84 |
| auto[1] |
auto[1] |
auto[1] |
462152 |
1 |
|
|
T23 |
12964 |
|
T25 |
4 |
|
T27 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |