Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9391072 |
1 |
|
|
T20 |
57 |
|
T22 |
209 |
|
T23 |
198147 |
| auto[1] |
7215298 |
1 |
|
|
T20 |
48 |
|
T23 |
193733 |
|
T25 |
174 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15680581 |
1 |
|
|
T20 |
104 |
|
T22 |
209 |
|
T23 |
365933 |
| auto[1] |
925789 |
1 |
|
|
T20 |
1 |
|
T23 |
25947 |
|
T25 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9386854 |
1 |
|
|
T20 |
60 |
|
T22 |
209 |
|
T23 |
195863 |
| auto[1] |
7219516 |
1 |
|
|
T20 |
45 |
|
T23 |
196017 |
|
T25 |
117 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3160975 |
1 |
|
|
T20 |
16 |
|
T23 |
87424 |
|
T25 |
40 |
| auto[1] |
auto[0] |
auto[1] |
465453 |
1 |
|
|
T20 |
1 |
|
T23 |
13302 |
|
T25 |
4 |
| auto[1] |
auto[1] |
auto[0] |
3132752 |
1 |
|
|
T20 |
28 |
|
T23 |
82646 |
|
T25 |
69 |
| auto[1] |
auto[1] |
auto[1] |
460336 |
1 |
|
|
T23 |
12645 |
|
T25 |
4 |
|
T27 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |