Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9368895 |
1 |
|
|
T20 |
40 |
|
T22 |
209 |
|
T23 |
194930 |
| auto[1] |
7237475 |
1 |
|
|
T20 |
65 |
|
T23 |
196950 |
|
T25 |
153 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15678525 |
1 |
|
|
T20 |
105 |
|
T22 |
209 |
|
T23 |
365985 |
| auto[1] |
927845 |
1 |
|
|
T23 |
25895 |
|
T25 |
8 |
|
T27 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9372368 |
1 |
|
|
T20 |
78 |
|
T22 |
209 |
|
T23 |
196494 |
| auto[1] |
7234002 |
1 |
|
|
T20 |
27 |
|
T23 |
195386 |
|
T25 |
120 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3153930 |
1 |
|
|
T20 |
16 |
|
T23 |
83674 |
|
T25 |
49 |
| auto[1] |
auto[0] |
auto[1] |
463979 |
1 |
|
|
T23 |
12664 |
|
T25 |
4 |
|
T27 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3152227 |
1 |
|
|
T20 |
11 |
|
T23 |
85817 |
|
T25 |
63 |
| auto[1] |
auto[1] |
auto[1] |
463866 |
1 |
|
|
T23 |
13231 |
|
T25 |
4 |
|
T28 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |