Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15684379 |
1 |
|
|
T20 |
103 |
|
T22 |
209 |
|
T23 |
366291 |
| auto[1] |
921991 |
1 |
|
|
T20 |
2 |
|
T23 |
25589 |
|
T25 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9406850 |
1 |
|
|
T20 |
60 |
|
T22 |
209 |
|
T23 |
199976 |
| auto[1] |
7199520 |
1 |
|
|
T20 |
45 |
|
T23 |
191904 |
|
T25 |
127 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3131898 |
1 |
|
|
T20 |
24 |
|
T23 |
81485 |
|
T25 |
44 |
| auto[1] |
auto[0] |
auto[1] |
459836 |
1 |
|
|
T20 |
1 |
|
T23 |
12305 |
|
T25 |
4 |
| auto[1] |
auto[1] |
auto[0] |
3145631 |
1 |
|
|
T20 |
19 |
|
T23 |
84830 |
|
T25 |
75 |
| auto[1] |
auto[1] |
auto[1] |
462155 |
1 |
|
|
T20 |
1 |
|
T23 |
13284 |
|
T25 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |