Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9338904 |
1 |
|
|
T20 |
88 |
|
T22 |
209 |
|
T23 |
188927 |
| auto[1] |
7267466 |
1 |
|
|
T20 |
17 |
|
T23 |
202953 |
|
T25 |
159 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13680589 |
1 |
|
|
T20 |
86 |
|
T22 |
209 |
|
T23 |
315496 |
| auto[1] |
2925781 |
1 |
|
|
T20 |
19 |
|
T23 |
76384 |
|
T25 |
81 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9410341 |
1 |
|
|
T20 |
72 |
|
T22 |
209 |
|
T23 |
196559 |
| auto[1] |
7196029 |
1 |
|
|
T20 |
33 |
|
T23 |
195321 |
|
T25 |
131 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2124399 |
1 |
|
|
T20 |
10 |
|
T23 |
57070 |
|
T25 |
17 |
| auto[1] |
auto[0] |
auto[1] |
1460550 |
1 |
|
|
T20 |
14 |
|
T23 |
36940 |
|
T25 |
39 |
| auto[1] |
auto[1] |
auto[0] |
2145849 |
1 |
|
|
T20 |
4 |
|
T23 |
61867 |
|
T25 |
33 |
| auto[1] |
auto[1] |
auto[1] |
1465231 |
1 |
|
|
T20 |
5 |
|
T23 |
39444 |
|
T25 |
42 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |