Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9388683 |
1 |
|
|
T20 |
58 |
|
T22 |
209 |
|
T23 |
194754 |
| auto[1] |
7217687 |
1 |
|
|
T20 |
47 |
|
T23 |
197126 |
|
T25 |
82 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13665302 |
1 |
|
|
T20 |
90 |
|
T22 |
209 |
|
T23 |
316930 |
| auto[1] |
2941068 |
1 |
|
|
T20 |
15 |
|
T23 |
74950 |
|
T25 |
46 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9383157 |
1 |
|
|
T20 |
77 |
|
T22 |
209 |
|
T23 |
196890 |
| auto[1] |
7223213 |
1 |
|
|
T20 |
28 |
|
T23 |
194990 |
|
T25 |
94 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2156838 |
1 |
|
|
T20 |
3 |
|
T23 |
61595 |
|
T25 |
23 |
| auto[1] |
auto[0] |
auto[1] |
1477388 |
1 |
|
|
T20 |
12 |
|
T23 |
38044 |
|
T25 |
37 |
| auto[1] |
auto[1] |
auto[0] |
2125307 |
1 |
|
|
T20 |
10 |
|
T23 |
58445 |
|
T25 |
25 |
| auto[1] |
auto[1] |
auto[1] |
1463680 |
1 |
|
|
T20 |
3 |
|
T23 |
36906 |
|
T25 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |