Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9377427 |
1 |
|
|
T20 |
68 |
|
T22 |
209 |
|
T23 |
193759 |
| auto[1] |
7228943 |
1 |
|
|
T20 |
37 |
|
T23 |
198121 |
|
T25 |
92 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13677354 |
1 |
|
|
T20 |
95 |
|
T22 |
209 |
|
T23 |
316484 |
| auto[1] |
2929016 |
1 |
|
|
T20 |
10 |
|
T23 |
75396 |
|
T25 |
45 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9406381 |
1 |
|
|
T20 |
93 |
|
T22 |
209 |
|
T23 |
197271 |
| auto[1] |
7199989 |
1 |
|
|
T20 |
12 |
|
T23 |
194609 |
|
T25 |
128 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2132791 |
1 |
|
|
T23 |
57787 |
|
T25 |
71 |
|
T27 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1463822 |
1 |
|
|
T20 |
5 |
|
T23 |
36911 |
|
T25 |
31 |
| auto[1] |
auto[1] |
auto[0] |
2138182 |
1 |
|
|
T20 |
2 |
|
T23 |
61426 |
|
T25 |
12 |
| auto[1] |
auto[1] |
auto[1] |
1465194 |
1 |
|
|
T20 |
5 |
|
T23 |
38485 |
|
T25 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |