Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9366290 |
1 |
|
|
T20 |
88 |
|
T22 |
209 |
|
T23 |
198971 |
| auto[1] |
7240080 |
1 |
|
|
T20 |
17 |
|
T23 |
192909 |
|
T25 |
90 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13663557 |
1 |
|
|
T20 |
95 |
|
T22 |
209 |
|
T23 |
315054 |
| auto[1] |
2942813 |
1 |
|
|
T20 |
10 |
|
T23 |
76826 |
|
T25 |
77 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9365970 |
1 |
|
|
T20 |
70 |
|
T22 |
209 |
|
T23 |
194321 |
| auto[1] |
7240400 |
1 |
|
|
T20 |
35 |
|
T23 |
197559 |
|
T25 |
156 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2142229 |
1 |
|
|
T20 |
22 |
|
T23 |
59991 |
|
T25 |
70 |
| auto[1] |
auto[0] |
auto[1] |
1471949 |
1 |
|
|
T20 |
7 |
|
T23 |
38517 |
|
T25 |
47 |
| auto[1] |
auto[1] |
auto[0] |
2155358 |
1 |
|
|
T20 |
3 |
|
T23 |
60742 |
|
T25 |
9 |
| auto[1] |
auto[1] |
auto[1] |
1470864 |
1 |
|
|
T20 |
3 |
|
T23 |
38309 |
|
T25 |
30 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |