Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9381162 |
1 |
|
|
T20 |
83 |
|
T22 |
209 |
|
T23 |
197269 |
| auto[1] |
7225208 |
1 |
|
|
T20 |
22 |
|
T23 |
194611 |
|
T25 |
140 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15679432 |
1 |
|
|
T20 |
104 |
|
T22 |
209 |
|
T23 |
365637 |
| auto[1] |
926938 |
1 |
|
|
T20 |
1 |
|
T23 |
26243 |
|
T25 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9375872 |
1 |
|
|
T20 |
48 |
|
T22 |
209 |
|
T23 |
195123 |
| auto[1] |
7230498 |
1 |
|
|
T20 |
57 |
|
T23 |
196757 |
|
T25 |
163 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3134811 |
1 |
|
|
T20 |
45 |
|
T23 |
87036 |
|
T25 |
66 |
| auto[1] |
auto[0] |
auto[1] |
459523 |
1 |
|
|
T20 |
1 |
|
T23 |
13355 |
|
T25 |
6 |
| auto[1] |
auto[1] |
auto[0] |
3168749 |
1 |
|
|
T20 |
11 |
|
T23 |
83478 |
|
T25 |
88 |
| auto[1] |
auto[1] |
auto[1] |
467415 |
1 |
|
|
T23 |
12888 |
|
T25 |
3 |
|
T28 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |