Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9350833 |
1 |
|
|
T20 |
66 |
|
T22 |
209 |
|
T23 |
196367 |
| auto[1] |
7255537 |
1 |
|
|
T20 |
39 |
|
T23 |
195513 |
|
T25 |
202 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15673891 |
1 |
|
|
T20 |
105 |
|
T22 |
209 |
|
T23 |
365113 |
| auto[1] |
932479 |
1 |
|
|
T23 |
26767 |
|
T25 |
9 |
|
T28 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9345534 |
1 |
|
|
T20 |
78 |
|
T22 |
209 |
|
T23 |
191208 |
| auto[1] |
7260836 |
1 |
|
|
T20 |
27 |
|
T23 |
200672 |
|
T25 |
132 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3157163 |
1 |
|
|
T20 |
7 |
|
T23 |
88560 |
|
T25 |
56 |
| auto[1] |
auto[0] |
auto[1] |
464802 |
1 |
|
|
T23 |
13737 |
|
T25 |
3 |
|
T28 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3171194 |
1 |
|
|
T20 |
20 |
|
T23 |
85345 |
|
T25 |
67 |
| auto[1] |
auto[1] |
auto[1] |
467677 |
1 |
|
|
T23 |
13030 |
|
T25 |
6 |
|
T28 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |