Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9402288 |
1 |
|
|
T20 |
71 |
|
T22 |
209 |
|
T23 |
197054 |
| auto[1] |
7204082 |
1 |
|
|
T20 |
34 |
|
T23 |
194826 |
|
T25 |
172 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15678062 |
1 |
|
|
T20 |
105 |
|
T22 |
209 |
|
T23 |
365032 |
| auto[1] |
928308 |
1 |
|
|
T23 |
26848 |
|
T25 |
10 |
|
T27 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9369088 |
1 |
|
|
T20 |
70 |
|
T22 |
209 |
|
T23 |
191660 |
| auto[1] |
7237282 |
1 |
|
|
T20 |
35 |
|
T23 |
200220 |
|
T25 |
163 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3168553 |
1 |
|
|
T20 |
23 |
|
T23 |
89006 |
|
T25 |
60 |
| auto[1] |
auto[0] |
auto[1] |
465902 |
1 |
|
|
T23 |
13790 |
|
T25 |
3 |
|
T28 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3140421 |
1 |
|
|
T20 |
12 |
|
T23 |
84366 |
|
T25 |
93 |
| auto[1] |
auto[1] |
auto[1] |
462406 |
1 |
|
|
T23 |
13058 |
|
T25 |
7 |
|
T27 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |