Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 949
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T765 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1112405273 Mar 24 12:33:38 PM PDT 24 Mar 24 12:33:40 PM PDT 24 68901824 ps
T766 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1963013396 Mar 24 12:33:30 PM PDT 24 Mar 24 12:33:31 PM PDT 24 51817285 ps
T104 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.746270328 Mar 24 12:33:36 PM PDT 24 Mar 24 12:33:38 PM PDT 24 41745191 ps
T767 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.648979303 Mar 24 12:33:49 PM PDT 24 Mar 24 12:33:50 PM PDT 24 39005510 ps
T768 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2885695267 Mar 24 12:33:48 PM PDT 24 Mar 24 12:33:48 PM PDT 24 49777778 ps
T769 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2395820868 Mar 24 12:33:45 PM PDT 24 Mar 24 12:33:46 PM PDT 24 30728717 ps
T770 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1435435334 Mar 24 12:33:33 PM PDT 24 Mar 24 12:33:33 PM PDT 24 29921962 ps
T771 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.847892163 Mar 24 12:35:09 PM PDT 24 Mar 24 12:35:10 PM PDT 24 23889666 ps
T772 /workspace/coverage/cover_reg_top/27.gpio_intr_test.4093807281 Mar 24 12:34:05 PM PDT 24 Mar 24 12:34:05 PM PDT 24 20643826 ps
T773 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3934453657 Mar 24 12:33:40 PM PDT 24 Mar 24 12:33:42 PM PDT 24 42818268 ps
T774 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2001944458 Mar 24 12:33:30 PM PDT 24 Mar 24 12:33:31 PM PDT 24 135746845 ps
T79 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2854683043 Mar 24 12:33:45 PM PDT 24 Mar 24 12:33:51 PM PDT 24 40371169 ps
T775 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1523741898 Mar 24 12:34:10 PM PDT 24 Mar 24 12:34:11 PM PDT 24 16708757 ps
T776 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.485382491 Mar 24 12:35:13 PM PDT 24 Mar 24 12:35:14 PM PDT 24 131063074 ps
T80 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3017342981 Mar 24 12:33:55 PM PDT 24 Mar 24 12:33:56 PM PDT 24 68095718 ps
T777 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.311757183 Mar 24 12:34:36 PM PDT 24 Mar 24 12:34:38 PM PDT 24 47129067 ps
T45 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3047454950 Mar 24 12:33:56 PM PDT 24 Mar 24 12:33:58 PM PDT 24 162399801 ps
T778 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1577398118 Mar 24 12:34:02 PM PDT 24 Mar 24 12:34:02 PM PDT 24 61314210 ps
T81 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1559528885 Mar 24 12:33:13 PM PDT 24 Mar 24 12:33:14 PM PDT 24 54950543 ps
T779 /workspace/coverage/cover_reg_top/21.gpio_intr_test.3229866849 Mar 24 12:33:39 PM PDT 24 Mar 24 12:33:45 PM PDT 24 25118571 ps
T780 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2906040607 Mar 24 12:34:15 PM PDT 24 Mar 24 12:34:16 PM PDT 24 121913417 ps
T781 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2172345544 Mar 24 12:33:31 PM PDT 24 Mar 24 12:33:32 PM PDT 24 25541325 ps
T782 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1904122155 Mar 24 12:33:36 PM PDT 24 Mar 24 12:33:38 PM PDT 24 361950005 ps
T85 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3604408256 Mar 24 12:33:39 PM PDT 24 Mar 24 12:33:41 PM PDT 24 41445953 ps
T783 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.827807574 Mar 24 12:33:57 PM PDT 24 Mar 24 12:33:58 PM PDT 24 13093806 ps
T83 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3325796657 Mar 24 12:33:47 PM PDT 24 Mar 24 12:33:48 PM PDT 24 38895333 ps
T784 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2497469117 Mar 24 12:33:29 PM PDT 24 Mar 24 12:33:30 PM PDT 24 14039590 ps
T785 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2608402898 Mar 24 12:35:18 PM PDT 24 Mar 24 12:35:20 PM PDT 24 106728523 ps
T786 /workspace/coverage/cover_reg_top/40.gpio_intr_test.157234114 Mar 24 12:33:50 PM PDT 24 Mar 24 12:33:50 PM PDT 24 19072743 ps
T86 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1358625733 Mar 24 12:33:45 PM PDT 24 Mar 24 12:33:46 PM PDT 24 16905143 ps
T82 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1262649371 Mar 24 12:33:48 PM PDT 24 Mar 24 12:33:49 PM PDT 24 31435804 ps
T47 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2034382507 Mar 24 12:33:47 PM PDT 24 Mar 24 12:33:49 PM PDT 24 290153751 ps
T787 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2893159055 Mar 24 12:33:47 PM PDT 24 Mar 24 12:33:49 PM PDT 24 62716020 ps
T788 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.845621727 Mar 24 12:34:12 PM PDT 24 Mar 24 12:34:13 PM PDT 24 146433593 ps
T789 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.587194960 Mar 24 12:33:48 PM PDT 24 Mar 24 12:33:49 PM PDT 24 44474525 ps
T790 /workspace/coverage/cover_reg_top/41.gpio_intr_test.1964113984 Mar 24 12:33:50 PM PDT 24 Mar 24 12:33:51 PM PDT 24 61553060 ps
T791 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3844281855 Mar 24 12:33:46 PM PDT 24 Mar 24 12:33:47 PM PDT 24 47194629 ps
T792 /workspace/coverage/cover_reg_top/33.gpio_intr_test.4008175770 Mar 24 12:34:14 PM PDT 24 Mar 24 12:34:15 PM PDT 24 71601057 ps
T793 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3862339255 Mar 24 12:33:31 PM PDT 24 Mar 24 12:33:32 PM PDT 24 23194245 ps
T794 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2424704802 Mar 24 12:33:47 PM PDT 24 Mar 24 12:33:48 PM PDT 24 62715169 ps
T795 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3141263778 Mar 24 12:33:49 PM PDT 24 Mar 24 12:33:49 PM PDT 24 11807530 ps
T796 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3401704761 Mar 24 12:33:41 PM PDT 24 Mar 24 12:33:44 PM PDT 24 173895516 ps
T797 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.543109293 Mar 24 12:33:54 PM PDT 24 Mar 24 12:33:56 PM PDT 24 136833600 ps
T798 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2496223102 Mar 24 12:33:36 PM PDT 24 Mar 24 12:33:37 PM PDT 24 221538006 ps
T799 /workspace/coverage/cover_reg_top/19.gpio_intr_test.971470035 Mar 24 12:33:51 PM PDT 24 Mar 24 12:33:51 PM PDT 24 11315339 ps
T800 /workspace/coverage/cover_reg_top/39.gpio_intr_test.3452747814 Mar 24 12:33:50 PM PDT 24 Mar 24 12:33:50 PM PDT 24 17782620 ps
T801 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3929843299 Mar 24 12:34:10 PM PDT 24 Mar 24 12:34:10 PM PDT 24 57695134 ps
T802 /workspace/coverage/cover_reg_top/14.gpio_intr_test.942131033 Mar 24 12:33:47 PM PDT 24 Mar 24 12:33:48 PM PDT 24 123654019 ps
T803 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1054430149 Mar 24 12:33:56 PM PDT 24 Mar 24 12:33:58 PM PDT 24 139001224 ps
T804 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.58174443 Mar 24 12:33:36 PM PDT 24 Mar 24 12:33:38 PM PDT 24 124260128 ps
T805 /workspace/coverage/cover_reg_top/24.gpio_intr_test.4124626764 Mar 24 12:33:48 PM PDT 24 Mar 24 12:33:49 PM PDT 24 14257208 ps
T105 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2514966660 Mar 24 12:33:44 PM PDT 24 Mar 24 12:33:46 PM PDT 24 173735484 ps
T806 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.690414129 Mar 24 12:33:35 PM PDT 24 Mar 24 12:33:37 PM PDT 24 32171140 ps
T807 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3105829112 Mar 24 12:33:40 PM PDT 24 Mar 24 12:33:42 PM PDT 24 189102652 ps
T808 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2308280748 Mar 24 12:33:55 PM PDT 24 Mar 24 12:33:56 PM PDT 24 60413564 ps
T809 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2678026972 Mar 24 12:33:37 PM PDT 24 Mar 24 12:33:39 PM PDT 24 18473592 ps
T810 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3221461327 Mar 24 12:34:12 PM PDT 24 Mar 24 12:34:13 PM PDT 24 27435028 ps
T811 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1066231290 Mar 24 12:35:05 PM PDT 24 Mar 24 12:35:06 PM PDT 24 24448730 ps
T812 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3678690929 Mar 24 12:33:41 PM PDT 24 Mar 24 12:33:44 PM PDT 24 129501074 ps
T813 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1625364237 Mar 24 12:35:10 PM PDT 24 Mar 24 12:35:10 PM PDT 24 101823974 ps
T814 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2657534456 Mar 24 12:33:39 PM PDT 24 Mar 24 12:33:41 PM PDT 24 12629149 ps
T815 /workspace/coverage/cover_reg_top/10.gpio_intr_test.4192133863 Mar 24 12:33:37 PM PDT 24 Mar 24 12:33:38 PM PDT 24 10877662 ps
T816 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2874768085 Mar 24 12:33:49 PM PDT 24 Mar 24 12:33:51 PM PDT 24 149619648 ps
T817 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1674549599 Mar 24 12:33:43 PM PDT 24 Mar 24 12:33:44 PM PDT 24 14518891 ps
T818 /workspace/coverage/cover_reg_top/49.gpio_intr_test.1623826123 Mar 24 12:33:49 PM PDT 24 Mar 24 12:33:49 PM PDT 24 39556791 ps
T819 /workspace/coverage/cover_reg_top/43.gpio_intr_test.1476588888 Mar 24 12:33:45 PM PDT 24 Mar 24 12:33:46 PM PDT 24 51952732 ps
T820 /workspace/coverage/cover_reg_top/8.gpio_intr_test.2042515469 Mar 24 12:33:56 PM PDT 24 Mar 24 12:33:57 PM PDT 24 14240351 ps
T821 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1419577531 Mar 24 12:33:51 PM PDT 24 Mar 24 12:33:52 PM PDT 24 14037335 ps
T822 /workspace/coverage/cover_reg_top/30.gpio_intr_test.3625904757 Mar 24 12:34:17 PM PDT 24 Mar 24 12:34:18 PM PDT 24 42238715 ps
T823 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1586967440 Mar 24 12:33:30 PM PDT 24 Mar 24 12:33:32 PM PDT 24 293627523 ps
T824 /workspace/coverage/cover_reg_top/47.gpio_intr_test.3719407382 Mar 24 12:33:55 PM PDT 24 Mar 24 12:33:56 PM PDT 24 37206858 ps
T825 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1901164909 Mar 24 12:33:39 PM PDT 24 Mar 24 12:33:41 PM PDT 24 12630021 ps
T826 /workspace/coverage/cover_reg_top/36.gpio_intr_test.4171512194 Mar 24 12:33:48 PM PDT 24 Mar 24 12:33:48 PM PDT 24 27287892 ps
T827 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.318042697 Mar 24 12:34:18 PM PDT 24 Mar 24 12:34:19 PM PDT 24 17884418 ps
T828 /workspace/coverage/cover_reg_top/37.gpio_intr_test.864467794 Mar 24 12:33:43 PM PDT 24 Mar 24 12:33:44 PM PDT 24 30924909 ps
T829 /workspace/coverage/cover_reg_top/12.gpio_intr_test.2461364021 Mar 24 12:33:49 PM PDT 24 Mar 24 12:33:50 PM PDT 24 63526202 ps
T830 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.467958129 Mar 24 12:33:30 PM PDT 24 Mar 24 12:33:31 PM PDT 24 35406732 ps
T831 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2737436431 Mar 24 12:33:54 PM PDT 24 Mar 24 12:33:55 PM PDT 24 111269302 ps
T832 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3385053053 Mar 24 12:33:52 PM PDT 24 Mar 24 12:33:54 PM PDT 24 43633146 ps
T833 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2566937271 Mar 24 12:34:36 PM PDT 24 Mar 24 12:34:38 PM PDT 24 392516847 ps
T834 /workspace/coverage/cover_reg_top/16.gpio_intr_test.2251262598 Mar 24 12:33:51 PM PDT 24 Mar 24 12:33:51 PM PDT 24 20053275 ps
T84 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2218099909 Mar 24 12:33:42 PM PDT 24 Mar 24 12:33:44 PM PDT 24 50955214 ps
T835 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2814538168 Mar 24 12:33:25 PM PDT 24 Mar 24 12:33:26 PM PDT 24 19225830 ps
T87 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4046469422 Mar 24 12:33:57 PM PDT 24 Mar 24 12:33:58 PM PDT 24 93915410 ps
T836 /workspace/coverage/cover_reg_top/13.gpio_intr_test.139901716 Mar 24 12:33:38 PM PDT 24 Mar 24 12:33:39 PM PDT 24 17801186 ps
T837 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.938255384 Mar 24 12:33:26 PM PDT 24 Mar 24 12:33:28 PM PDT 24 29440234 ps
T838 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1310681239 Mar 24 12:33:40 PM PDT 24 Mar 24 12:33:44 PM PDT 24 135285817 ps
T839 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2480354199 Mar 24 12:33:39 PM PDT 24 Mar 24 12:33:41 PM PDT 24 70361172 ps
T840 /workspace/coverage/cover_reg_top/38.gpio_intr_test.1199554256 Mar 24 12:33:34 PM PDT 24 Mar 24 12:33:35 PM PDT 24 14105418 ps
T841 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.563276021 Mar 24 12:33:39 PM PDT 24 Mar 24 12:33:40 PM PDT 24 18024303 ps
T842 /workspace/coverage/cover_reg_top/0.gpio_intr_test.658804006 Mar 24 12:33:53 PM PDT 24 Mar 24 12:33:54 PM PDT 24 76079804 ps
T49 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1636127342 Mar 24 12:33:21 PM PDT 24 Mar 24 12:33:23 PM PDT 24 165304332 ps
T843 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.10661537 Mar 24 12:33:50 PM PDT 24 Mar 24 12:33:51 PM PDT 24 35771749 ps
T844 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2323378067 Mar 24 12:33:52 PM PDT 24 Mar 24 12:33:54 PM PDT 24 70516279 ps
T845 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1163216012 Mar 24 12:33:51 PM PDT 24 Mar 24 12:33:52 PM PDT 24 12464192 ps
T846 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3453906388 Mar 24 12:33:55 PM PDT 24 Mar 24 12:33:56 PM PDT 24 21282905 ps
T847 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.25293521 Mar 24 12:33:35 PM PDT 24 Mar 24 12:33:36 PM PDT 24 171102274 ps
T848 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2495428205 Mar 24 12:34:06 PM PDT 24 Mar 24 12:34:07 PM PDT 24 92249239 ps
T849 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.603160554 Mar 24 12:33:31 PM PDT 24 Mar 24 12:33:32 PM PDT 24 38928652 ps
T850 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1343134199 Mar 24 12:33:13 PM PDT 24 Mar 24 12:33:15 PM PDT 24 624801243 ps
T851 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1054623337 Mar 24 12:33:20 PM PDT 24 Mar 24 12:33:23 PM PDT 24 71495538 ps
T852 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2552410783 Mar 24 12:33:03 PM PDT 24 Mar 24 12:33:04 PM PDT 24 53842796 ps
T853 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1435395091 Mar 24 12:33:04 PM PDT 24 Mar 24 12:33:05 PM PDT 24 64596638 ps
T854 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4268283552 Mar 24 12:33:33 PM PDT 24 Mar 24 12:33:34 PM PDT 24 66375517 ps
T855 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3122697890 Mar 24 12:33:23 PM PDT 24 Mar 24 12:33:25 PM PDT 24 86539112 ps
T856 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3808159048 Mar 24 12:33:01 PM PDT 24 Mar 24 12:33:04 PM PDT 24 72095834 ps
T857 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3267254956 Mar 24 12:33:25 PM PDT 24 Mar 24 12:33:26 PM PDT 24 44152812 ps
T858 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4257546406 Mar 24 12:33:16 PM PDT 24 Mar 24 12:33:17 PM PDT 24 30520983 ps
T859 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1518614714 Mar 24 12:33:12 PM PDT 24 Mar 24 12:33:13 PM PDT 24 163414012 ps
T860 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3714096915 Mar 24 12:33:19 PM PDT 24 Mar 24 12:33:23 PM PDT 24 68065902 ps
T861 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1550465243 Mar 24 12:33:07 PM PDT 24 Mar 24 12:33:10 PM PDT 24 249279739 ps
T862 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.4189760723 Mar 24 12:33:44 PM PDT 24 Mar 24 12:33:46 PM PDT 24 287610178 ps
T863 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1476097151 Mar 24 12:33:13 PM PDT 24 Mar 24 12:33:14 PM PDT 24 537409065 ps
T864 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3122183673 Mar 24 12:33:03 PM PDT 24 Mar 24 12:33:04 PM PDT 24 248674908 ps
T865 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.719457167 Mar 24 12:33:35 PM PDT 24 Mar 24 12:33:37 PM PDT 24 181989705 ps
T866 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1358708293 Mar 24 12:33:11 PM PDT 24 Mar 24 12:33:12 PM PDT 24 66219700 ps
T867 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2906890409 Mar 24 12:33:19 PM PDT 24 Mar 24 12:33:22 PM PDT 24 37527218 ps
T868 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2952763117 Mar 24 12:33:07 PM PDT 24 Mar 24 12:33:10 PM PDT 24 23709343 ps
T869 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.144960310 Mar 24 12:33:03 PM PDT 24 Mar 24 12:33:04 PM PDT 24 320881467 ps
T870 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1691534119 Mar 24 12:33:17 PM PDT 24 Mar 24 12:33:18 PM PDT 24 87893828 ps
T871 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.364297178 Mar 24 12:33:04 PM PDT 24 Mar 24 12:33:06 PM PDT 24 388935565 ps
T872 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2365363889 Mar 24 12:33:00 PM PDT 24 Mar 24 12:33:03 PM PDT 24 48472944 ps
T873 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3783912677 Mar 24 12:33:03 PM PDT 24 Mar 24 12:33:04 PM PDT 24 149987027 ps
T874 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2830629982 Mar 24 12:33:11 PM PDT 24 Mar 24 12:33:13 PM PDT 24 69049100 ps
T875 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3586087562 Mar 24 12:33:19 PM PDT 24 Mar 24 12:33:23 PM PDT 24 92754369 ps
T876 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4063232331 Mar 24 12:33:20 PM PDT 24 Mar 24 12:33:23 PM PDT 24 197691412 ps
T877 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2978503254 Mar 24 12:33:23 PM PDT 24 Mar 24 12:33:25 PM PDT 24 204045574 ps
T878 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.150026765 Mar 24 12:33:31 PM PDT 24 Mar 24 12:33:37 PM PDT 24 141231938 ps
T879 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.319015180 Mar 24 12:33:12 PM PDT 24 Mar 24 12:33:13 PM PDT 24 518797332 ps
T880 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3404168692 Mar 24 12:33:06 PM PDT 24 Mar 24 12:33:08 PM PDT 24 138452022 ps
T881 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3892089804 Mar 24 12:33:07 PM PDT 24 Mar 24 12:33:10 PM PDT 24 98164968 ps
T882 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1154775662 Mar 24 12:33:07 PM PDT 24 Mar 24 12:33:10 PM PDT 24 418404688 ps
T883 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1762839979 Mar 24 12:33:22 PM PDT 24 Mar 24 12:33:23 PM PDT 24 56503614 ps
T884 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1140413762 Mar 24 12:33:11 PM PDT 24 Mar 24 12:33:12 PM PDT 24 45893580 ps
T885 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.367547533 Mar 24 12:33:28 PM PDT 24 Mar 24 12:33:29 PM PDT 24 229759777 ps
T886 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1247346138 Mar 24 12:33:27 PM PDT 24 Mar 24 12:33:29 PM PDT 24 109009934 ps
T887 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.735548454 Mar 24 12:33:16 PM PDT 24 Mar 24 12:33:17 PM PDT 24 245646805 ps
T888 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.988579385 Mar 24 12:33:10 PM PDT 24 Mar 24 12:33:11 PM PDT 24 229852367 ps
T889 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3278100571 Mar 24 12:33:11 PM PDT 24 Mar 24 12:33:12 PM PDT 24 56538346 ps
T890 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1708704148 Mar 24 12:33:21 PM PDT 24 Mar 24 12:33:23 PM PDT 24 20930327 ps
T891 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1808697766 Mar 24 12:33:06 PM PDT 24 Mar 24 12:33:07 PM PDT 24 36823452 ps
T892 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2189956997 Mar 24 12:33:15 PM PDT 24 Mar 24 12:33:16 PM PDT 24 42134289 ps
T893 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3071500808 Mar 24 12:33:09 PM PDT 24 Mar 24 12:33:10 PM PDT 24 371488706 ps
T894 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3336005704 Mar 24 12:33:15 PM PDT 24 Mar 24 12:33:16 PM PDT 24 132199455 ps
T895 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3659620410 Mar 24 12:33:13 PM PDT 24 Mar 24 12:33:14 PM PDT 24 422528596 ps
T896 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.312911679 Mar 24 12:33:11 PM PDT 24 Mar 24 12:33:12 PM PDT 24 178270949 ps
T897 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1707304384 Mar 24 12:33:19 PM PDT 24 Mar 24 12:33:23 PM PDT 24 215900721 ps
T898 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2385087465 Mar 24 12:33:08 PM PDT 24 Mar 24 12:33:10 PM PDT 24 217104480 ps
T899 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1010273568 Mar 24 12:33:15 PM PDT 24 Mar 24 12:33:17 PM PDT 24 38754947 ps
T900 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1996630465 Mar 24 12:33:13 PM PDT 24 Mar 24 12:33:15 PM PDT 24 37015907 ps
T901 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2941354592 Mar 24 12:33:06 PM PDT 24 Mar 24 12:33:07 PM PDT 24 135777097 ps
T902 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.784875310 Mar 24 12:33:12 PM PDT 24 Mar 24 12:33:15 PM PDT 24 205311785 ps
T903 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.533292107 Mar 24 12:33:16 PM PDT 24 Mar 24 12:33:17 PM PDT 24 58635394 ps
T904 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1793351042 Mar 24 12:33:06 PM PDT 24 Mar 24 12:33:07 PM PDT 24 44408745 ps
T905 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2824699890 Mar 24 12:33:16 PM PDT 24 Mar 24 12:33:17 PM PDT 24 66785427 ps
T906 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3066720166 Mar 24 12:33:07 PM PDT 24 Mar 24 12:33:08 PM PDT 24 66034368 ps
T907 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3974762737 Mar 24 12:33:22 PM PDT 24 Mar 24 12:33:23 PM PDT 24 129685070 ps
T908 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4156597814 Mar 24 12:33:11 PM PDT 24 Mar 24 12:33:12 PM PDT 24 91179510 ps
T909 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.130460483 Mar 24 12:33:13 PM PDT 24 Mar 24 12:33:14 PM PDT 24 82959456 ps
T910 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4246211703 Mar 24 12:33:06 PM PDT 24 Mar 24 12:33:07 PM PDT 24 41757478 ps
T911 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3766636732 Mar 24 12:33:13 PM PDT 24 Mar 24 12:33:14 PM PDT 24 91968776 ps
T912 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1025031079 Mar 24 12:33:21 PM PDT 24 Mar 24 12:33:23 PM PDT 24 306249015 ps
T913 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1056747786 Mar 24 12:33:20 PM PDT 24 Mar 24 12:33:23 PM PDT 24 132196129 ps
T914 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4152168661 Mar 24 12:33:28 PM PDT 24 Mar 24 12:33:29 PM PDT 24 127993492 ps
T915 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2651369950 Mar 24 12:32:55 PM PDT 24 Mar 24 12:32:56 PM PDT 24 40683234 ps
T916 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.353357485 Mar 24 12:33:08 PM PDT 24 Mar 24 12:33:10 PM PDT 24 46127987 ps
T917 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1695702372 Mar 24 12:33:22 PM PDT 24 Mar 24 12:33:23 PM PDT 24 206334671 ps
T918 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1229665412 Mar 24 12:33:24 PM PDT 24 Mar 24 12:33:26 PM PDT 24 101406919 ps
T919 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3297113206 Mar 24 12:33:21 PM PDT 24 Mar 24 12:33:23 PM PDT 24 342323339 ps
T920 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3367453527 Mar 24 12:33:17 PM PDT 24 Mar 24 12:33:19 PM PDT 24 401019850 ps
T921 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3596225567 Mar 24 12:33:35 PM PDT 24 Mar 24 12:33:36 PM PDT 24 57733095 ps
T922 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.872896548 Mar 24 12:33:27 PM PDT 24 Mar 24 12:33:29 PM PDT 24 114082837 ps
T923 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.4096451067 Mar 24 12:33:05 PM PDT 24 Mar 24 12:33:07 PM PDT 24 239342912 ps
T924 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2607642386 Mar 24 12:32:59 PM PDT 24 Mar 24 12:33:01 PM PDT 24 46273507 ps
T925 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2069432124 Mar 24 12:33:10 PM PDT 24 Mar 24 12:33:12 PM PDT 24 159458390 ps
T926 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1116445512 Mar 24 12:33:23 PM PDT 24 Mar 24 12:33:25 PM PDT 24 67205490 ps
T927 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2497792208 Mar 24 12:33:17 PM PDT 24 Mar 24 12:33:18 PM PDT 24 137435416 ps
T928 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4054507603 Mar 24 12:33:07 PM PDT 24 Mar 24 12:33:08 PM PDT 24 324032084 ps
T929 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2415799936 Mar 24 12:33:10 PM PDT 24 Mar 24 12:33:11 PM PDT 24 146389677 ps
T930 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4210694688 Mar 24 12:33:19 PM PDT 24 Mar 24 12:33:22 PM PDT 24 99029838 ps
T931 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3560983879 Mar 24 12:33:23 PM PDT 24 Mar 24 12:33:25 PM PDT 24 37503951 ps
T932 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.131754169 Mar 24 12:33:13 PM PDT 24 Mar 24 12:33:15 PM PDT 24 609918744 ps
T933 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.8620478 Mar 24 12:33:07 PM PDT 24 Mar 24 12:33:08 PM PDT 24 48724077 ps
T934 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2699940793 Mar 24 12:33:07 PM PDT 24 Mar 24 12:33:10 PM PDT 24 58435186 ps
T935 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2164464652 Mar 24 12:33:10 PM PDT 24 Mar 24 12:33:11 PM PDT 24 208397886 ps
T936 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4139480366 Mar 24 12:33:20 PM PDT 24 Mar 24 12:33:23 PM PDT 24 100185235 ps
T937 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2588362628 Mar 24 12:33:12 PM PDT 24 Mar 24 12:33:15 PM PDT 24 138560974 ps
T938 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.568264697 Mar 24 12:33:14 PM PDT 24 Mar 24 12:33:15 PM PDT 24 212979361 ps
T939 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3807480693 Mar 24 12:33:28 PM PDT 24 Mar 24 12:33:30 PM PDT 24 293946144 ps
T940 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4034789737 Mar 24 12:33:13 PM PDT 24 Mar 24 12:33:14 PM PDT 24 259782037 ps
T941 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.526491945 Mar 24 12:33:17 PM PDT 24 Mar 24 12:33:19 PM PDT 24 254116365 ps
T942 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2577387753 Mar 24 12:33:07 PM PDT 24 Mar 24 12:33:10 PM PDT 24 47255920 ps
T943 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1331123023 Mar 24 12:33:18 PM PDT 24 Mar 24 12:33:19 PM PDT 24 439374315 ps
T944 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1071154004 Mar 24 12:33:10 PM PDT 24 Mar 24 12:33:12 PM PDT 24 322693391 ps
T945 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1802918747 Mar 24 12:33:05 PM PDT 24 Mar 24 12:33:07 PM PDT 24 245828506 ps
T946 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4049713916 Mar 24 12:33:10 PM PDT 24 Mar 24 12:33:12 PM PDT 24 201004719 ps
T947 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.4204814889 Mar 24 12:33:15 PM PDT 24 Mar 24 12:33:17 PM PDT 24 248735884 ps
T948 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.366749040 Mar 24 12:33:08 PM PDT 24 Mar 24 12:33:10 PM PDT 24 211440186 ps
T949 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2085183813 Mar 24 12:33:02 PM PDT 24 Mar 24 12:33:04 PM PDT 24 1746708945 ps

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3577993516
Short name T23
Test name
Test status
Simulation time 143979638391 ps
CPU time 1010.15 seconds
Started Mar 24 12:47:37 PM PDT 24
Finished Mar 24 01:04:28 PM PDT 24
Peak memory 198284 kb
Host smart-041bb635-1beb-42f7-95d9-69d4d27494d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3577993516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3577993516
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2578662894
Short name T32
Test name
Test status
Simulation time 199520017 ps
CPU time 1.92 seconds
Started Mar 24 12:46:09 PM PDT 24
Finished Mar 24 12:46:11 PM PDT 24
Peak memory 198068 kb
Host smart-4b1c1f3f-3326-498f-80e1-6bb18ca2d702
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578662894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2578662894
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1781351862
Short name T38
Test name
Test status
Simulation time 160725232 ps
CPU time 0.94 seconds
Started Mar 24 12:45:20 PM PDT 24
Finished Mar 24 12:45:22 PM PDT 24
Peak memory 214980 kb
Host smart-eb8847ec-1427-4960-b7df-f0feb5aab787
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781351862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1781351862
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/47.gpio_full_random.3783335815
Short name T20
Test name
Test status
Simulation time 118884357 ps
CPU time 0.87 seconds
Started Mar 24 12:47:30 PM PDT 24
Finished Mar 24 12:47:32 PM PDT 24
Peak memory 196184 kb
Host smart-2732dbb5-65f2-4549-9fef-cbedbcb65420
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783335815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3783335815
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.116314943
Short name T78
Test name
Test status
Simulation time 12433266 ps
CPU time 0.61 seconds
Started Mar 24 12:33:40 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 195308 kb
Host smart-1e4a4949-dea9-45a5-877d-dcf07e3e2e51
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116314943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.116314943
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2835677944
Short name T46
Test name
Test status
Simulation time 124980408 ps
CPU time 1.45 seconds
Started Mar 24 12:34:36 PM PDT 24
Finished Mar 24 12:34:38 PM PDT 24
Peak memory 196280 kb
Host smart-d11b9488-33da-4ef5-83aa-b4edd921c07c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835677944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2835677944
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3186864014
Short name T68
Test name
Test status
Simulation time 16280417 ps
CPU time 0.61 seconds
Started Mar 24 12:33:56 PM PDT 24
Finished Mar 24 12:33:57 PM PDT 24
Peak memory 194684 kb
Host smart-735b6521-62d2-476a-bde1-1a1eb3c7e39e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186864014 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3186864014
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.gpio_stress_all.216725655
Short name T9
Test name
Test status
Simulation time 43787442686 ps
CPU time 32.94 seconds
Started Mar 24 12:45:04 PM PDT 24
Finished Mar 24 12:45:38 PM PDT 24
Peak memory 198080 kb
Host smart-0be1fc17-aaa7-4ccb-acbc-205a6b803d39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216725655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.216725655
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3168241497
Short name T182
Test name
Test status
Simulation time 34335723 ps
CPU time 0.62 seconds
Started Mar 24 12:45:51 PM PDT 24
Finished Mar 24 12:45:51 PM PDT 24
Peak memory 194632 kb
Host smart-73ff4149-43cf-4558-ac40-d50d293598aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168241497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3168241497
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2034382507
Short name T47
Test name
Test status
Simulation time 290153751 ps
CPU time 1.11 seconds
Started Mar 24 12:33:47 PM PDT 24
Finished Mar 24 12:33:49 PM PDT 24
Peak memory 197880 kb
Host smart-541fdded-21b9-46e9-8cfe-3820aa31841a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034382507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2034382507
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2566937271
Short name T833
Test name
Test status
Simulation time 392516847 ps
CPU time 1.44 seconds
Started Mar 24 12:34:36 PM PDT 24
Finished Mar 24 12:34:38 PM PDT 24
Peak memory 196668 kb
Host smart-17237355-5a17-4801-aae9-fa0c679b08c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566937271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2566937271
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2854683043
Short name T79
Test name
Test status
Simulation time 40371169 ps
CPU time 0.83 seconds
Started Mar 24 12:33:45 PM PDT 24
Finished Mar 24 12:33:51 PM PDT 24
Peak memory 195864 kb
Host smart-bd5e1653-e0e0-4c67-b060-52980904257c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854683043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2854683043
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3678690929
Short name T812
Test name
Test status
Simulation time 129501074 ps
CPU time 1.35 seconds
Started Mar 24 12:33:41 PM PDT 24
Finished Mar 24 12:33:44 PM PDT 24
Peak memory 196196 kb
Host smart-ab8cc51d-166d-4da9-96cc-b7ea0999c7b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678690929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3678690929
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2485080972
Short name T74
Test name
Test status
Simulation time 24303722 ps
CPU time 0.61 seconds
Started Mar 24 12:33:41 PM PDT 24
Finished Mar 24 12:33:43 PM PDT 24
Peak memory 194428 kb
Host smart-279268cb-f1f7-4288-a6c8-07d1f6db310b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485080972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2485080972
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2711649702
Short name T759
Test name
Test status
Simulation time 194869865 ps
CPU time 1.64 seconds
Started Mar 24 12:34:08 PM PDT 24
Finished Mar 24 12:34:10 PM PDT 24
Peak memory 198004 kb
Host smart-acbf5fdb-f8bd-42d0-99a3-dffc00467530
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711649702 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2711649702
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.658804006
Short name T842
Test name
Test status
Simulation time 76079804 ps
CPU time 0.6 seconds
Started Mar 24 12:33:53 PM PDT 24
Finished Mar 24 12:33:54 PM PDT 24
Peak memory 194148 kb
Host smart-97f8657a-fc83-4b98-a25f-a78b4b7e2222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658804006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.658804006
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3453906388
Short name T846
Test name
Test status
Simulation time 21282905 ps
CPU time 0.69 seconds
Started Mar 24 12:33:55 PM PDT 24
Finished Mar 24 12:33:56 PM PDT 24
Peak memory 194860 kb
Host smart-823c80e2-c564-4383-924b-80b9239fdca8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453906388 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3453906388
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1904122155
Short name T782
Test name
Test status
Simulation time 361950005 ps
CPU time 1.82 seconds
Started Mar 24 12:33:36 PM PDT 24
Finished Mar 24 12:33:38 PM PDT 24
Peak memory 197868 kb
Host smart-b063b2a0-6412-4cbb-9e1c-f0660ca9c60a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904122155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1904122155
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1201911309
Short name T35
Test name
Test status
Simulation time 163994776 ps
CPU time 0.83 seconds
Started Mar 24 12:33:35 PM PDT 24
Finished Mar 24 12:33:36 PM PDT 24
Peak memory 197696 kb
Host smart-2e1c36c3-4fee-45f3-9e65-6d308dc18af6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201911309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1201911309
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3654267796
Short name T75
Test name
Test status
Simulation time 98296889 ps
CPU time 0.71 seconds
Started Mar 24 12:33:23 PM PDT 24
Finished Mar 24 12:33:25 PM PDT 24
Peak memory 195576 kb
Host smart-c595261c-9f5e-435c-8305-0fdbfb9003b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654267796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3654267796
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3401704761
Short name T796
Test name
Test status
Simulation time 173895516 ps
CPU time 2.32 seconds
Started Mar 24 12:33:41 PM PDT 24
Finished Mar 24 12:33:44 PM PDT 24
Peak memory 196528 kb
Host smart-76371ad2-4a97-4089-8f56-f2c1bbfd2bc3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401704761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3401704761
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1561241568
Short name T758
Test name
Test status
Simulation time 102263525 ps
CPU time 0.65 seconds
Started Mar 24 12:33:23 PM PDT 24
Finished Mar 24 12:33:24 PM PDT 24
Peak memory 194776 kb
Host smart-1cfacf15-f71c-4d6f-a1d3-ac2461aa2975
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561241568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1561241568
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2496223102
Short name T798
Test name
Test status
Simulation time 221538006 ps
CPU time 0.82 seconds
Started Mar 24 12:33:36 PM PDT 24
Finished Mar 24 12:33:37 PM PDT 24
Peak memory 197816 kb
Host smart-4b231c00-abc4-4847-b650-812135e7757b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496223102 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2496223102
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1559528885
Short name T81
Test name
Test status
Simulation time 54950543 ps
CPU time 0.61 seconds
Started Mar 24 12:33:13 PM PDT 24
Finished Mar 24 12:33:14 PM PDT 24
Peak memory 195312 kb
Host smart-797e370f-bee9-47c0-943d-bbc9d6142a5b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559528885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1559528885
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3105829112
Short name T807
Test name
Test status
Simulation time 189102652 ps
CPU time 0.63 seconds
Started Mar 24 12:33:40 PM PDT 24
Finished Mar 24 12:33:42 PM PDT 24
Peak memory 193540 kb
Host smart-7ceafbe7-a58b-400b-8c5a-9073ea10d5f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105829112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3105829112
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1540343050
Short name T91
Test name
Test status
Simulation time 34963912 ps
CPU time 0.84 seconds
Started Mar 24 12:33:34 PM PDT 24
Finished Mar 24 12:33:35 PM PDT 24
Peak memory 196824 kb
Host smart-ef587917-fb5d-4d63-8e7b-a4584044fc6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540343050 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1540343050
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3398072238
Short name T739
Test name
Test status
Simulation time 180500164 ps
CPU time 2.97 seconds
Started Mar 24 12:33:41 PM PDT 24
Finished Mar 24 12:33:45 PM PDT 24
Peak memory 197840 kb
Host smart-e1068cb5-8223-4822-b234-44ec5f627a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398072238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3398072238
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1636127342
Short name T49
Test name
Test status
Simulation time 165304332 ps
CPU time 0.85 seconds
Started Mar 24 12:33:21 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 197056 kb
Host smart-c6f09251-440f-4330-967d-9b1f9019c115
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636127342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1636127342
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.563276021
Short name T841
Test name
Test status
Simulation time 18024303 ps
CPU time 0.74 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:40 PM PDT 24
Peak memory 197888 kb
Host smart-184b9a95-c399-4475-9dd2-1b480b0f0edf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563276021 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.563276021
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3844281855
Short name T791
Test name
Test status
Simulation time 47194629 ps
CPU time 0.59 seconds
Started Mar 24 12:33:46 PM PDT 24
Finished Mar 24 12:33:47 PM PDT 24
Peak memory 194284 kb
Host smart-d8640b93-4032-405d-ba1f-37b89f194b3e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844281855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3844281855
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.4192133863
Short name T815
Test name
Test status
Simulation time 10877662 ps
CPU time 0.59 seconds
Started Mar 24 12:33:37 PM PDT 24
Finished Mar 24 12:33:38 PM PDT 24
Peak memory 193528 kb
Host smart-46267805-d106-417c-b103-72bb8e9584d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192133863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.4192133863
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.467958129
Short name T830
Test name
Test status
Simulation time 35406732 ps
CPU time 0.86 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:31 PM PDT 24
Peak memory 196060 kb
Host smart-7d15b88f-6770-4b05-92ed-36ca4442c991
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467958129 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.467958129
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.690414129
Short name T806
Test name
Test status
Simulation time 32171140 ps
CPU time 0.97 seconds
Started Mar 24 12:33:35 PM PDT 24
Finished Mar 24 12:33:37 PM PDT 24
Peak memory 197732 kb
Host smart-71f3dcfa-1246-4e9c-b850-b0e0443cb67d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690414129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.690414129
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3047454950
Short name T45
Test name
Test status
Simulation time 162399801 ps
CPU time 1.14 seconds
Started Mar 24 12:33:56 PM PDT 24
Finished Mar 24 12:33:58 PM PDT 24
Peak memory 197884 kb
Host smart-651b27bc-c3ae-4bd1-b43f-d92e0d9572ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047454950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3047454950
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1320255830
Short name T736
Test name
Test status
Simulation time 31864204 ps
CPU time 1.43 seconds
Started Mar 24 12:33:32 PM PDT 24
Finished Mar 24 12:33:33 PM PDT 24
Peak memory 197944 kb
Host smart-588345c9-3705-4266-b832-c1568b912fea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320255830 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1320255830
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2218099909
Short name T84
Test name
Test status
Simulation time 50955214 ps
CPU time 0.61 seconds
Started Mar 24 12:33:42 PM PDT 24
Finished Mar 24 12:33:44 PM PDT 24
Peak memory 194968 kb
Host smart-82b0a72f-2b81-44ff-84c2-23c24c93d406
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218099909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2218099909
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1674549599
Short name T817
Test name
Test status
Simulation time 14518891 ps
CPU time 0.56 seconds
Started Mar 24 12:33:43 PM PDT 24
Finished Mar 24 12:33:44 PM PDT 24
Peak memory 193484 kb
Host smart-f54fbe86-995e-4fe3-bff1-3e20f9f5f01b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674549599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1674549599
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.35091780
Short name T89
Test name
Test status
Simulation time 18524256 ps
CPU time 0.63 seconds
Started Mar 24 12:33:32 PM PDT 24
Finished Mar 24 12:33:39 PM PDT 24
Peak memory 195172 kb
Host smart-a5ee7532-03f3-4947-8fb8-6b0ea69385c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35091780 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.gpio_same_csr_outstanding.35091780
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2323378067
Short name T844
Test name
Test status
Simulation time 70516279 ps
CPU time 1.63 seconds
Started Mar 24 12:33:52 PM PDT 24
Finished Mar 24 12:33:54 PM PDT 24
Peak memory 197860 kb
Host smart-e4c9ad65-7de3-4b8d-89d3-f31c1a8d7be0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323378067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2323378067
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.746270328
Short name T104
Test name
Test status
Simulation time 41745191 ps
CPU time 0.83 seconds
Started Mar 24 12:33:36 PM PDT 24
Finished Mar 24 12:33:38 PM PDT 24
Peak memory 196784 kb
Host smart-81200bbc-f941-4c47-9425-b71e3312a9ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746270328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.746270328
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1701053248
Short name T748
Test name
Test status
Simulation time 96892299 ps
CPU time 0.66 seconds
Started Mar 24 12:34:03 PM PDT 24
Finished Mar 24 12:34:04 PM PDT 24
Peak memory 197164 kb
Host smart-ea945424-12b1-4a11-adf1-027a07e15a7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701053248 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1701053248
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1901164909
Short name T825
Test name
Test status
Simulation time 12630021 ps
CPU time 0.62 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 194472 kb
Host smart-f4e95c31-9d2f-440e-8177-504563c5e8a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901164909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1901164909
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2461364021
Short name T829
Test name
Test status
Simulation time 63526202 ps
CPU time 0.59 seconds
Started Mar 24 12:33:49 PM PDT 24
Finished Mar 24 12:33:50 PM PDT 24
Peak memory 193608 kb
Host smart-f32df2b8-ddca-4ed4-b73d-65ad1518d826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461364021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2461364021
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1625364237
Short name T813
Test name
Test status
Simulation time 101823974 ps
CPU time 0.62 seconds
Started Mar 24 12:35:10 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 195432 kb
Host smart-1150036e-5e48-44e1-8608-077d1752fba9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625364237 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1625364237
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1310681239
Short name T838
Test name
Test status
Simulation time 135285817 ps
CPU time 2.85 seconds
Started Mar 24 12:33:40 PM PDT 24
Finished Mar 24 12:33:44 PM PDT 24
Peak memory 197948 kb
Host smart-689f36a9-ae6c-4c35-8309-f342799e7681
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310681239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1310681239
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.485382491
Short name T776
Test name
Test status
Simulation time 131063074 ps
CPU time 0.85 seconds
Started Mar 24 12:35:13 PM PDT 24
Finished Mar 24 12:35:14 PM PDT 24
Peak memory 197772 kb
Host smart-14adac75-302d-4fb1-8644-f60943c387d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485382491 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.485382491
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.718452520
Short name T754
Test name
Test status
Simulation time 13831718 ps
CPU time 0.61 seconds
Started Mar 24 12:33:42 PM PDT 24
Finished Mar 24 12:33:43 PM PDT 24
Peak memory 195372 kb
Host smart-a83af052-f8a7-4a71-a3de-99039d5fe364
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718452520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.718452520
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.139901716
Short name T836
Test name
Test status
Simulation time 17801186 ps
CPU time 0.61 seconds
Started Mar 24 12:33:38 PM PDT 24
Finished Mar 24 12:33:39 PM PDT 24
Peak memory 194092 kb
Host smart-0fa2913c-8c92-400b-9cf0-37248d91d044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139901716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.139901716
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.648979303
Short name T767
Test name
Test status
Simulation time 39005510 ps
CPU time 0.87 seconds
Started Mar 24 12:33:49 PM PDT 24
Finished Mar 24 12:33:50 PM PDT 24
Peak memory 197320 kb
Host smart-0d2eec14-7634-4819-8bed-b7a88915ce33
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648979303 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.648979303
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3385053053
Short name T832
Test name
Test status
Simulation time 43633146 ps
CPU time 1.38 seconds
Started Mar 24 12:33:52 PM PDT 24
Finished Mar 24 12:33:54 PM PDT 24
Peak memory 197912 kb
Host smart-5941005b-6e89-4677-afea-e77a16ed5823
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385053053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3385053053
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2495428205
Short name T848
Test name
Test status
Simulation time 92249239 ps
CPU time 1.15 seconds
Started Mar 24 12:34:06 PM PDT 24
Finished Mar 24 12:34:07 PM PDT 24
Peak memory 197880 kb
Host smart-cb835e94-53c5-4de8-b9b6-fa9e460fe954
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495428205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2495428205
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2395820868
Short name T769
Test name
Test status
Simulation time 30728717 ps
CPU time 0.86 seconds
Started Mar 24 12:33:45 PM PDT 24
Finished Mar 24 12:33:46 PM PDT 24
Peak memory 197828 kb
Host smart-6c05e497-5d50-4f95-b488-0eb6b6162269
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395820868 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2395820868
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2499514625
Short name T749
Test name
Test status
Simulation time 123850670 ps
CPU time 0.56 seconds
Started Mar 24 12:34:09 PM PDT 24
Finished Mar 24 12:34:10 PM PDT 24
Peak memory 193844 kb
Host smart-fde8bdd9-9bb5-4a5b-ab28-72d6fc8d2657
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499514625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2499514625
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.942131033
Short name T802
Test name
Test status
Simulation time 123654019 ps
CPU time 0.6 seconds
Started Mar 24 12:33:47 PM PDT 24
Finished Mar 24 12:33:48 PM PDT 24
Peak memory 193516 kb
Host smart-9656b5d5-3c96-4178-abba-5d6c8637da74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942131033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.942131033
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.827807574
Short name T783
Test name
Test status
Simulation time 13093806 ps
CPU time 0.65 seconds
Started Mar 24 12:33:57 PM PDT 24
Finished Mar 24 12:33:58 PM PDT 24
Peak memory 194484 kb
Host smart-c785dfac-99eb-4d32-b1b7-6c7c1fac45a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827807574 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.827807574
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1984580185
Short name T753
Test name
Test status
Simulation time 204155812 ps
CPU time 2.71 seconds
Started Mar 24 12:34:06 PM PDT 24
Finished Mar 24 12:34:09 PM PDT 24
Peak memory 197908 kb
Host smart-49efc48b-cfb0-4aab-bd54-7e6b6c11d860
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984580185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1984580185
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1066231290
Short name T811
Test name
Test status
Simulation time 24448730 ps
CPU time 0.82 seconds
Started Mar 24 12:35:05 PM PDT 24
Finished Mar 24 12:35:06 PM PDT 24
Peak memory 197688 kb
Host smart-20c086ba-5d63-4cc7-b349-373587a7918b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066231290 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1066231290
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2565725025
Short name T67
Test name
Test status
Simulation time 14349215 ps
CPU time 0.63 seconds
Started Mar 24 12:33:54 PM PDT 24
Finished Mar 24 12:33:54 PM PDT 24
Peak memory 194680 kb
Host smart-64194a03-9012-473b-b3a5-9d4cfdcecb01
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565725025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2565725025
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3862339255
Short name T793
Test name
Test status
Simulation time 23194245 ps
CPU time 0.58 seconds
Started Mar 24 12:33:31 PM PDT 24
Finished Mar 24 12:33:32 PM PDT 24
Peak memory 193528 kb
Host smart-58c06833-f346-4a41-8b92-0cb7b4033603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862339255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3862339255
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.10661537
Short name T843
Test name
Test status
Simulation time 35771749 ps
CPU time 0.85 seconds
Started Mar 24 12:33:50 PM PDT 24
Finished Mar 24 12:33:51 PM PDT 24
Peak memory 196824 kb
Host smart-ba152a18-ec5c-4597-99eb-a75dc09dda3c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10661537 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.gpio_same_csr_outstanding.10661537
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.311757183
Short name T777
Test name
Test status
Simulation time 47129067 ps
CPU time 1.37 seconds
Started Mar 24 12:34:36 PM PDT 24
Finished Mar 24 12:34:38 PM PDT 24
Peak memory 196252 kb
Host smart-9b7d7965-66fc-4a90-81f2-3f2759f12ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311757183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.311757183
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2480354199
Short name T839
Test name
Test status
Simulation time 70361172 ps
CPU time 0.82 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 197856 kb
Host smart-90a1cd42-90b2-4130-8c4d-48af4d19bc55
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480354199 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2480354199
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3486943654
Short name T752
Test name
Test status
Simulation time 153913373 ps
CPU time 0.57 seconds
Started Mar 24 12:33:35 PM PDT 24
Finished Mar 24 12:33:36 PM PDT 24
Peak memory 194444 kb
Host smart-db0b3dc0-b5d3-4d74-bb7b-4beba0128b26
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486943654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3486943654
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2251262598
Short name T834
Test name
Test status
Simulation time 20053275 ps
CPU time 0.57 seconds
Started Mar 24 12:33:51 PM PDT 24
Finished Mar 24 12:33:51 PM PDT 24
Peak memory 193536 kb
Host smart-302a8e84-70d0-4560-a077-78f627611684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251262598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2251262598
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1551888463
Short name T92
Test name
Test status
Simulation time 20028966 ps
CPU time 0.85 seconds
Started Mar 24 12:33:51 PM PDT 24
Finished Mar 24 12:33:52 PM PDT 24
Peak memory 197048 kb
Host smart-c5e9160c-1a77-46b1-97d4-513eec1a315d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551888463 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1551888463
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.543109293
Short name T797
Test name
Test status
Simulation time 136833600 ps
CPU time 1.95 seconds
Started Mar 24 12:33:54 PM PDT 24
Finished Mar 24 12:33:56 PM PDT 24
Peak memory 197856 kb
Host smart-bb5fa8a6-f76c-4ee6-be15-ca2266a30142
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543109293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.543109293
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.603160554
Short name T849
Test name
Test status
Simulation time 38928652 ps
CPU time 0.82 seconds
Started Mar 24 12:33:31 PM PDT 24
Finished Mar 24 12:33:32 PM PDT 24
Peak memory 196828 kb
Host smart-ff7df75b-7bb1-4ee0-9645-fc22dbd74123
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603160554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.603160554
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.953613786
Short name T751
Test name
Test status
Simulation time 17353219 ps
CPU time 0.72 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 197732 kb
Host smart-2aea835b-3843-4a53-8714-f4ecfb6eff97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953613786 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.953613786
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2308280748
Short name T808
Test name
Test status
Simulation time 60413564 ps
CPU time 0.6 seconds
Started Mar 24 12:33:55 PM PDT 24
Finished Mar 24 12:33:56 PM PDT 24
Peak memory 194336 kb
Host smart-9abbddce-ade8-4f4e-84f3-71f28259e7d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308280748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2308280748
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3929843299
Short name T801
Test name
Test status
Simulation time 57695134 ps
CPU time 0.61 seconds
Started Mar 24 12:34:10 PM PDT 24
Finished Mar 24 12:34:10 PM PDT 24
Peak memory 193592 kb
Host smart-0af2000f-2ae4-4465-ad60-6e873690b30d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929843299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3929843299
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.56889149
Short name T93
Test name
Test status
Simulation time 55270261 ps
CPU time 0.73 seconds
Started Mar 24 12:33:53 PM PDT 24
Finished Mar 24 12:33:54 PM PDT 24
Peak memory 195068 kb
Host smart-ca68a396-31b2-48e1-a225-2ec2489908ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56889149 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.gpio_same_csr_outstanding.56889149
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.668376843
Short name T738
Test name
Test status
Simulation time 285349724 ps
CPU time 2.88 seconds
Started Mar 24 12:34:03 PM PDT 24
Finished Mar 24 12:34:06 PM PDT 24
Peak memory 197888 kb
Host smart-775e49f3-d6a2-4149-9083-5c0ce5323b96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668376843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.668376843
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3395446471
Short name T43
Test name
Test status
Simulation time 259831879 ps
CPU time 1.36 seconds
Started Mar 24 12:33:50 PM PDT 24
Finished Mar 24 12:33:51 PM PDT 24
Peak memory 197760 kb
Host smart-19cc415f-4a19-44f4-b580-f5892e953b96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395446471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3395446471
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3177897807
Short name T727
Test name
Test status
Simulation time 72318321 ps
CPU time 1.07 seconds
Started Mar 24 12:33:35 PM PDT 24
Finished Mar 24 12:33:36 PM PDT 24
Peak memory 197888 kb
Host smart-79c0b5bc-3caa-4b27-ab06-71dd521b9553
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177897807 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3177897807
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3325796657
Short name T83
Test name
Test status
Simulation time 38895333 ps
CPU time 0.56 seconds
Started Mar 24 12:33:47 PM PDT 24
Finished Mar 24 12:33:48 PM PDT 24
Peak memory 194156 kb
Host smart-43412ba9-f91e-4fae-9124-69b16302dd14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325796657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3325796657
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1419577531
Short name T821
Test name
Test status
Simulation time 14037335 ps
CPU time 0.59 seconds
Started Mar 24 12:33:51 PM PDT 24
Finished Mar 24 12:33:52 PM PDT 24
Peak memory 193520 kb
Host smart-6aa090a8-185a-4596-bf8e-643f540f6c55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419577531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1419577531
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3345511089
Short name T747
Test name
Test status
Simulation time 167950614 ps
CPU time 1.83 seconds
Started Mar 24 12:33:38 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 197868 kb
Host smart-252fd45d-0af5-4c19-a8df-df9d0452f11b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345511089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3345511089
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2608402898
Short name T785
Test name
Test status
Simulation time 106728523 ps
CPU time 1.12 seconds
Started Mar 24 12:35:18 PM PDT 24
Finished Mar 24 12:35:20 PM PDT 24
Peak memory 197736 kb
Host smart-bc728a05-f6f3-4aeb-b6df-132dfa43ef77
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608402898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2608402898
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2537603294
Short name T728
Test name
Test status
Simulation time 23224994 ps
CPU time 0.7 seconds
Started Mar 24 12:33:40 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 197364 kb
Host smart-4ecede5f-0ca5-40df-b3d0-915f2ab3b0bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537603294 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2537603294
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4046469422
Short name T87
Test name
Test status
Simulation time 93915410 ps
CPU time 0.6 seconds
Started Mar 24 12:33:57 PM PDT 24
Finished Mar 24 12:33:58 PM PDT 24
Peak memory 194640 kb
Host smart-22b624f9-00e3-48c2-a98f-55fbb0341be3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046469422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4046469422
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.971470035
Short name T799
Test name
Test status
Simulation time 11315339 ps
CPU time 0.66 seconds
Started Mar 24 12:33:51 PM PDT 24
Finished Mar 24 12:33:51 PM PDT 24
Peak memory 193548 kb
Host smart-8839357e-7fc2-4595-ab6a-3177c00570d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971470035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.971470035
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.847892163
Short name T771
Test name
Test status
Simulation time 23889666 ps
CPU time 0.62 seconds
Started Mar 24 12:35:09 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 194320 kb
Host smart-650790d2-fa61-4bc3-a0aa-c6f2d3db7edf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847892163 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.847892163
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2874768085
Short name T816
Test name
Test status
Simulation time 149619648 ps
CPU time 1.71 seconds
Started Mar 24 12:33:49 PM PDT 24
Finished Mar 24 12:33:51 PM PDT 24
Peak memory 197900 kb
Host smart-1b6f2666-99f5-42c6-8ee5-83ebdd1c667c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874768085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2874768085
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2737436431
Short name T831
Test name
Test status
Simulation time 111269302 ps
CPU time 1.41 seconds
Started Mar 24 12:33:54 PM PDT 24
Finished Mar 24 12:33:55 PM PDT 24
Peak memory 197880 kb
Host smart-bb4c0041-9081-4a71-82f6-2b2f54719feb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737436431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2737436431
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.845621727
Short name T788
Test name
Test status
Simulation time 146433593 ps
CPU time 0.76 seconds
Started Mar 24 12:34:12 PM PDT 24
Finished Mar 24 12:34:13 PM PDT 24
Peak memory 195760 kb
Host smart-0418303a-23bd-4e27-9627-124b91464355
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845621727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.845621727
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2874280857
Short name T756
Test name
Test status
Simulation time 59680731 ps
CPU time 2.26 seconds
Started Mar 24 12:33:41 PM PDT 24
Finished Mar 24 12:33:44 PM PDT 24
Peak memory 196928 kb
Host smart-a4baad06-0dfd-4d59-a119-c659728d954d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874280857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2874280857
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2577792517
Short name T73
Test name
Test status
Simulation time 59001511 ps
CPU time 0.64 seconds
Started Mar 24 12:33:19 PM PDT 24
Finished Mar 24 12:33:22 PM PDT 24
Peak memory 194552 kb
Host smart-20b36a6e-d20f-44b6-96f9-5ced5798d736
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577792517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2577792517
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2001944458
Short name T774
Test name
Test status
Simulation time 135746845 ps
CPU time 0.93 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:31 PM PDT 24
Peak memory 197816 kb
Host smart-51d6d76b-8557-4581-8b03-e4fe847f9572
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001944458 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2001944458
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1262649371
Short name T82
Test name
Test status
Simulation time 31435804 ps
CPU time 0.61 seconds
Started Mar 24 12:33:48 PM PDT 24
Finished Mar 24 12:33:49 PM PDT 24
Peak memory 194720 kb
Host smart-dc34d58a-6003-4883-b3c1-41e340f417d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262649371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1262649371
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3065783550
Short name T729
Test name
Test status
Simulation time 23133370 ps
CPU time 0.6 seconds
Started Mar 24 12:33:31 PM PDT 24
Finished Mar 24 12:33:31 PM PDT 24
Peak memory 194200 kb
Host smart-e67b70df-ed49-4de3-b1e2-a4b035d89232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065783550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3065783550
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2814538168
Short name T835
Test name
Test status
Simulation time 19225830 ps
CPU time 0.77 seconds
Started Mar 24 12:33:25 PM PDT 24
Finished Mar 24 12:33:26 PM PDT 24
Peak memory 196088 kb
Host smart-0d00ca8c-64e8-4b65-971d-fc7762150ca2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814538168 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2814538168
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.938255384
Short name T837
Test name
Test status
Simulation time 29440234 ps
CPU time 1.44 seconds
Started Mar 24 12:33:26 PM PDT 24
Finished Mar 24 12:33:28 PM PDT 24
Peak memory 197864 kb
Host smart-151f5e54-e28c-4a17-be15-42e6d743cee3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938255384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.938255384
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1963013396
Short name T766
Test name
Test status
Simulation time 51817285 ps
CPU time 0.83 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:31 PM PDT 24
Peak memory 197420 kb
Host smart-7c1dd3b1-d484-4393-91f7-a2fb5e0027be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963013396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1963013396
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2353368843
Short name T746
Test name
Test status
Simulation time 43558825 ps
CPU time 0.57 seconds
Started Mar 24 12:33:58 PM PDT 24
Finished Mar 24 12:33:59 PM PDT 24
Peak memory 193548 kb
Host smart-cd714c27-7577-41c5-bfd8-e531d600c41e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353368843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2353368843
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3229866849
Short name T779
Test name
Test status
Simulation time 25118571 ps
CPU time 0.58 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:45 PM PDT 24
Peak memory 193448 kb
Host smart-9531d792-ce94-4b63-a841-0491c1e388de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229866849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3229866849
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3955776760
Short name T726
Test name
Test status
Simulation time 33700246 ps
CPU time 0.6 seconds
Started Mar 24 12:33:57 PM PDT 24
Finished Mar 24 12:33:58 PM PDT 24
Peak memory 194184 kb
Host smart-b3b38907-1e3a-42f5-b91b-6a366812a31b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955776760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3955776760
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3076467620
Short name T732
Test name
Test status
Simulation time 11467709 ps
CPU time 0.61 seconds
Started Mar 24 12:33:47 PM PDT 24
Finished Mar 24 12:33:48 PM PDT 24
Peak memory 193608 kb
Host smart-51d888c7-3ee7-466b-a6a5-213c664808d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076467620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3076467620
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.4124626764
Short name T805
Test name
Test status
Simulation time 14257208 ps
CPU time 0.57 seconds
Started Mar 24 12:33:48 PM PDT 24
Finished Mar 24 12:33:49 PM PDT 24
Peak memory 193528 kb
Host smart-a08ecd56-aff4-45e3-9a7f-3731ef250f8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124626764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.4124626764
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.786225653
Short name T745
Test name
Test status
Simulation time 20596623 ps
CPU time 0.58 seconds
Started Mar 24 12:33:41 PM PDT 24
Finished Mar 24 12:33:43 PM PDT 24
Peak memory 193460 kb
Host smart-91a7bcf4-9a0f-47e0-ba27-87021dce2ac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786225653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.786225653
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2885695267
Short name T768
Test name
Test status
Simulation time 49777778 ps
CPU time 0.55 seconds
Started Mar 24 12:33:48 PM PDT 24
Finished Mar 24 12:33:48 PM PDT 24
Peak memory 193548 kb
Host smart-56fb798c-928d-489e-82f8-a07b217edf0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885695267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2885695267
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.4093807281
Short name T772
Test name
Test status
Simulation time 20643826 ps
CPU time 0.58 seconds
Started Mar 24 12:34:05 PM PDT 24
Finished Mar 24 12:34:05 PM PDT 24
Peak memory 193504 kb
Host smart-55e31675-2f4d-47d9-8da3-1e9bcd03bc35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093807281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.4093807281
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1523741898
Short name T775
Test name
Test status
Simulation time 16708757 ps
CPU time 0.61 seconds
Started Mar 24 12:34:10 PM PDT 24
Finished Mar 24 12:34:11 PM PDT 24
Peak memory 193476 kb
Host smart-e5dfd228-4417-40e1-b57d-95162ece676f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523741898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1523741898
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.651031510
Short name T741
Test name
Test status
Simulation time 13068000 ps
CPU time 0.57 seconds
Started Mar 24 12:33:58 PM PDT 24
Finished Mar 24 12:33:59 PM PDT 24
Peak memory 194156 kb
Host smart-11326ddd-ec4c-4039-a202-612d2e5400fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651031510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.651031510
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3017342981
Short name T80
Test name
Test status
Simulation time 68095718 ps
CPU time 0.83 seconds
Started Mar 24 12:33:55 PM PDT 24
Finished Mar 24 12:33:56 PM PDT 24
Peak memory 195976 kb
Host smart-25c72266-5ae8-4d78-afee-57b28a0a92f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017342981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3017342981
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1586967440
Short name T823
Test name
Test status
Simulation time 293627523 ps
CPU time 2.37 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:32 PM PDT 24
Peak memory 196468 kb
Host smart-e80a8e7b-231f-451e-990b-0410a37182fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586967440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1586967440
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3141263778
Short name T795
Test name
Test status
Simulation time 11807530 ps
CPU time 0.58 seconds
Started Mar 24 12:33:49 PM PDT 24
Finished Mar 24 12:33:49 PM PDT 24
Peak memory 194184 kb
Host smart-bd2172cd-d27f-4997-9832-0a03f841cbd2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141263778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3141263778
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3754078543
Short name T742
Test name
Test status
Simulation time 19925668 ps
CPU time 0.95 seconds
Started Mar 24 12:33:38 PM PDT 24
Finished Mar 24 12:33:39 PM PDT 24
Peak memory 198220 kb
Host smart-4719607a-71de-443c-8146-6ac6d5588581
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754078543 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3754078543
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2583399001
Short name T69
Test name
Test status
Simulation time 184649063 ps
CPU time 0.6 seconds
Started Mar 24 12:33:37 PM PDT 24
Finished Mar 24 12:33:38 PM PDT 24
Peak memory 194684 kb
Host smart-639fa46e-bd06-41bd-9aa9-65726b1f3f85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583399001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2583399001
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1435435334
Short name T770
Test name
Test status
Simulation time 29921962 ps
CPU time 0.62 seconds
Started Mar 24 12:33:33 PM PDT 24
Finished Mar 24 12:33:33 PM PDT 24
Peak memory 193492 kb
Host smart-be4b50ed-7962-46f0-9d56-bd496869876e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435435334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1435435334
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3900857946
Short name T94
Test name
Test status
Simulation time 32356903 ps
CPU time 0.78 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:31 PM PDT 24
Peak memory 196100 kb
Host smart-e5a86fad-2132-49fe-a305-c744fbf17ecb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900857946 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3900857946
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3605968113
Short name T737
Test name
Test status
Simulation time 109640786 ps
CPU time 1.71 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 197856 kb
Host smart-559b18e2-665a-4203-bd58-240675d93b9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605968113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3605968113
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.25293521
Short name T847
Test name
Test status
Simulation time 171102274 ps
CPU time 0.91 seconds
Started Mar 24 12:33:35 PM PDT 24
Finished Mar 24 12:33:36 PM PDT 24
Peak memory 197764 kb
Host smart-e00d68d0-47c3-463d-aef8-d2657bc4bc7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25293521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_tl_intg_err.25293521
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3625904757
Short name T822
Test name
Test status
Simulation time 42238715 ps
CPU time 0.58 seconds
Started Mar 24 12:34:17 PM PDT 24
Finished Mar 24 12:34:18 PM PDT 24
Peak memory 194176 kb
Host smart-d6145d19-52c4-45c4-8817-3bb109e7e9ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625904757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3625904757
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.76973569
Short name T743
Test name
Test status
Simulation time 46773826 ps
CPU time 0.58 seconds
Started Mar 24 12:33:52 PM PDT 24
Finished Mar 24 12:33:53 PM PDT 24
Peak memory 193436 kb
Host smart-7477021c-ae6f-48ed-a595-084154de3eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76973569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.76973569
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3068979324
Short name T730
Test name
Test status
Simulation time 11563362 ps
CPU time 0.65 seconds
Started Mar 24 12:33:57 PM PDT 24
Finished Mar 24 12:33:58 PM PDT 24
Peak memory 194196 kb
Host smart-9796363b-8b96-42eb-8266-38e4ff947146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068979324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3068979324
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.4008175770
Short name T792
Test name
Test status
Simulation time 71601057 ps
CPU time 0.6 seconds
Started Mar 24 12:34:14 PM PDT 24
Finished Mar 24 12:34:15 PM PDT 24
Peak memory 193600 kb
Host smart-0616daef-4b4b-4aca-9ee6-cf9f63240224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008175770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.4008175770
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2227533391
Short name T734
Test name
Test status
Simulation time 20436374 ps
CPU time 0.58 seconds
Started Mar 24 12:33:51 PM PDT 24
Finished Mar 24 12:33:52 PM PDT 24
Peak memory 194184 kb
Host smart-acfd8c66-8308-4e59-887d-867e5dc26916
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227533391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2227533391
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3453249618
Short name T764
Test name
Test status
Simulation time 12437762 ps
CPU time 0.6 seconds
Started Mar 24 12:33:44 PM PDT 24
Finished Mar 24 12:33:45 PM PDT 24
Peak memory 193548 kb
Host smart-40fe4eab-57f1-41f4-a9bc-4653b1855cbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453249618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3453249618
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.4171512194
Short name T826
Test name
Test status
Simulation time 27287892 ps
CPU time 0.57 seconds
Started Mar 24 12:33:48 PM PDT 24
Finished Mar 24 12:33:48 PM PDT 24
Peak memory 193496 kb
Host smart-0e00dd29-fcb3-45ed-8381-e396bc2e7401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171512194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.4171512194
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.864467794
Short name T828
Test name
Test status
Simulation time 30924909 ps
CPU time 0.59 seconds
Started Mar 24 12:33:43 PM PDT 24
Finished Mar 24 12:33:44 PM PDT 24
Peak memory 193552 kb
Host smart-db74e905-49bf-4250-96aa-bddfb72cbd9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864467794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.864467794
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1199554256
Short name T840
Test name
Test status
Simulation time 14105418 ps
CPU time 0.54 seconds
Started Mar 24 12:33:34 PM PDT 24
Finished Mar 24 12:33:35 PM PDT 24
Peak memory 193492 kb
Host smart-ee0d8055-d4ec-4e6a-9f8d-c76e2ba0cc2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199554256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1199554256
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3452747814
Short name T800
Test name
Test status
Simulation time 17782620 ps
CPU time 0.61 seconds
Started Mar 24 12:33:50 PM PDT 24
Finished Mar 24 12:33:50 PM PDT 24
Peak memory 194268 kb
Host smart-85716e55-c8f1-4dba-bcaa-13bdaef98ab1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452747814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3452747814
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.58174443
Short name T804
Test name
Test status
Simulation time 124260128 ps
CPU time 0.87 seconds
Started Mar 24 12:33:36 PM PDT 24
Finished Mar 24 12:33:38 PM PDT 24
Peak memory 196672 kb
Host smart-4fbb4d5a-0343-42fa-80c1-d55abdde9e98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58174443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
gpio_csr_aliasing.58174443
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4008192854
Short name T70
Test name
Test status
Simulation time 1925624966 ps
CPU time 3.35 seconds
Started Mar 24 12:33:48 PM PDT 24
Finished Mar 24 12:33:51 PM PDT 24
Peak memory 196988 kb
Host smart-6b41c187-c41d-42ef-9592-60e3cb393274
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008192854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.4008192854
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.94941694
Short name T77
Test name
Test status
Simulation time 17250090 ps
CPU time 0.62 seconds
Started Mar 24 12:33:45 PM PDT 24
Finished Mar 24 12:33:46 PM PDT 24
Peak memory 194548 kb
Host smart-86644196-1e0e-43a8-b518-55a5e031dbb8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94941694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.94941694
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.4181466149
Short name T762
Test name
Test status
Simulation time 53859900 ps
CPU time 0.89 seconds
Started Mar 24 12:33:45 PM PDT 24
Finished Mar 24 12:33:46 PM PDT 24
Peak memory 197864 kb
Host smart-70e59d1b-4c5f-414b-8caa-41e140bc490a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181466149 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.4181466149
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1358625733
Short name T86
Test name
Test status
Simulation time 16905143 ps
CPU time 0.63 seconds
Started Mar 24 12:33:45 PM PDT 24
Finished Mar 24 12:33:46 PM PDT 24
Peak memory 195044 kb
Host smart-f54f8023-5552-4aad-aee0-066cc3422b4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358625733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1358625733
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2139309887
Short name T733
Test name
Test status
Simulation time 64645190 ps
CPU time 0.61 seconds
Started Mar 24 12:33:48 PM PDT 24
Finished Mar 24 12:33:49 PM PDT 24
Peak memory 193592 kb
Host smart-3cb495f6-437b-4875-8ea4-4de84634e812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139309887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2139309887
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2887934845
Short name T76
Test name
Test status
Simulation time 118507141 ps
CPU time 0.79 seconds
Started Mar 24 12:34:10 PM PDT 24
Finished Mar 24 12:34:11 PM PDT 24
Peak memory 195996 kb
Host smart-817d793c-21e4-44c5-a15c-e8b474c2b26e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887934845 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2887934845
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2172345544
Short name T781
Test name
Test status
Simulation time 25541325 ps
CPU time 1.34 seconds
Started Mar 24 12:33:31 PM PDT 24
Finished Mar 24 12:33:32 PM PDT 24
Peak memory 197848 kb
Host smart-85b9f481-a681-420a-8b6e-af4650b29083
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172345544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2172345544
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2639500540
Short name T36
Test name
Test status
Simulation time 72659579 ps
CPU time 1.12 seconds
Started Mar 24 12:33:44 PM PDT 24
Finished Mar 24 12:33:45 PM PDT 24
Peak memory 197880 kb
Host smart-24379031-96f8-43e4-8d18-6798423c0086
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639500540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2639500540
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.157234114
Short name T786
Test name
Test status
Simulation time 19072743 ps
CPU time 0.6 seconds
Started Mar 24 12:33:50 PM PDT 24
Finished Mar 24 12:33:50 PM PDT 24
Peak memory 193488 kb
Host smart-5fbef66d-96f5-4512-adee-e0888e0f04bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157234114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.157234114
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1964113984
Short name T790
Test name
Test status
Simulation time 61553060 ps
CPU time 0.6 seconds
Started Mar 24 12:33:50 PM PDT 24
Finished Mar 24 12:33:51 PM PDT 24
Peak memory 193504 kb
Host smart-415ab371-daee-413f-9798-efdb28575640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964113984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1964113984
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1003968704
Short name T744
Test name
Test status
Simulation time 38754049 ps
CPU time 0.62 seconds
Started Mar 24 12:34:05 PM PDT 24
Finished Mar 24 12:34:06 PM PDT 24
Peak memory 194144 kb
Host smart-b8ddc388-dadb-4084-afda-42a89df4b550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003968704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1003968704
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1476588888
Short name T819
Test name
Test status
Simulation time 51952732 ps
CPU time 0.6 seconds
Started Mar 24 12:33:45 PM PDT 24
Finished Mar 24 12:33:46 PM PDT 24
Peak memory 193504 kb
Host smart-e1824fd4-386c-4d0c-a936-66f8841db2c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476588888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1476588888
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2695822732
Short name T731
Test name
Test status
Simulation time 20110992 ps
CPU time 0.59 seconds
Started Mar 24 12:34:02 PM PDT 24
Finished Mar 24 12:34:02 PM PDT 24
Peak memory 193536 kb
Host smart-4437dbc2-a631-4a45-a6ac-93d3ed90d72e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695822732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2695822732
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1577398118
Short name T778
Test name
Test status
Simulation time 61314210 ps
CPU time 0.63 seconds
Started Mar 24 12:34:02 PM PDT 24
Finished Mar 24 12:34:02 PM PDT 24
Peak memory 193588 kb
Host smart-59cedf50-5760-4747-8718-e1c291ec8b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577398118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1577398118
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3315131971
Short name T761
Test name
Test status
Simulation time 42400018 ps
CPU time 0.61 seconds
Started Mar 24 12:33:51 PM PDT 24
Finished Mar 24 12:33:51 PM PDT 24
Peak memory 193632 kb
Host smart-30dbd4cf-58c2-454a-927d-ab404b24d6fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315131971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3315131971
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3719407382
Short name T824
Test name
Test status
Simulation time 37206858 ps
CPU time 0.62 seconds
Started Mar 24 12:33:55 PM PDT 24
Finished Mar 24 12:33:56 PM PDT 24
Peak memory 194216 kb
Host smart-2c1faccd-45d3-4283-9236-41401d273db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719407382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3719407382
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3493372125
Short name T755
Test name
Test status
Simulation time 12244641 ps
CPU time 0.6 seconds
Started Mar 24 12:34:01 PM PDT 24
Finished Mar 24 12:34:01 PM PDT 24
Peak memory 193448 kb
Host smart-a8d182fe-57d4-4c05-b457-b49576dc2ab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493372125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3493372125
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1623826123
Short name T818
Test name
Test status
Simulation time 39556791 ps
CPU time 0.56 seconds
Started Mar 24 12:33:49 PM PDT 24
Finished Mar 24 12:33:49 PM PDT 24
Peak memory 193492 kb
Host smart-2222361b-8835-4229-ac1c-da046db32d6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623826123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1623826123
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2906040607
Short name T780
Test name
Test status
Simulation time 121913417 ps
CPU time 0.91 seconds
Started Mar 24 12:34:15 PM PDT 24
Finished Mar 24 12:34:16 PM PDT 24
Peak memory 197852 kb
Host smart-17df2c42-72db-49a0-94a5-d974d2675dde
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906040607 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2906040607
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2657534456
Short name T814
Test name
Test status
Simulation time 12629149 ps
CPU time 0.65 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 194420 kb
Host smart-97960833-6cd3-4588-ad10-1d3a120e9004
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657534456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2657534456
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1300248139
Short name T740
Test name
Test status
Simulation time 24240323 ps
CPU time 0.62 seconds
Started Mar 24 12:33:40 PM PDT 24
Finished Mar 24 12:33:42 PM PDT 24
Peak memory 194224 kb
Host smart-47e570b8-fe63-4b5d-9a45-ba4a19c69d06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300248139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1300248139
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1629055615
Short name T88
Test name
Test status
Simulation time 358434616 ps
CPU time 0.77 seconds
Started Mar 24 12:33:57 PM PDT 24
Finished Mar 24 12:33:58 PM PDT 24
Peak memory 196204 kb
Host smart-bbb17e35-d9e3-4747-939f-b259d41a2ef4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629055615 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1629055615
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.587194960
Short name T789
Test name
Test status
Simulation time 44474525 ps
CPU time 1.08 seconds
Started Mar 24 12:33:48 PM PDT 24
Finished Mar 24 12:33:49 PM PDT 24
Peak memory 197780 kb
Host smart-a6bb0d7c-2c2e-4327-9650-00d5e49f0ca4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587194960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.587194960
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3641873044
Short name T48
Test name
Test status
Simulation time 75338041 ps
CPU time 1.15 seconds
Started Mar 24 12:33:53 PM PDT 24
Finished Mar 24 12:33:54 PM PDT 24
Peak memory 197444 kb
Host smart-e1ed3bf9-58f8-4e8b-9c70-505c8017e231
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641873044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3641873044
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2424704802
Short name T794
Test name
Test status
Simulation time 62715169 ps
CPU time 0.82 seconds
Started Mar 24 12:33:47 PM PDT 24
Finished Mar 24 12:33:48 PM PDT 24
Peak memory 197812 kb
Host smart-881b3045-6bf7-421a-b3ea-bd196ea95390
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424704802 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2424704802
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1163216012
Short name T845
Test name
Test status
Simulation time 12464192 ps
CPU time 0.61 seconds
Started Mar 24 12:33:51 PM PDT 24
Finished Mar 24 12:33:52 PM PDT 24
Peak memory 194592 kb
Host smart-03253cc3-0b9c-4ce1-8349-3bb327a7bd1e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163216012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1163216012
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2497469117
Short name T784
Test name
Test status
Simulation time 14039590 ps
CPU time 0.56 seconds
Started Mar 24 12:33:29 PM PDT 24
Finished Mar 24 12:33:30 PM PDT 24
Peak memory 194148 kb
Host smart-3765ac86-7651-4222-934a-d010c097ca73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497469117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2497469117
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.318042697
Short name T827
Test name
Test status
Simulation time 17884418 ps
CPU time 0.79 seconds
Started Mar 24 12:34:18 PM PDT 24
Finished Mar 24 12:34:19 PM PDT 24
Peak memory 196264 kb
Host smart-16089f11-e743-4c05-817d-7cc7c6e2f43f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318042697 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.318042697
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1112405273
Short name T765
Test name
Test status
Simulation time 68901824 ps
CPU time 2.08 seconds
Started Mar 24 12:33:38 PM PDT 24
Finished Mar 24 12:33:40 PM PDT 24
Peak memory 197704 kb
Host smart-2a864f29-7b15-46fc-8ac3-05012d95887a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112405273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1112405273
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2514966660
Short name T105
Test name
Test status
Simulation time 173735484 ps
CPU time 1 seconds
Started Mar 24 12:33:44 PM PDT 24
Finished Mar 24 12:33:46 PM PDT 24
Peak memory 197152 kb
Host smart-7d818d3c-b0fc-43bd-a565-c0a175222257
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514966660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2514966660
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2678026972
Short name T809
Test name
Test status
Simulation time 18473592 ps
CPU time 0.99 seconds
Started Mar 24 12:33:37 PM PDT 24
Finished Mar 24 12:33:39 PM PDT 24
Peak memory 197868 kb
Host smart-c6d14501-93cf-4b56-8914-91a22438a3b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678026972 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2678026972
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1938217631
Short name T71
Test name
Test status
Simulation time 17313008 ps
CPU time 0.64 seconds
Started Mar 24 12:34:01 PM PDT 24
Finished Mar 24 12:34:02 PM PDT 24
Peak memory 194620 kb
Host smart-b1542930-b90c-4de1-9a93-46ebe16ed7a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938217631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1938217631
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2132005455
Short name T750
Test name
Test status
Simulation time 13125497 ps
CPU time 0.56 seconds
Started Mar 24 12:34:15 PM PDT 24
Finished Mar 24 12:34:16 PM PDT 24
Peak memory 193552 kb
Host smart-86f2d817-cf87-45a7-8b8c-9caeb442f2a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132005455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2132005455
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3847947008
Short name T763
Test name
Test status
Simulation time 89911416 ps
CPU time 0.7 seconds
Started Mar 24 12:33:48 PM PDT 24
Finished Mar 24 12:33:49 PM PDT 24
Peak memory 195888 kb
Host smart-2e2265bd-4a6d-48e7-a9ac-e502a85bb215
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847947008 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3847947008
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2893159055
Short name T787
Test name
Test status
Simulation time 62716020 ps
CPU time 1.79 seconds
Started Mar 24 12:33:47 PM PDT 24
Finished Mar 24 12:33:49 PM PDT 24
Peak memory 197864 kb
Host smart-ef3aa324-9dc7-4c85-af07-1a5ab6c415c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893159055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2893159055
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1580027563
Short name T37
Test name
Test status
Simulation time 387834388 ps
CPU time 1.3 seconds
Started Mar 24 12:34:12 PM PDT 24
Finished Mar 24 12:34:13 PM PDT 24
Peak memory 197876 kb
Host smart-2e1a4488-8334-4754-8e5b-bc0676f35454
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580027563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1580027563
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3221461327
Short name T810
Test name
Test status
Simulation time 27435028 ps
CPU time 1.25 seconds
Started Mar 24 12:34:12 PM PDT 24
Finished Mar 24 12:34:13 PM PDT 24
Peak memory 197880 kb
Host smart-fdaba2e4-d4d9-40b3-94f5-5b38c2dffd51
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221461327 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3221461327
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3604408256
Short name T85
Test name
Test status
Simulation time 41445953 ps
CPU time 0.59 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 194480 kb
Host smart-925fdaae-88b4-42c1-b31d-4b81091e5077
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604408256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3604408256
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2042515469
Short name T820
Test name
Test status
Simulation time 14240351 ps
CPU time 0.58 seconds
Started Mar 24 12:33:56 PM PDT 24
Finished Mar 24 12:33:57 PM PDT 24
Peak memory 194132 kb
Host smart-29a4f7b3-7dd4-4345-8c48-1fc4d1744a80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042515469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2042515469
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2692447482
Short name T72
Test name
Test status
Simulation time 369930016 ps
CPU time 0.65 seconds
Started Mar 24 12:33:37 PM PDT 24
Finished Mar 24 12:33:38 PM PDT 24
Peak memory 194660 kb
Host smart-0f3a49dd-a975-4348-b446-053eebd16388
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692447482 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2692447482
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2570820901
Short name T757
Test name
Test status
Simulation time 339713433 ps
CPU time 3.08 seconds
Started Mar 24 12:33:49 PM PDT 24
Finished Mar 24 12:33:53 PM PDT 24
Peak memory 198340 kb
Host smart-8d7de99d-27ec-456e-bea2-d8f4e0fb04a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570820901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2570820901
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3746813235
Short name T44
Test name
Test status
Simulation time 122145637 ps
CPU time 1.13 seconds
Started Mar 24 12:33:46 PM PDT 24
Finished Mar 24 12:33:47 PM PDT 24
Peak memory 197936 kb
Host smart-7745dce6-7a52-46ab-8469-f066e29e5c05
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746813235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3746813235
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1054430149
Short name T803
Test name
Test status
Simulation time 139001224 ps
CPU time 1.68 seconds
Started Mar 24 12:33:56 PM PDT 24
Finished Mar 24 12:33:58 PM PDT 24
Peak memory 197992 kb
Host smart-1d6b3fcd-ce0e-4e7e-9b88-3375acb652ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054430149 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1054430149
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3934453657
Short name T773
Test name
Test status
Simulation time 42818268 ps
CPU time 0.62 seconds
Started Mar 24 12:33:40 PM PDT 24
Finished Mar 24 12:33:42 PM PDT 24
Peak memory 194784 kb
Host smart-3c68a38b-c199-4999-9949-ef63c8d4d42a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934453657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3934453657
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.362072958
Short name T760
Test name
Test status
Simulation time 42151119 ps
CPU time 0.61 seconds
Started Mar 24 12:33:40 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 193592 kb
Host smart-0f453f0b-4b79-499d-9b40-8110832b6e90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362072958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.362072958
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1183845381
Short name T90
Test name
Test status
Simulation time 12404321 ps
CPU time 0.6 seconds
Started Mar 24 12:33:58 PM PDT 24
Finished Mar 24 12:33:59 PM PDT 24
Peak memory 194680 kb
Host smart-bb8ecdd6-93cc-47db-a931-00a9432ec462
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183845381 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1183845381
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3690171682
Short name T735
Test name
Test status
Simulation time 90264803 ps
CPU time 1.96 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 197876 kb
Host smart-09657d9e-8cba-4cac-8d28-8af771bd5e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690171682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3690171682
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3497959178
Short name T34
Test name
Test status
Simulation time 50219579 ps
CPU time 0.94 seconds
Started Mar 24 12:33:48 PM PDT 24
Finished Mar 24 12:33:49 PM PDT 24
Peak memory 197460 kb
Host smart-149eadea-8efa-47d0-92d8-ac2f386b6bd4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497959178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3497959178
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1824471547
Short name T636
Test name
Test status
Simulation time 142159336 ps
CPU time 0.55 seconds
Started Mar 24 12:45:06 PM PDT 24
Finished Mar 24 12:45:07 PM PDT 24
Peak memory 193912 kb
Host smart-b903d71f-c2c7-42d0-a8c2-5052a307b8f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824471547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1824471547
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1331889212
Short name T404
Test name
Test status
Simulation time 98396894 ps
CPU time 0.86 seconds
Started Mar 24 12:45:37 PM PDT 24
Finished Mar 24 12:45:38 PM PDT 24
Peak memory 195504 kb
Host smart-8f358f7a-cca3-46f5-9868-484afd900a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331889212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1331889212
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2013141133
Short name T641
Test name
Test status
Simulation time 10617799826 ps
CPU time 19.5 seconds
Started Mar 24 12:45:11 PM PDT 24
Finished Mar 24 12:45:31 PM PDT 24
Peak memory 197056 kb
Host smart-c80bf727-dc4a-4e9d-b02e-56edf220ef8c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013141133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2013141133
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2862152131
Short name T356
Test name
Test status
Simulation time 78264335 ps
CPU time 0.91 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 12:45:10 PM PDT 24
Peak memory 197332 kb
Host smart-461893d3-2840-4472-ad10-b9855ba34a05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862152131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2862152131
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.674911905
Short name T359
Test name
Test status
Simulation time 96798929 ps
CPU time 0.94 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 12:45:09 PM PDT 24
Peak memory 195684 kb
Host smart-6ced0b8e-a9f9-40cc-8a23-eb4a6317a04c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674911905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.674911905
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1001226208
Short name T217
Test name
Test status
Simulation time 846776019 ps
CPU time 2.47 seconds
Started Mar 24 12:45:03 PM PDT 24
Finished Mar 24 12:45:05 PM PDT 24
Peak memory 196308 kb
Host smart-d5805d6a-c372-4400-9859-20db63273ee0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001226208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1001226208
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3988086583
Short name T558
Test name
Test status
Simulation time 24225143 ps
CPU time 0.96 seconds
Started Mar 24 12:45:28 PM PDT 24
Finished Mar 24 12:45:30 PM PDT 24
Peak memory 195480 kb
Host smart-950e75b9-32bb-40de-9377-f029afa50207
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988086583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3988086583
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1275433726
Short name T123
Test name
Test status
Simulation time 49993732 ps
CPU time 1.12 seconds
Started Mar 24 12:45:21 PM PDT 24
Finished Mar 24 12:45:23 PM PDT 24
Peak memory 196012 kb
Host smart-a7eebe86-1c4e-4c72-b9da-caa1a16b7337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275433726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1275433726
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.98640921
Short name T133
Test name
Test status
Simulation time 324453657 ps
CPU time 1.28 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:45:14 PM PDT 24
Peak memory 196564 kb
Host smart-105743a0-6827-4e80-a500-aef4a590aacf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98640921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_p
ulldown.98640921
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2205190659
Short name T142
Test name
Test status
Simulation time 293880405 ps
CPU time 4.6 seconds
Started Mar 24 12:45:13 PM PDT 24
Finished Mar 24 12:45:18 PM PDT 24
Peak memory 197916 kb
Host smart-722fb8c0-0c28-41fe-bcfd-619fc00ac5f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205190659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2205190659
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.93265482
Short name T40
Test name
Test status
Simulation time 179582529 ps
CPU time 1 seconds
Started Mar 24 12:45:18 PM PDT 24
Finished Mar 24 12:45:20 PM PDT 24
Peak memory 214992 kb
Host smart-ffee1a09-b4e1-43d6-9e40-be8457b130cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93265482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.93265482
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.234856985
Short name T277
Test name
Test status
Simulation time 35953914 ps
CPU time 0.98 seconds
Started Mar 24 12:45:13 PM PDT 24
Finished Mar 24 12:45:14 PM PDT 24
Peak memory 196100 kb
Host smart-eae1c574-585d-44ea-83a3-06fc655b09d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234856985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.234856985
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2242130101
Short name T214
Test name
Test status
Simulation time 118577929 ps
CPU time 0.95 seconds
Started Mar 24 12:45:23 PM PDT 24
Finished Mar 24 12:45:24 PM PDT 24
Peak memory 196564 kb
Host smart-38bf6ed6-9af1-4346-b013-bf1f1de996dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242130101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2242130101
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1057566188
Short name T429
Test name
Test status
Simulation time 2869782210 ps
CPU time 84.2 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:46:37 PM PDT 24
Peak memory 198180 kb
Host smart-7c831193-2847-4f64-a4ac-30b100362711
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057566188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1057566188
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.3335504981
Short name T103
Test name
Test status
Simulation time 231098483942 ps
CPU time 1333.56 seconds
Started Mar 24 12:45:09 PM PDT 24
Finished Mar 24 01:07:23 PM PDT 24
Peak memory 198156 kb
Host smart-3ec89be8-74db-440f-8af6-69dc551e1647
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3335504981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.3335504981
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1480383452
Short name T231
Test name
Test status
Simulation time 44163176 ps
CPU time 0.57 seconds
Started Mar 24 12:45:15 PM PDT 24
Finished Mar 24 12:45:16 PM PDT 24
Peak memory 193948 kb
Host smart-1a8d1b2f-60fd-46cf-9e03-ec229df3897d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480383452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1480383452
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3319575832
Short name T553
Test name
Test status
Simulation time 65319282 ps
CPU time 0.75 seconds
Started Mar 24 12:45:22 PM PDT 24
Finished Mar 24 12:45:23 PM PDT 24
Peak memory 195416 kb
Host smart-32b29549-ad20-45db-a523-7c8729ea4acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319575832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3319575832
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2885623288
Short name T542
Test name
Test status
Simulation time 3192430902 ps
CPU time 24.69 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:45:37 PM PDT 24
Peak memory 195920 kb
Host smart-c4f0824a-b2b7-4884-b562-35b0ca1720b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885623288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2885623288
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1678625969
Short name T525
Test name
Test status
Simulation time 19912390 ps
CPU time 0.6 seconds
Started Mar 24 12:45:15 PM PDT 24
Finished Mar 24 12:45:16 PM PDT 24
Peak memory 194348 kb
Host smart-fada9079-fa53-4615-a6c7-2694e3ecb3a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678625969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1678625969
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1097205679
Short name T27
Test name
Test status
Simulation time 119993297 ps
CPU time 0.75 seconds
Started Mar 24 12:45:13 PM PDT 24
Finished Mar 24 12:45:14 PM PDT 24
Peak memory 195488 kb
Host smart-0c7fd3fa-b44e-4115-8f5b-17e0bc799e58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097205679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1097205679
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1403728620
Short name T300
Test name
Test status
Simulation time 107350902 ps
CPU time 1.35 seconds
Started Mar 24 12:45:17 PM PDT 24
Finished Mar 24 12:45:20 PM PDT 24
Peak memory 198060 kb
Host smart-8359c18e-ba82-44c2-9bb0-849930698055
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403728620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1403728620
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1440045391
Short name T382
Test name
Test status
Simulation time 141560405 ps
CPU time 2.77 seconds
Started Mar 24 12:45:21 PM PDT 24
Finished Mar 24 12:45:24 PM PDT 24
Peak memory 196660 kb
Host smart-448c9eb9-dad0-45cd-bc64-04851a801034
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440045391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1440045391
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1557252871
Short name T165
Test name
Test status
Simulation time 25234013 ps
CPU time 0.88 seconds
Started Mar 24 12:45:05 PM PDT 24
Finished Mar 24 12:45:06 PM PDT 24
Peak memory 196004 kb
Host smart-f7080e17-7f4d-4413-947f-a54ff8b8d0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557252871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1557252871
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2622928349
Short name T511
Test name
Test status
Simulation time 44762108 ps
CPU time 1.1 seconds
Started Mar 24 12:45:16 PM PDT 24
Finished Mar 24 12:45:17 PM PDT 24
Peak memory 196708 kb
Host smart-1c1937d7-8a36-4898-a52e-9406cae754db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622928349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2622928349
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1007357634
Short name T604
Test name
Test status
Simulation time 192354713 ps
CPU time 4.29 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 12:45:12 PM PDT 24
Peak memory 197888 kb
Host smart-d9e97cc3-9e44-459c-9de0-caac5ce4f101
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007357634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1007357634
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.696670157
Short name T39
Test name
Test status
Simulation time 133883643 ps
CPU time 0.77 seconds
Started Mar 24 12:45:06 PM PDT 24
Finished Mar 24 12:45:07 PM PDT 24
Peak memory 213740 kb
Host smart-6cf4c1d0-b6ef-4a47-8166-422e45c0df89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696670157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.696670157
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2028136025
Short name T632
Test name
Test status
Simulation time 54547681 ps
CPU time 1.02 seconds
Started Mar 24 12:45:19 PM PDT 24
Finished Mar 24 12:45:21 PM PDT 24
Peak memory 195524 kb
Host smart-8db366a2-1021-4b86-9635-2f1b127150a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028136025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2028136025
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3840466885
Short name T18
Test name
Test status
Simulation time 311809436 ps
CPU time 0.86 seconds
Started Mar 24 12:45:11 PM PDT 24
Finished Mar 24 12:45:12 PM PDT 24
Peak memory 195304 kb
Host smart-8923ed1c-66e9-4d42-890b-4a906b13d805
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840466885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3840466885
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.2643190749
Short name T58
Test name
Test status
Simulation time 21201385939 ps
CPU time 544.33 seconds
Started Mar 24 12:45:15 PM PDT 24
Finished Mar 24 12:54:19 PM PDT 24
Peak memory 198184 kb
Host smart-dee6b096-1d09-421b-92ed-9f1892fe1fc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2643190749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.2643190749
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2867537394
Short name T365
Test name
Test status
Simulation time 52625767 ps
CPU time 0.54 seconds
Started Mar 24 12:45:46 PM PDT 24
Finished Mar 24 12:45:46 PM PDT 24
Peak memory 193900 kb
Host smart-f8410973-5f63-4315-a65f-1d8dfc719772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867537394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2867537394
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3693685300
Short name T258
Test name
Test status
Simulation time 461971723 ps
CPU time 0.94 seconds
Started Mar 24 12:45:45 PM PDT 24
Finished Mar 24 12:45:46 PM PDT 24
Peak memory 195780 kb
Host smart-60bf76c9-a951-41a8-ac22-d120e132b0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693685300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3693685300
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.25823402
Short name T166
Test name
Test status
Simulation time 356965435 ps
CPU time 4.96 seconds
Started Mar 24 12:45:46 PM PDT 24
Finished Mar 24 12:45:51 PM PDT 24
Peak memory 196788 kb
Host smart-8fae7ff3-cd61-4f10-b750-4f30e9c19fc0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25823402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stress
.25823402
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1137601182
Short name T401
Test name
Test status
Simulation time 46197425 ps
CPU time 0.8 seconds
Started Mar 24 12:45:46 PM PDT 24
Finished Mar 24 12:45:47 PM PDT 24
Peak memory 196056 kb
Host smart-e2b23e1b-df2e-4f4e-a306-da5731558e4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137601182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1137601182
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2181677297
Short name T137
Test name
Test status
Simulation time 42790231 ps
CPU time 1.23 seconds
Started Mar 24 12:45:47 PM PDT 24
Finished Mar 24 12:45:49 PM PDT 24
Peak memory 196544 kb
Host smart-133d8dc0-5808-464d-9b63-3b6e972d4a1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181677297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2181677297
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3536966398
Short name T719
Test name
Test status
Simulation time 155633134 ps
CPU time 2.02 seconds
Started Mar 24 12:45:44 PM PDT 24
Finished Mar 24 12:45:46 PM PDT 24
Peak memory 198080 kb
Host smart-3f7a9c3b-0c3d-4cc5-9029-33bd34c0160e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536966398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3536966398
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1790941915
Short name T314
Test name
Test status
Simulation time 134613135 ps
CPU time 1.32 seconds
Started Mar 24 12:45:44 PM PDT 24
Finished Mar 24 12:45:46 PM PDT 24
Peak memory 195732 kb
Host smart-de9f96dd-060c-43e6-86f8-676010b9cd72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790941915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1790941915
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3846174399
Short name T324
Test name
Test status
Simulation time 33336836 ps
CPU time 1.19 seconds
Started Mar 24 12:45:47 PM PDT 24
Finished Mar 24 12:45:48 PM PDT 24
Peak memory 197992 kb
Host smart-d032dc0c-4b76-4f22-b9df-5d86a9625c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846174399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3846174399
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2179318595
Short name T508
Test name
Test status
Simulation time 62013066 ps
CPU time 0.76 seconds
Started Mar 24 12:45:45 PM PDT 24
Finished Mar 24 12:45:45 PM PDT 24
Peak memory 195476 kb
Host smart-7fb04747-7dce-4d48-948e-b0c44ebb18a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179318595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2179318595
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.626147663
Short name T457
Test name
Test status
Simulation time 1515820626 ps
CPU time 4.96 seconds
Started Mar 24 12:45:46 PM PDT 24
Finished Mar 24 12:45:51 PM PDT 24
Peak memory 198000 kb
Host smart-f8b7fe8f-602e-4fc9-ba95-8078b2108d29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626147663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.626147663
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.25166450
Short name T651
Test name
Test status
Simulation time 44850191 ps
CPU time 0.95 seconds
Started Mar 24 12:45:49 PM PDT 24
Finished Mar 24 12:45:50 PM PDT 24
Peak memory 195872 kb
Host smart-1d07d719-b198-4cf2-a820-d755e9531c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25166450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.25166450
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3058221665
Short name T532
Test name
Test status
Simulation time 163108074 ps
CPU time 0.96 seconds
Started Mar 24 12:45:48 PM PDT 24
Finished Mar 24 12:45:49 PM PDT 24
Peak memory 196584 kb
Host smart-3b4b1689-e6d3-47d6-a6ba-49b42e9e8f49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058221665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3058221665
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2755897955
Short name T122
Test name
Test status
Simulation time 5773961201 ps
CPU time 144.41 seconds
Started Mar 24 12:45:46 PM PDT 24
Finished Mar 24 12:48:10 PM PDT 24
Peak memory 198140 kb
Host smart-1b91935c-fb3b-4344-bfb9-63a778f405a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755897955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2755897955
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1305212145
Short name T567
Test name
Test status
Simulation time 12379287 ps
CPU time 0.62 seconds
Started Mar 24 12:45:51 PM PDT 24
Finished Mar 24 12:45:51 PM PDT 24
Peak memory 193940 kb
Host smart-77accc29-15c4-4b75-a123-6bf81a38c50e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305212145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1305212145
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3131132980
Short name T119
Test name
Test status
Simulation time 64457446 ps
CPU time 0.75 seconds
Started Mar 24 12:45:50 PM PDT 24
Finished Mar 24 12:45:51 PM PDT 24
Peak memory 195192 kb
Host smart-de90f07e-2418-4dae-a189-b6d8af324745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131132980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3131132980
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3064506209
Short name T621
Test name
Test status
Simulation time 2699861337 ps
CPU time 23.03 seconds
Started Mar 24 12:45:54 PM PDT 24
Finished Mar 24 12:46:17 PM PDT 24
Peak memory 196784 kb
Host smart-3ab31b22-71c9-40d5-88de-88b990e4a9d4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064506209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3064506209
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2072134002
Short name T370
Test name
Test status
Simulation time 235739276 ps
CPU time 0.92 seconds
Started Mar 24 12:45:53 PM PDT 24
Finished Mar 24 12:45:54 PM PDT 24
Peak memory 196588 kb
Host smart-75ce9432-f168-4eb2-986d-848b66bc2039
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072134002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2072134002
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1758370509
Short name T310
Test name
Test status
Simulation time 215286893 ps
CPU time 1.07 seconds
Started Mar 24 12:45:53 PM PDT 24
Finished Mar 24 12:45:54 PM PDT 24
Peak memory 195976 kb
Host smart-2086fca0-168e-44c6-b95a-7ebbef09214a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758370509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1758370509
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2524867128
Short name T364
Test name
Test status
Simulation time 51481237 ps
CPU time 1.88 seconds
Started Mar 24 12:45:52 PM PDT 24
Finished Mar 24 12:45:53 PM PDT 24
Peak memory 196380 kb
Host smart-6e3eae5e-170a-4abe-9241-d380d78bb3f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524867128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2524867128
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3207550078
Short name T497
Test name
Test status
Simulation time 34868428 ps
CPU time 0.97 seconds
Started Mar 24 12:45:53 PM PDT 24
Finished Mar 24 12:45:54 PM PDT 24
Peak memory 195568 kb
Host smart-6d05d4b5-e3aa-451a-8911-78ffe79cfe97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207550078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3207550078
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3680027999
Short name T140
Test name
Test status
Simulation time 21652172 ps
CPU time 0.94 seconds
Started Mar 24 12:45:50 PM PDT 24
Finished Mar 24 12:45:52 PM PDT 24
Peak memory 195704 kb
Host smart-e4ed9ac4-49e7-4048-83af-953f24433c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680027999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3680027999
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1725755889
Short name T417
Test name
Test status
Simulation time 49819825 ps
CPU time 1.08 seconds
Started Mar 24 12:45:51 PM PDT 24
Finished Mar 24 12:45:52 PM PDT 24
Peak memory 195976 kb
Host smart-f14ca46c-b605-4c93-a052-813ed0e0cf99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725755889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1725755889
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3894568763
Short name T552
Test name
Test status
Simulation time 2042592511 ps
CPU time 5.5 seconds
Started Mar 24 12:45:51 PM PDT 24
Finished Mar 24 12:45:57 PM PDT 24
Peak memory 197980 kb
Host smart-7cd9034c-89b3-4e0a-9b2c-14e3b10af66d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894568763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3894568763
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3173495079
Short name T421
Test name
Test status
Simulation time 128390660 ps
CPU time 1.15 seconds
Started Mar 24 12:45:47 PM PDT 24
Finished Mar 24 12:45:48 PM PDT 24
Peak memory 196428 kb
Host smart-2e7cea18-906b-4c05-b456-323a41b67bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173495079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3173495079
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1839416394
Short name T304
Test name
Test status
Simulation time 50699076 ps
CPU time 0.77 seconds
Started Mar 24 12:45:46 PM PDT 24
Finished Mar 24 12:45:47 PM PDT 24
Peak memory 196028 kb
Host smart-5e9cb1b9-2ca7-47aa-9f7d-5475bba3901f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839416394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1839416394
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2751731136
Short name T586
Test name
Test status
Simulation time 34083885508 ps
CPU time 139.14 seconds
Started Mar 24 12:45:50 PM PDT 24
Finished Mar 24 12:48:09 PM PDT 24
Peak memory 198164 kb
Host smart-c15afcd3-9440-4439-a1e4-1adbc34f3da4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751731136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2751731136
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.2806508575
Short name T309
Test name
Test status
Simulation time 10708595972 ps
CPU time 252.02 seconds
Started Mar 24 12:45:49 PM PDT 24
Finished Mar 24 12:50:01 PM PDT 24
Peak memory 198068 kb
Host smart-5860c1ab-624f-4998-84db-f9e9e8f4160a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2806508575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.2806508575
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1310076844
Short name T426
Test name
Test status
Simulation time 41971274 ps
CPU time 0.79 seconds
Started Mar 24 12:45:52 PM PDT 24
Finished Mar 24 12:45:53 PM PDT 24
Peak memory 195216 kb
Host smart-a8c46921-28c9-49fd-9118-2b679cac09d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310076844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1310076844
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3555974464
Short name T673
Test name
Test status
Simulation time 4497826330 ps
CPU time 18.82 seconds
Started Mar 24 12:45:54 PM PDT 24
Finished Mar 24 12:46:13 PM PDT 24
Peak memory 196960 kb
Host smart-5d8e6a62-99b5-45a6-8305-6b7e70a48287
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555974464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3555974464
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3289917784
Short name T574
Test name
Test status
Simulation time 55958670 ps
CPU time 0.9 seconds
Started Mar 24 12:45:56 PM PDT 24
Finished Mar 24 12:45:57 PM PDT 24
Peak memory 196108 kb
Host smart-7e1b09fa-273e-4354-9ec4-aabb3b721661
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289917784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3289917784
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.80347061
Short name T110
Test name
Test status
Simulation time 25420530 ps
CPU time 0.7 seconds
Started Mar 24 12:45:54 PM PDT 24
Finished Mar 24 12:45:55 PM PDT 24
Peak memory 194400 kb
Host smart-70eabdb9-d49b-4de0-9645-c8282bd8337a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80347061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.80347061
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.260363878
Short name T547
Test name
Test status
Simulation time 393917466 ps
CPU time 1.26 seconds
Started Mar 24 12:45:52 PM PDT 24
Finished Mar 24 12:45:53 PM PDT 24
Peak memory 196612 kb
Host smart-8c959707-785f-49c7-ba2d-8fc04b191909
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260363878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.260363878
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.531023031
Short name T147
Test name
Test status
Simulation time 451589696 ps
CPU time 3.17 seconds
Started Mar 24 12:45:50 PM PDT 24
Finished Mar 24 12:45:53 PM PDT 24
Peak memory 198092 kb
Host smart-a4965d1d-01e6-49f8-b943-ebc03b65435f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531023031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
531023031
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2186915405
Short name T257
Test name
Test status
Simulation time 26414118 ps
CPU time 0.92 seconds
Started Mar 24 12:45:50 PM PDT 24
Finished Mar 24 12:45:51 PM PDT 24
Peak memory 196004 kb
Host smart-9590d859-bf63-46cb-93a4-3c4460bd45c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186915405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2186915405
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.950597109
Short name T631
Test name
Test status
Simulation time 43288907 ps
CPU time 0.9 seconds
Started Mar 24 12:45:50 PM PDT 24
Finished Mar 24 12:45:51 PM PDT 24
Peak memory 196032 kb
Host smart-b0afb121-f25f-4a5b-b04a-55865eeecb27
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950597109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.950597109
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2631277185
Short name T624
Test name
Test status
Simulation time 4040566654 ps
CPU time 4.09 seconds
Started Mar 24 12:45:52 PM PDT 24
Finished Mar 24 12:45:57 PM PDT 24
Peak memory 198080 kb
Host smart-e1b94136-1222-4913-935c-e3766280982d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631277185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2631277185
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1054903224
Short name T569
Test name
Test status
Simulation time 309629179 ps
CPU time 1.31 seconds
Started Mar 24 12:45:51 PM PDT 24
Finished Mar 24 12:45:52 PM PDT 24
Peak memory 197980 kb
Host smart-1f42158b-6385-4c5b-bb08-fdf853a7c724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054903224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1054903224
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.4062708862
Short name T628
Test name
Test status
Simulation time 279163197 ps
CPU time 1.16 seconds
Started Mar 24 12:45:52 PM PDT 24
Finished Mar 24 12:45:53 PM PDT 24
Peak memory 196576 kb
Host smart-23f4308b-50bc-44be-9af4-b056644e0bc7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062708862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.4062708862
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1622041665
Short name T633
Test name
Test status
Simulation time 32434749003 ps
CPU time 205.9 seconds
Started Mar 24 12:45:50 PM PDT 24
Finished Mar 24 12:49:16 PM PDT 24
Peak memory 198180 kb
Host smart-2901caf1-b579-42df-b8b4-6fae678f03e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622041665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1622041665
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.3323251683
Short name T57
Test name
Test status
Simulation time 443550712320 ps
CPU time 1034.3 seconds
Started Mar 24 12:45:55 PM PDT 24
Finished Mar 24 01:03:10 PM PDT 24
Peak memory 206468 kb
Host smart-f5f6bf24-a5be-44fa-bba6-ef4d1dcce949
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3323251683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.3323251683
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.579072786
Short name T240
Test name
Test status
Simulation time 13532425 ps
CPU time 0.55 seconds
Started Mar 24 12:45:59 PM PDT 24
Finished Mar 24 12:46:00 PM PDT 24
Peak memory 194604 kb
Host smart-06411c76-9b31-419c-aa29-30c4b38d7304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579072786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.579072786
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3716489862
Short name T366
Test name
Test status
Simulation time 68648567 ps
CPU time 0.74 seconds
Started Mar 24 12:45:55 PM PDT 24
Finished Mar 24 12:45:56 PM PDT 24
Peak memory 194260 kb
Host smart-fa6c9065-b482-466f-9341-679a1fd08002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716489862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3716489862
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1264960720
Short name T541
Test name
Test status
Simulation time 1203270390 ps
CPU time 12.02 seconds
Started Mar 24 12:46:02 PM PDT 24
Finished Mar 24 12:46:14 PM PDT 24
Peak memory 196704 kb
Host smart-fb4db216-4548-49d5-8730-35184d0c3853
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264960720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1264960720
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1090597032
Short name T405
Test name
Test status
Simulation time 66211038 ps
CPU time 0.92 seconds
Started Mar 24 12:46:01 PM PDT 24
Finished Mar 24 12:46:02 PM PDT 24
Peak memory 196396 kb
Host smart-419f57d1-dd22-4ca1-8927-48154c151b78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090597032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1090597032
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.464853016
Short name T335
Test name
Test status
Simulation time 89389628 ps
CPU time 0.84 seconds
Started Mar 24 12:45:50 PM PDT 24
Finished Mar 24 12:45:51 PM PDT 24
Peak memory 197300 kb
Host smart-5254a0e0-5a28-4082-9786-aaf58b0e9c38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464853016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.464853016
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.772110337
Short name T236
Test name
Test status
Simulation time 81641641 ps
CPU time 1.01 seconds
Started Mar 24 12:46:00 PM PDT 24
Finished Mar 24 12:46:01 PM PDT 24
Peak memory 197140 kb
Host smart-6bfc4c05-0f90-49b1-a28e-e2b6990b76eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772110337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.772110337
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.4206649503
Short name T446
Test name
Test status
Simulation time 116175480 ps
CPU time 3.66 seconds
Started Mar 24 12:45:59 PM PDT 24
Finished Mar 24 12:46:03 PM PDT 24
Peak memory 197112 kb
Host smart-d7062939-eeaa-40b6-b94f-3e2edf6f77a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206649503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.4206649503
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.76330312
Short name T526
Test name
Test status
Simulation time 40163375 ps
CPU time 1.09 seconds
Started Mar 24 12:45:52 PM PDT 24
Finished Mar 24 12:45:53 PM PDT 24
Peak memory 196044 kb
Host smart-9a727a8b-918e-404c-86c1-68d5ef37a88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76330312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.76330312
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2381183412
Short name T22
Test name
Test status
Simulation time 44274090 ps
CPU time 0.9 seconds
Started Mar 24 12:45:56 PM PDT 24
Finished Mar 24 12:45:57 PM PDT 24
Peak memory 195836 kb
Host smart-9cd3f50f-81c4-4fd5-9956-80fd08c9a8fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381183412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2381183412
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3330461320
Short name T441
Test name
Test status
Simulation time 785448357 ps
CPU time 3.86 seconds
Started Mar 24 12:45:59 PM PDT 24
Finished Mar 24 12:46:03 PM PDT 24
Peak memory 197960 kb
Host smart-0222cbd9-d1f4-4643-8020-97a1a1328b06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330461320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3330461320
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2357070825
Short name T612
Test name
Test status
Simulation time 350163889 ps
CPU time 1.26 seconds
Started Mar 24 12:45:54 PM PDT 24
Finished Mar 24 12:45:55 PM PDT 24
Peak memory 196672 kb
Host smart-df10c246-fe84-41b0-bff1-09cb07559640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357070825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2357070825
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3553663930
Short name T336
Test name
Test status
Simulation time 36987710 ps
CPU time 1.13 seconds
Started Mar 24 12:45:52 PM PDT 24
Finished Mar 24 12:45:53 PM PDT 24
Peak memory 196332 kb
Host smart-250c9483-5999-4f28-9e58-80f7dd60abbb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553663930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3553663930
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1568184775
Short name T129
Test name
Test status
Simulation time 62838032112 ps
CPU time 189.09 seconds
Started Mar 24 12:46:03 PM PDT 24
Finished Mar 24 12:49:13 PM PDT 24
Peak memory 198232 kb
Host smart-587cdd35-dd54-4c1d-af3d-e7b9df66135d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568184775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1568184775
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.535399773
Short name T555
Test name
Test status
Simulation time 97176726 ps
CPU time 0.58 seconds
Started Mar 24 12:46:00 PM PDT 24
Finished Mar 24 12:46:00 PM PDT 24
Peak memory 194020 kb
Host smart-9112b80c-b6aa-41b4-ad97-4c976efd464b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535399773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.535399773
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3327019413
Short name T414
Test name
Test status
Simulation time 201539523 ps
CPU time 0.7 seconds
Started Mar 24 12:46:01 PM PDT 24
Finished Mar 24 12:46:02 PM PDT 24
Peak memory 194856 kb
Host smart-07bb1495-4a2e-437c-8be5-decd680471b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327019413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3327019413
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.895652815
Short name T301
Test name
Test status
Simulation time 1276365159 ps
CPU time 11.38 seconds
Started Mar 24 12:45:59 PM PDT 24
Finished Mar 24 12:46:11 PM PDT 24
Peak memory 196700 kb
Host smart-a762194d-31f4-46e6-945f-c11b2d57bf2a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895652815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.895652815
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1109545845
Short name T400
Test name
Test status
Simulation time 81746418 ps
CPU time 0.79 seconds
Started Mar 24 12:46:00 PM PDT 24
Finished Mar 24 12:46:01 PM PDT 24
Peak memory 195976 kb
Host smart-6819754c-0042-484e-9d2d-89cd82c249b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109545845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1109545845
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.777357757
Short name T152
Test name
Test status
Simulation time 49501236 ps
CPU time 0.95 seconds
Started Mar 24 12:45:59 PM PDT 24
Finished Mar 24 12:46:00 PM PDT 24
Peak memory 197396 kb
Host smart-bf0cd9bd-adcf-4114-ae05-5dbb6f0e1862
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777357757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.777357757
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3441165964
Short name T582
Test name
Test status
Simulation time 83845832 ps
CPU time 1.73 seconds
Started Mar 24 12:46:00 PM PDT 24
Finished Mar 24 12:46:01 PM PDT 24
Peak memory 196652 kb
Host smart-c8f6f34d-2625-4eeb-9e96-921810d749f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441165964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3441165964
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2312037527
Short name T177
Test name
Test status
Simulation time 159803739 ps
CPU time 2.35 seconds
Started Mar 24 12:46:01 PM PDT 24
Finished Mar 24 12:46:04 PM PDT 24
Peak memory 197192 kb
Host smart-860c1974-ebee-4b81-8063-af393c749296
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312037527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2312037527
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3783783766
Short name T344
Test name
Test status
Simulation time 36528401 ps
CPU time 0.87 seconds
Started Mar 24 12:45:58 PM PDT 24
Finished Mar 24 12:45:59 PM PDT 24
Peak memory 196476 kb
Host smart-13e1509a-27bd-4f93-b2df-7495af19c908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783783766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3783783766
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2258366447
Short name T609
Test name
Test status
Simulation time 16670842 ps
CPU time 0.64 seconds
Started Mar 24 12:46:00 PM PDT 24
Finished Mar 24 12:46:01 PM PDT 24
Peak memory 194256 kb
Host smart-9e024185-0299-4b9b-82fd-5eedc1185f69
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258366447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2258366447
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.403909419
Short name T4
Test name
Test status
Simulation time 910438268 ps
CPU time 2.78 seconds
Started Mar 24 12:45:59 PM PDT 24
Finished Mar 24 12:46:02 PM PDT 24
Peak memory 197888 kb
Host smart-a5b7d1a6-dcc2-4814-af8e-74d79ea6111e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403909419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ran
dom_long_reg_writes_reg_reads.403909419
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2793700024
Short name T706
Test name
Test status
Simulation time 35871256 ps
CPU time 1.01 seconds
Started Mar 24 12:45:58 PM PDT 24
Finished Mar 24 12:45:59 PM PDT 24
Peak memory 195652 kb
Host smart-88b6c588-2bc9-4b3e-8db0-a422b44580c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793700024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2793700024
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.232544979
Short name T454
Test name
Test status
Simulation time 31236711 ps
CPU time 0.8 seconds
Started Mar 24 12:46:00 PM PDT 24
Finished Mar 24 12:46:02 PM PDT 24
Peak memory 196024 kb
Host smart-fbba019a-699f-45b7-a923-1ab62c18ac98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232544979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.232544979
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3186779830
Short name T596
Test name
Test status
Simulation time 2012508139 ps
CPU time 21.91 seconds
Started Mar 24 12:46:03 PM PDT 24
Finished Mar 24 12:46:25 PM PDT 24
Peak memory 197812 kb
Host smart-e0db519b-dfe5-4b91-bdca-c6c9eed43762
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186779830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3186779830
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2233779877
Short name T289
Test name
Test status
Simulation time 50686888819 ps
CPU time 1280.42 seconds
Started Mar 24 12:46:01 PM PDT 24
Finished Mar 24 01:07:22 PM PDT 24
Peak memory 198236 kb
Host smart-19aa44d3-651a-487f-9f41-dd24a5ea3278
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2233779877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2233779877
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3437711193
Short name T235
Test name
Test status
Simulation time 75468096 ps
CPU time 0.6 seconds
Started Mar 24 12:46:06 PM PDT 24
Finished Mar 24 12:46:07 PM PDT 24
Peak memory 194752 kb
Host smart-ed3b6c87-cc35-491f-965d-95408f56bf41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437711193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3437711193
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2797453370
Short name T462
Test name
Test status
Simulation time 71824702 ps
CPU time 0.68 seconds
Started Mar 24 12:45:59 PM PDT 24
Finished Mar 24 12:46:00 PM PDT 24
Peak memory 194876 kb
Host smart-34710cbc-8951-4a73-8fd2-afb5311eecf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797453370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2797453370
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1027476490
Short name T654
Test name
Test status
Simulation time 2364563972 ps
CPU time 11.46 seconds
Started Mar 24 12:46:09 PM PDT 24
Finished Mar 24 12:46:21 PM PDT 24
Peak memory 196884 kb
Host smart-25fb728c-c8ce-4b40-b8cf-6a8a9b3e1018
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027476490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1027476490
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1429263571
Short name T180
Test name
Test status
Simulation time 69359933 ps
CPU time 1.01 seconds
Started Mar 24 12:46:07 PM PDT 24
Finished Mar 24 12:46:09 PM PDT 24
Peak memory 196592 kb
Host smart-7f2f3dae-3efe-4aee-bd84-71e6c33b36ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429263571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1429263571
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.970536958
Short name T422
Test name
Test status
Simulation time 70282361 ps
CPU time 0.8 seconds
Started Mar 24 12:46:03 PM PDT 24
Finished Mar 24 12:46:04 PM PDT 24
Peak memory 195660 kb
Host smart-2b7b079e-f2bc-4f1c-adad-c8483fcbfd01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970536958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.970536958
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2372210057
Short name T436
Test name
Test status
Simulation time 65774778 ps
CPU time 2.63 seconds
Started Mar 24 12:46:06 PM PDT 24
Finished Mar 24 12:46:09 PM PDT 24
Peak memory 196480 kb
Host smart-b0a18536-01d9-4268-a3d9-dd26e3dfbe42
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372210057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2372210057
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.160939561
Short name T502
Test name
Test status
Simulation time 81571651 ps
CPU time 1.45 seconds
Started Mar 24 12:46:02 PM PDT 24
Finished Mar 24 12:46:03 PM PDT 24
Peak memory 196136 kb
Host smart-176d5f3d-48d9-4a34-8ddc-8d713b053b3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160939561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
160939561
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1432752391
Short name T372
Test name
Test status
Simulation time 97641455 ps
CPU time 0.69 seconds
Started Mar 24 12:46:00 PM PDT 24
Finished Mar 24 12:46:01 PM PDT 24
Peak memory 195020 kb
Host smart-1675248e-367a-4896-960c-14d9c99f7eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432752391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1432752391
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3260078418
Short name T427
Test name
Test status
Simulation time 323056388 ps
CPU time 0.78 seconds
Started Mar 24 12:45:59 PM PDT 24
Finished Mar 24 12:46:00 PM PDT 24
Peak memory 195500 kb
Host smart-37f7e7c8-eabb-4cc3-bd8d-200ac7a49e9d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260078418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3260078418
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.234106439
Short name T242
Test name
Test status
Simulation time 100434554 ps
CPU time 4.23 seconds
Started Mar 24 12:46:06 PM PDT 24
Finished Mar 24 12:46:12 PM PDT 24
Peak memory 198040 kb
Host smart-cef096ab-dd73-41f4-b3a1-d54ba7eea3e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234106439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.234106439
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3848605573
Short name T278
Test name
Test status
Simulation time 61394252 ps
CPU time 1.12 seconds
Started Mar 24 12:46:02 PM PDT 24
Finished Mar 24 12:46:03 PM PDT 24
Peak memory 196408 kb
Host smart-ae141b3e-7e98-4809-b8fd-9ec953cb83ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848605573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3848605573
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2001714431
Short name T172
Test name
Test status
Simulation time 70332785 ps
CPU time 1.16 seconds
Started Mar 24 12:46:01 PM PDT 24
Finished Mar 24 12:46:02 PM PDT 24
Peak memory 196432 kb
Host smart-d143171a-bcb7-4c47-9521-0834c3a8d65f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001714431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2001714431
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1483350186
Short name T209
Test name
Test status
Simulation time 3535206058 ps
CPU time 16.92 seconds
Started Mar 24 12:46:07 PM PDT 24
Finished Mar 24 12:46:25 PM PDT 24
Peak memory 198144 kb
Host smart-6f6baee3-f364-4167-8e20-17373a2a638a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483350186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1483350186
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.4286881611
Short name T333
Test name
Test status
Simulation time 49777882675 ps
CPU time 543.01 seconds
Started Mar 24 12:46:08 PM PDT 24
Finished Mar 24 12:55:12 PM PDT 24
Peak memory 198136 kb
Host smart-cd5d7186-ab40-4941-8cdf-1fa604f2f7f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4286881611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.4286881611
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1587729561
Short name T255
Test name
Test status
Simulation time 26241099 ps
CPU time 0.57 seconds
Started Mar 24 12:46:05 PM PDT 24
Finished Mar 24 12:46:06 PM PDT 24
Peak memory 194800 kb
Host smart-6181b23e-0f29-4a6f-a97b-169f1d34b948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587729561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1587729561
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2405094196
Short name T145
Test name
Test status
Simulation time 42260272 ps
CPU time 0.93 seconds
Started Mar 24 12:46:05 PM PDT 24
Finished Mar 24 12:46:07 PM PDT 24
Peak memory 195908 kb
Host smart-4b042bc2-3b5a-434a-8cd8-f4827d5d6516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405094196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2405094196
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3123475791
Short name T625
Test name
Test status
Simulation time 2733923351 ps
CPU time 20.47 seconds
Started Mar 24 12:46:09 PM PDT 24
Finished Mar 24 12:46:30 PM PDT 24
Peak memory 197092 kb
Host smart-9357fd07-81fd-4dbc-9843-44dd8ec89a30
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123475791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3123475791
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.4212909540
Short name T31
Test name
Test status
Simulation time 80273133 ps
CPU time 1.11 seconds
Started Mar 24 12:46:06 PM PDT 24
Finished Mar 24 12:46:08 PM PDT 24
Peak memory 197940 kb
Host smart-08e3d2e1-18ae-489f-ba7c-bb264b354043
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212909540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.4212909540
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3651154401
Short name T593
Test name
Test status
Simulation time 85073009 ps
CPU time 1.3 seconds
Started Mar 24 12:46:05 PM PDT 24
Finished Mar 24 12:46:07 PM PDT 24
Peak memory 197236 kb
Host smart-0807fc79-8304-4aae-86b6-6083d8b647eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651154401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3651154401
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.4171504311
Short name T318
Test name
Test status
Simulation time 87378702 ps
CPU time 3.47 seconds
Started Mar 24 12:46:11 PM PDT 24
Finished Mar 24 12:46:15 PM PDT 24
Peak memory 198052 kb
Host smart-010fb1a7-5eb1-40b6-bc2e-e58d2db4af85
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171504311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.4171504311
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1415352846
Short name T141
Test name
Test status
Simulation time 114146743 ps
CPU time 2.57 seconds
Started Mar 24 12:46:09 PM PDT 24
Finished Mar 24 12:46:13 PM PDT 24
Peak memory 195832 kb
Host smart-cc278316-dcce-41a4-80f9-4a35e3cab1dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415352846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1415352846
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2266598672
Short name T645
Test name
Test status
Simulation time 120036399 ps
CPU time 1.14 seconds
Started Mar 24 12:46:06 PM PDT 24
Finished Mar 24 12:46:08 PM PDT 24
Peak memory 196068 kb
Host smart-10c4e59e-75cb-481e-8765-88e8805bc484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266598672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2266598672
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2319365287
Short name T131
Test name
Test status
Simulation time 97802951 ps
CPU time 1.06 seconds
Started Mar 24 12:46:08 PM PDT 24
Finished Mar 24 12:46:10 PM PDT 24
Peak memory 196636 kb
Host smart-54b32080-05f1-4135-b552-572ab8f3681c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319365287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2319365287
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1660882767
Short name T241
Test name
Test status
Simulation time 261923826 ps
CPU time 3.2 seconds
Started Mar 24 12:46:08 PM PDT 24
Finished Mar 24 12:46:12 PM PDT 24
Peak memory 197844 kb
Host smart-e756b9f5-6f2f-4b69-800e-08b906156843
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660882767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1660882767
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3081477102
Short name T199
Test name
Test status
Simulation time 98566970 ps
CPU time 1.09 seconds
Started Mar 24 12:46:08 PM PDT 24
Finished Mar 24 12:46:10 PM PDT 24
Peak memory 196732 kb
Host smart-ca3aa8b2-e10f-4397-9040-aea9040a0f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081477102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3081477102
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2104418360
Short name T428
Test name
Test status
Simulation time 71764050 ps
CPU time 1.21 seconds
Started Mar 24 12:46:07 PM PDT 24
Finished Mar 24 12:46:09 PM PDT 24
Peak memory 195496 kb
Host smart-5dc20be3-755c-4f25-837b-ce5b72d98714
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104418360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2104418360
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1871756014
Short name T644
Test name
Test status
Simulation time 15287386309 ps
CPU time 66.95 seconds
Started Mar 24 12:46:09 PM PDT 24
Finished Mar 24 12:47:17 PM PDT 24
Peak memory 198192 kb
Host smart-16dc6ccf-bd4b-4946-8f8c-4d4f3501bef8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871756014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1871756014
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.3722160020
Short name T62
Test name
Test status
Simulation time 502374103546 ps
CPU time 2903.04 seconds
Started Mar 24 12:46:06 PM PDT 24
Finished Mar 24 01:34:31 PM PDT 24
Peak memory 206432 kb
Host smart-e8c3a169-9d41-438a-842e-41f98616731b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3722160020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.3722160020
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2789123998
Short name T311
Test name
Test status
Simulation time 14818924 ps
CPU time 0.59 seconds
Started Mar 24 12:46:09 PM PDT 24
Finished Mar 24 12:46:10 PM PDT 24
Peak memory 194824 kb
Host smart-b0154dd6-76b2-4ede-9fc9-5c6d1d17c705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789123998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2789123998
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3997077375
Short name T551
Test name
Test status
Simulation time 51519244 ps
CPU time 0.8 seconds
Started Mar 24 12:46:10 PM PDT 24
Finished Mar 24 12:46:11 PM PDT 24
Peak memory 196140 kb
Host smart-7697b646-0161-4377-bf3d-a99687bdad14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997077375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3997077375
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.788227572
Short name T159
Test name
Test status
Simulation time 944144578 ps
CPU time 16.13 seconds
Started Mar 24 12:46:05 PM PDT 24
Finished Mar 24 12:46:22 PM PDT 24
Peak memory 195524 kb
Host smart-a6d7e2da-ce54-4c4b-aa52-63396ffc082e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788227572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.788227572
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1442080721
Short name T516
Test name
Test status
Simulation time 192641610 ps
CPU time 1.1 seconds
Started Mar 24 12:46:09 PM PDT 24
Finished Mar 24 12:46:11 PM PDT 24
Peak memory 196424 kb
Host smart-60a73b5f-6e90-4fe9-891c-d3fa0a3d6f1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442080721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1442080721
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1638207818
Short name T274
Test name
Test status
Simulation time 76682033 ps
CPU time 1.16 seconds
Started Mar 24 12:46:09 PM PDT 24
Finished Mar 24 12:46:11 PM PDT 24
Peak memory 196784 kb
Host smart-31031592-0cbc-448a-8912-9ae3710a9932
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638207818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1638207818
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1872298911
Short name T592
Test name
Test status
Simulation time 81967316 ps
CPU time 1.63 seconds
Started Mar 24 12:46:08 PM PDT 24
Finished Mar 24 12:46:11 PM PDT 24
Peak memory 195960 kb
Host smart-38439359-78b8-4e27-839e-904ad759a6ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872298911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1872298911
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.151591559
Short name T267
Test name
Test status
Simulation time 33421240 ps
CPU time 0.9 seconds
Started Mar 24 12:46:06 PM PDT 24
Finished Mar 24 12:46:08 PM PDT 24
Peak memory 197156 kb
Host smart-05976ff0-c63d-485a-83b9-0d4b113ef44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151591559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.151591559
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3672844553
Short name T520
Test name
Test status
Simulation time 54977311 ps
CPU time 1.1 seconds
Started Mar 24 12:46:06 PM PDT 24
Finished Mar 24 12:46:09 PM PDT 24
Peak memory 196000 kb
Host smart-929f95a4-5fee-429e-896d-5eaaa9d88578
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672844553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3672844553
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.4755795
Short name T674
Test name
Test status
Simulation time 319246750 ps
CPU time 3.9 seconds
Started Mar 24 12:46:09 PM PDT 24
Finished Mar 24 12:46:14 PM PDT 24
Peak memory 197900 kb
Host smart-72507db9-d4cd-4819-bbae-e23e3b070053
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4755795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_wr
ites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rando
m_long_reg_writes_reg_reads.4755795
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3395556843
Short name T522
Test name
Test status
Simulation time 120173560 ps
CPU time 1.48 seconds
Started Mar 24 12:46:09 PM PDT 24
Finished Mar 24 12:46:11 PM PDT 24
Peak memory 195488 kb
Host smart-6f98efa1-1ff7-4a59-9800-7108698e83ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395556843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3395556843
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2037103760
Short name T153
Test name
Test status
Simulation time 151607114 ps
CPU time 1.33 seconds
Started Mar 24 12:46:07 PM PDT 24
Finished Mar 24 12:46:09 PM PDT 24
Peak memory 197128 kb
Host smart-b95302ab-8aeb-4e18-a3f4-5bcf0c5814c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037103760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2037103760
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1982623741
Short name T212
Test name
Test status
Simulation time 174003265380 ps
CPU time 198.36 seconds
Started Mar 24 12:46:07 PM PDT 24
Finished Mar 24 12:49:26 PM PDT 24
Peak memory 198240 kb
Host smart-be8dd458-77e4-4453-9a4d-1408347678d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982623741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1982623741
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3714998612
Short name T361
Test name
Test status
Simulation time 32000299 ps
CPU time 0.55 seconds
Started Mar 24 12:46:18 PM PDT 24
Finished Mar 24 12:46:18 PM PDT 24
Peak memory 193924 kb
Host smart-1c25e6f5-dae3-4191-86c9-15ef22623dca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714998612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3714998612
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3067614540
Short name T156
Test name
Test status
Simulation time 45194518 ps
CPU time 0.82 seconds
Started Mar 24 12:46:12 PM PDT 24
Finished Mar 24 12:46:13 PM PDT 24
Peak memory 196052 kb
Host smart-2ccca6b9-7c2e-478c-b9e7-48ea990b2003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067614540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3067614540
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2669745358
Short name T97
Test name
Test status
Simulation time 389557722 ps
CPU time 11.12 seconds
Started Mar 24 12:46:16 PM PDT 24
Finished Mar 24 12:46:27 PM PDT 24
Peak memory 196660 kb
Host smart-69588b59-bd3c-49d0-96b3-b58331fc1cd4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669745358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2669745358
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2389168523
Short name T19
Test name
Test status
Simulation time 71149079 ps
CPU time 0.89 seconds
Started Mar 24 12:46:14 PM PDT 24
Finished Mar 24 12:46:15 PM PDT 24
Peak memory 196108 kb
Host smart-9cdae9a4-3b7e-4a93-b076-f38ed7bccc73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389168523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2389168523
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.4137649888
Short name T266
Test name
Test status
Simulation time 75260524 ps
CPU time 1.16 seconds
Started Mar 24 12:46:12 PM PDT 24
Finished Mar 24 12:46:13 PM PDT 24
Peak memory 196016 kb
Host smart-c22b8f9b-3cab-4b5e-9792-9fb0a05c6361
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137649888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.4137649888
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2649051514
Short name T188
Test name
Test status
Simulation time 368982627 ps
CPU time 1.69 seconds
Started Mar 24 12:46:18 PM PDT 24
Finished Mar 24 12:46:20 PM PDT 24
Peak memory 196476 kb
Host smart-90c856b5-3687-438a-89cc-65b7bb5cb3da
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649051514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2649051514
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2152655413
Short name T290
Test name
Test status
Simulation time 709480151 ps
CPU time 3.43 seconds
Started Mar 24 12:46:14 PM PDT 24
Finished Mar 24 12:46:18 PM PDT 24
Peak memory 198108 kb
Host smart-a31e1dcf-a2b6-4f5d-8de3-602cc6af2e42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152655413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2152655413
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2637350579
Short name T233
Test name
Test status
Simulation time 21574502 ps
CPU time 0.77 seconds
Started Mar 24 12:46:16 PM PDT 24
Finished Mar 24 12:46:17 PM PDT 24
Peak memory 195284 kb
Host smart-f6485bb3-9d08-4079-bc4a-307dde2c4669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637350579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2637350579
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.4204412233
Short name T251
Test name
Test status
Simulation time 51571154 ps
CPU time 0.92 seconds
Started Mar 24 12:46:11 PM PDT 24
Finished Mar 24 12:46:12 PM PDT 24
Peak memory 195928 kb
Host smart-9a9ee9dc-afc7-4910-a72a-59628e03c5ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204412233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.4204412233
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2620020304
Short name T546
Test name
Test status
Simulation time 55246838 ps
CPU time 2.61 seconds
Started Mar 24 12:46:13 PM PDT 24
Finished Mar 24 12:46:16 PM PDT 24
Peak memory 197956 kb
Host smart-92ffe77e-2fb7-46a5-8d12-8e84c571d460
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620020304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2620020304
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1380541888
Short name T161
Test name
Test status
Simulation time 49977745 ps
CPU time 1.1 seconds
Started Mar 24 12:46:17 PM PDT 24
Finished Mar 24 12:46:19 PM PDT 24
Peak memory 196500 kb
Host smart-440c4ac2-7b2c-4623-a8d0-cbaa3f570c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380541888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1380541888
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1280751188
Short name T296
Test name
Test status
Simulation time 336675859 ps
CPU time 1.43 seconds
Started Mar 24 12:46:11 PM PDT 24
Finished Mar 24 12:46:13 PM PDT 24
Peak memory 196772 kb
Host smart-663de88e-5b06-4c95-b1e7-b13fb106fd59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280751188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1280751188
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1709746430
Short name T572
Test name
Test status
Simulation time 59178939675 ps
CPU time 183.1 seconds
Started Mar 24 12:46:11 PM PDT 24
Finished Mar 24 12:49:15 PM PDT 24
Peak memory 198212 kb
Host smart-b1e34d14-d2ef-4aa0-8bd4-8fb003b4d429
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709746430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1709746430
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1525371353
Short name T484
Test name
Test status
Simulation time 18643236 ps
CPU time 0.57 seconds
Started Mar 24 12:46:17 PM PDT 24
Finished Mar 24 12:46:18 PM PDT 24
Peak memory 194600 kb
Host smart-88036cb3-e64f-4a8d-9073-4246063656c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525371353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1525371353
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3731344929
Short name T334
Test name
Test status
Simulation time 33204293 ps
CPU time 0.78 seconds
Started Mar 24 12:46:12 PM PDT 24
Finished Mar 24 12:46:13 PM PDT 24
Peak memory 196120 kb
Host smart-16201b62-550b-44a5-a435-131ec293f3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731344929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3731344929
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1198725848
Short name T610
Test name
Test status
Simulation time 222784689 ps
CPU time 8.03 seconds
Started Mar 24 12:46:11 PM PDT 24
Finished Mar 24 12:46:19 PM PDT 24
Peak memory 196848 kb
Host smart-224e87f8-69e0-4723-8685-f1c36d8324ea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198725848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1198725848
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3333484218
Short name T584
Test name
Test status
Simulation time 67952716 ps
CPU time 0.67 seconds
Started Mar 24 12:46:19 PM PDT 24
Finished Mar 24 12:46:20 PM PDT 24
Peak memory 194796 kb
Host smart-29b95def-409d-4ce1-a3e6-0c505011cb1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333484218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3333484218
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3169691033
Short name T286
Test name
Test status
Simulation time 96270098 ps
CPU time 1.37 seconds
Started Mar 24 12:46:13 PM PDT 24
Finished Mar 24 12:46:15 PM PDT 24
Peak memory 198056 kb
Host smart-6f4f0d98-4a88-4adf-aafb-e15b2dc05742
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169691033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3169691033
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3007742361
Short name T725
Test name
Test status
Simulation time 37637110 ps
CPU time 1.45 seconds
Started Mar 24 12:46:17 PM PDT 24
Finished Mar 24 12:46:18 PM PDT 24
Peak memory 196332 kb
Host smart-b677df6a-ad58-4242-9414-ed16036451cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007742361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3007742361
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1614890473
Short name T376
Test name
Test status
Simulation time 88181616 ps
CPU time 2.06 seconds
Started Mar 24 12:46:11 PM PDT 24
Finished Mar 24 12:46:13 PM PDT 24
Peak memory 195972 kb
Host smart-1a55d7d4-a95a-401f-8245-9eda85cdfa50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614890473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1614890473
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.4157666575
Short name T134
Test name
Test status
Simulation time 137441345 ps
CPU time 1.29 seconds
Started Mar 24 12:46:16 PM PDT 24
Finished Mar 24 12:46:17 PM PDT 24
Peak memory 197036 kb
Host smart-61e95d50-01a7-4a2a-b52b-b58452abe072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157666575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.4157666575
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.954816871
Short name T471
Test name
Test status
Simulation time 39613427 ps
CPU time 1.03 seconds
Started Mar 24 12:46:13 PM PDT 24
Finished Mar 24 12:46:14 PM PDT 24
Peak memory 196544 kb
Host smart-e99b67f7-6ef1-4deb-aa81-d9063f1cac91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954816871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.954816871
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.322392607
Short name T168
Test name
Test status
Simulation time 124985034 ps
CPU time 2.25 seconds
Started Mar 24 12:46:14 PM PDT 24
Finished Mar 24 12:46:17 PM PDT 24
Peak memory 197848 kb
Host smart-61c97522-7cd1-4969-a3e1-720c2cedf8f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322392607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.322392607
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2287923538
Short name T135
Test name
Test status
Simulation time 1242984136 ps
CPU time 1.42 seconds
Started Mar 24 12:46:11 PM PDT 24
Finished Mar 24 12:46:13 PM PDT 24
Peak memory 196700 kb
Host smart-beb5368a-1490-4a88-ab89-9366e4f44f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287923538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2287923538
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3133070535
Short name T297
Test name
Test status
Simulation time 38230535 ps
CPU time 0.81 seconds
Started Mar 24 12:46:13 PM PDT 24
Finished Mar 24 12:46:14 PM PDT 24
Peak memory 195796 kb
Host smart-a4f4ab49-9a67-4f1e-bde7-f70524eb7ff8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133070535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3133070535
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.372997678
Short name T709
Test name
Test status
Simulation time 15651475066 ps
CPU time 50.21 seconds
Started Mar 24 12:46:17 PM PDT 24
Finished Mar 24 12:47:07 PM PDT 24
Peak memory 198256 kb
Host smart-d33d928e-193c-4180-860d-986a93ecb31d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372997678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.372997678
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.4239301462
Short name T481
Test name
Test status
Simulation time 14000271 ps
CPU time 0.62 seconds
Started Mar 24 12:45:35 PM PDT 24
Finished Mar 24 12:45:35 PM PDT 24
Peak memory 194840 kb
Host smart-9ac4d4b5-8d1d-4acc-9beb-a252104dfd4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239301462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.4239301462
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.402383369
Short name T380
Test name
Test status
Simulation time 89582520 ps
CPU time 0.81 seconds
Started Mar 24 12:45:13 PM PDT 24
Finished Mar 24 12:45:14 PM PDT 24
Peak memory 195472 kb
Host smart-3da3c4c4-240a-43e8-88b7-41fc737184ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402383369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.402383369
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1980191049
Short name T279
Test name
Test status
Simulation time 943680787 ps
CPU time 5.46 seconds
Started Mar 24 12:45:26 PM PDT 24
Finished Mar 24 12:45:32 PM PDT 24
Peak memory 197000 kb
Host smart-9826c08e-4558-42da-b33b-f979d40e29f8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980191049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1980191049
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.304097791
Short name T470
Test name
Test status
Simulation time 76664461 ps
CPU time 0.91 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 12:45:10 PM PDT 24
Peak memory 195976 kb
Host smart-efc914fa-c13e-4b83-bc56-8d8dcff8e23f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304097791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.304097791
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.4053403
Short name T276
Test name
Test status
Simulation time 32081782 ps
CPU time 0.82 seconds
Started Mar 24 12:45:26 PM PDT 24
Finished Mar 24 12:45:27 PM PDT 24
Peak memory 195680 kb
Host smart-4701485c-d447-43ed-8dcc-0e15e2094e0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.4053403
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3371849404
Short name T397
Test name
Test status
Simulation time 122936698 ps
CPU time 2.47 seconds
Started Mar 24 12:45:22 PM PDT 24
Finished Mar 24 12:45:25 PM PDT 24
Peak memory 197972 kb
Host smart-52f0c82a-36de-41a5-82ea-926bc205236d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371849404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3371849404
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2849547890
Short name T224
Test name
Test status
Simulation time 33967224 ps
CPU time 1.08 seconds
Started Mar 24 12:45:07 PM PDT 24
Finished Mar 24 12:45:08 PM PDT 24
Peak memory 196040 kb
Host smart-2f8100d8-c129-43fe-98d8-29002f9a6906
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849547890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2849547890
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1549122557
Short name T678
Test name
Test status
Simulation time 207824605 ps
CPU time 1.18 seconds
Started Mar 24 12:45:18 PM PDT 24
Finished Mar 24 12:45:20 PM PDT 24
Peak memory 197060 kb
Host smart-de5fbef0-ab14-4acf-91e6-26402d5be10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549122557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1549122557
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1551513527
Short name T682
Test name
Test status
Simulation time 28911220 ps
CPU time 0.67 seconds
Started Mar 24 12:45:16 PM PDT 24
Finished Mar 24 12:45:17 PM PDT 24
Peak memory 194304 kb
Host smart-ba4ed169-38a2-457d-a5f5-ffe9ec220daf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551513527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1551513527
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1475720028
Short name T627
Test name
Test status
Simulation time 1458641896 ps
CPU time 5.84 seconds
Started Mar 24 12:45:19 PM PDT 24
Finished Mar 24 12:45:25 PM PDT 24
Peak memory 197908 kb
Host smart-651916ba-bd2d-437f-b25d-30395bfff9e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475720028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1475720028
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_smoke.3926764473
Short name T690
Test name
Test status
Simulation time 202060294 ps
CPU time 0.87 seconds
Started Mar 24 12:45:17 PM PDT 24
Finished Mar 24 12:45:18 PM PDT 24
Peak memory 196532 kb
Host smart-4ffa3e15-0b86-4452-9d84-d0fc7355b8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926764473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3926764473
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.206443297
Short name T408
Test name
Test status
Simulation time 55139528 ps
CPU time 1.04 seconds
Started Mar 24 12:45:10 PM PDT 24
Finished Mar 24 12:45:11 PM PDT 24
Peak memory 195564 kb
Host smart-41de1550-1dd1-4c61-8df2-99accacd0e5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206443297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.206443297
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1999025687
Short name T176
Test name
Test status
Simulation time 13247109865 ps
CPU time 182.7 seconds
Started Mar 24 12:45:23 PM PDT 24
Finished Mar 24 12:48:26 PM PDT 24
Peak memory 198164 kb
Host smart-6e166987-4df1-45bf-a0e5-71851ccc49ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999025687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1999025687
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.3840249241
Short name T100
Test name
Test status
Simulation time 526572269756 ps
CPU time 1692.55 seconds
Started Mar 24 12:45:22 PM PDT 24
Finished Mar 24 01:13:35 PM PDT 24
Peak memory 198132 kb
Host smart-ab8ae3fb-5521-4182-8470-01cf26027d48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3840249241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.3840249241
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1553655892
Short name T151
Test name
Test status
Simulation time 46529206 ps
CPU time 0.57 seconds
Started Mar 24 12:46:19 PM PDT 24
Finished Mar 24 12:46:20 PM PDT 24
Peak memory 193992 kb
Host smart-100c6642-cd34-4662-a70b-0a8c10c133ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553655892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1553655892
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3705419542
Short name T181
Test name
Test status
Simulation time 114722934 ps
CPU time 0.78 seconds
Started Mar 24 12:46:18 PM PDT 24
Finished Mar 24 12:46:19 PM PDT 24
Peak memory 194100 kb
Host smart-d1e02736-ab8d-469a-9fc1-bd87755591dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705419542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3705419542
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2248466122
Short name T285
Test name
Test status
Simulation time 214581824 ps
CPU time 5.74 seconds
Started Mar 24 12:46:19 PM PDT 24
Finished Mar 24 12:46:25 PM PDT 24
Peak memory 196732 kb
Host smart-3d8872a5-86c2-4d86-9b05-7e94358182cb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248466122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2248466122
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3121873012
Short name T492
Test name
Test status
Simulation time 249987862 ps
CPU time 0.94 seconds
Started Mar 24 12:46:16 PM PDT 24
Finished Mar 24 12:46:17 PM PDT 24
Peak memory 196656 kb
Host smart-30d4d1ef-b8ea-470f-b451-52ea081d460b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121873012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3121873012
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1408297242
Short name T325
Test name
Test status
Simulation time 197499565 ps
CPU time 1.3 seconds
Started Mar 24 12:46:17 PM PDT 24
Finished Mar 24 12:46:19 PM PDT 24
Peak memory 196884 kb
Host smart-db89c7af-0e11-4bfe-ab1f-ffca79571e19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408297242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1408297242
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.412898276
Short name T639
Test name
Test status
Simulation time 369869612 ps
CPU time 3.24 seconds
Started Mar 24 12:46:17 PM PDT 24
Finished Mar 24 12:46:20 PM PDT 24
Peak memory 198048 kb
Host smart-ec4f8bbb-60ca-4fc1-b5aa-ac0cb14b9da3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412898276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.412898276
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3399885982
Short name T256
Test name
Test status
Simulation time 198918534 ps
CPU time 2 seconds
Started Mar 24 12:46:19 PM PDT 24
Finished Mar 24 12:46:22 PM PDT 24
Peak memory 196684 kb
Host smart-3011a8ac-fbaa-4513-83c2-2c9e06c94381
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399885982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3399885982
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.355545078
Short name T423
Test name
Test status
Simulation time 52889554 ps
CPU time 1.22 seconds
Started Mar 24 12:46:20 PM PDT 24
Finished Mar 24 12:46:22 PM PDT 24
Peak memory 196516 kb
Host smart-ab0cf051-9d02-41de-be77-332297a646e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355545078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.355545078
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2215574621
Short name T534
Test name
Test status
Simulation time 61826642 ps
CPU time 0.87 seconds
Started Mar 24 12:46:17 PM PDT 24
Finished Mar 24 12:46:18 PM PDT 24
Peak memory 196788 kb
Host smart-614c0f04-86de-42bb-a8a1-66aab5946039
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215574621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2215574621
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2276507483
Short name T174
Test name
Test status
Simulation time 207712828 ps
CPU time 4.91 seconds
Started Mar 24 12:46:17 PM PDT 24
Finished Mar 24 12:46:23 PM PDT 24
Peak memory 198004 kb
Host smart-35f3681d-7098-4940-8b3c-5ac344632699
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276507483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2276507483
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1554595311
Short name T306
Test name
Test status
Simulation time 112389291 ps
CPU time 1.2 seconds
Started Mar 24 12:46:15 PM PDT 24
Finished Mar 24 12:46:17 PM PDT 24
Peak memory 195640 kb
Host smart-f258ea33-b88b-4f2a-946d-d379d5714702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554595311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1554595311
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3592341345
Short name T713
Test name
Test status
Simulation time 237391074 ps
CPU time 1.23 seconds
Started Mar 24 12:46:18 PM PDT 24
Finished Mar 24 12:46:19 PM PDT 24
Peak memory 198016 kb
Host smart-aa863eb9-6417-4f0d-952c-c565065d91eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592341345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3592341345
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3952116982
Short name T723
Test name
Test status
Simulation time 151493172008 ps
CPU time 106.05 seconds
Started Mar 24 12:46:20 PM PDT 24
Finished Mar 24 12:48:07 PM PDT 24
Peak memory 198080 kb
Host smart-b17c17ca-e0b5-415c-867c-ffa9fba139bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952116982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3952116982
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.84754336
Short name T65
Test name
Test status
Simulation time 5193706635 ps
CPU time 161.71 seconds
Started Mar 24 12:46:19 PM PDT 24
Finished Mar 24 12:49:01 PM PDT 24
Peak memory 198116 kb
Host smart-93ef1084-6556-44bf-8188-f35134ee842a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=84754336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.84754336
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1244544680
Short name T227
Test name
Test status
Simulation time 11181932 ps
CPU time 0.55 seconds
Started Mar 24 12:46:22 PM PDT 24
Finished Mar 24 12:46:23 PM PDT 24
Peak memory 192736 kb
Host smart-c03fee4a-0c99-46d4-84ca-ca6f20b2eea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244544680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1244544680
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.660125383
Short name T483
Test name
Test status
Simulation time 21705792 ps
CPU time 0.69 seconds
Started Mar 24 12:46:19 PM PDT 24
Finished Mar 24 12:46:20 PM PDT 24
Peak memory 194236 kb
Host smart-7c1aa18d-360b-448d-8b4e-3d70e572f17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660125383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.660125383
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2505003386
Short name T411
Test name
Test status
Simulation time 3903759279 ps
CPU time 23.42 seconds
Started Mar 24 12:46:27 PM PDT 24
Finished Mar 24 12:46:51 PM PDT 24
Peak memory 196588 kb
Host smart-40e5fd40-53b3-4606-915a-ee0024485cc9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505003386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2505003386
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2192668553
Short name T561
Test name
Test status
Simulation time 104184966 ps
CPU time 0.65 seconds
Started Mar 24 12:46:23 PM PDT 24
Finished Mar 24 12:46:24 PM PDT 24
Peak memory 194596 kb
Host smart-b610efc3-7fd0-4102-a0d4-b1b57d4d7573
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192668553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2192668553
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2549334205
Short name T109
Test name
Test status
Simulation time 104470437 ps
CPU time 1.36 seconds
Started Mar 24 12:46:16 PM PDT 24
Finished Mar 24 12:46:17 PM PDT 24
Peak memory 197104 kb
Host smart-7bc18515-e552-4508-9c2b-4a33e4fb7916
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549334205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2549334205
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1111997653
Short name T216
Test name
Test status
Simulation time 53575445 ps
CPU time 1.18 seconds
Started Mar 24 12:46:24 PM PDT 24
Finished Mar 24 12:46:25 PM PDT 24
Peak memory 198004 kb
Host smart-ad96b393-75e0-4791-b59a-4e1464cfb359
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111997653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1111997653
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.316537536
Short name T189
Test name
Test status
Simulation time 430199519 ps
CPU time 2.07 seconds
Started Mar 24 12:46:21 PM PDT 24
Finished Mar 24 12:46:23 PM PDT 24
Peak memory 196160 kb
Host smart-927575f7-2038-4540-9cf3-859ef2ec2006
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316537536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
316537536
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2419268575
Short name T649
Test name
Test status
Simulation time 125916655 ps
CPU time 1.29 seconds
Started Mar 24 12:46:19 PM PDT 24
Finished Mar 24 12:46:20 PM PDT 24
Peak memory 196840 kb
Host smart-286858f4-93ab-463a-92b5-8f030b36fe19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419268575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2419268575
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2142058514
Short name T245
Test name
Test status
Simulation time 40246372 ps
CPU time 0.97 seconds
Started Mar 24 12:46:18 PM PDT 24
Finished Mar 24 12:46:19 PM PDT 24
Peak memory 196712 kb
Host smart-2b455068-28ec-48f2-9cbd-24ad01a58f1b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142058514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2142058514
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2162080459
Short name T688
Test name
Test status
Simulation time 92261935 ps
CPU time 1.76 seconds
Started Mar 24 12:46:24 PM PDT 24
Finished Mar 24 12:46:26 PM PDT 24
Peak memory 197968 kb
Host smart-a70cc0a0-c1e4-4fdf-94ae-8955add7536c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162080459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2162080459
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2201965886
Short name T443
Test name
Test status
Simulation time 454026786 ps
CPU time 1.13 seconds
Started Mar 24 12:46:20 PM PDT 24
Finished Mar 24 12:46:22 PM PDT 24
Peak memory 195504 kb
Host smart-d22673f6-0353-4470-8099-ea74f7aaa78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201965886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2201965886
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3202427911
Short name T704
Test name
Test status
Simulation time 132523494 ps
CPU time 0.81 seconds
Started Mar 24 12:46:18 PM PDT 24
Finished Mar 24 12:46:19 PM PDT 24
Peak memory 195956 kb
Host smart-55e445ec-7969-4799-9100-82803cacd1ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202427911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3202427911
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.361750561
Short name T591
Test name
Test status
Simulation time 10106078363 ps
CPU time 136.25 seconds
Started Mar 24 12:46:23 PM PDT 24
Finished Mar 24 12:48:39 PM PDT 24
Peak memory 198112 kb
Host smart-f8ea8aa5-590a-4b3b-9a17-b269d717aee8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361750561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.361750561
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1497857297
Short name T102
Test name
Test status
Simulation time 45878316337 ps
CPU time 899.17 seconds
Started Mar 24 12:46:25 PM PDT 24
Finished Mar 24 01:01:24 PM PDT 24
Peak memory 198276 kb
Host smart-67c8b25b-839e-423f-8362-9f5555e9753f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1497857297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1497857297
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3691314219
Short name T705
Test name
Test status
Simulation time 12988646 ps
CPU time 0.6 seconds
Started Mar 24 12:46:23 PM PDT 24
Finished Mar 24 12:46:24 PM PDT 24
Peak memory 193916 kb
Host smart-6e4c627c-5d67-4621-8536-69a0f2d15fe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691314219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3691314219
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.900790940
Short name T284
Test name
Test status
Simulation time 89807693 ps
CPU time 0.97 seconds
Started Mar 24 12:46:23 PM PDT 24
Finished Mar 24 12:46:24 PM PDT 24
Peak memory 195904 kb
Host smart-6c7f0852-f380-4a59-bd0d-ccc5090bfe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900790940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.900790940
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.4191328301
Short name T328
Test name
Test status
Simulation time 230285576 ps
CPU time 12.42 seconds
Started Mar 24 12:46:23 PM PDT 24
Finished Mar 24 12:46:36 PM PDT 24
Peak memory 195528 kb
Host smart-1e6f0ff4-3470-4db5-957e-84d0d4bc7405
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191328301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.4191328301
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3479491335
Short name T637
Test name
Test status
Simulation time 33850244 ps
CPU time 0.69 seconds
Started Mar 24 12:46:25 PM PDT 24
Finished Mar 24 12:46:26 PM PDT 24
Peak memory 194620 kb
Host smart-5e5009e8-5da9-4eea-9930-0fafd90fa8a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479491335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3479491335
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2943181362
Short name T363
Test name
Test status
Simulation time 205449370 ps
CPU time 1.1 seconds
Started Mar 24 12:46:30 PM PDT 24
Finished Mar 24 12:46:32 PM PDT 24
Peak memory 196048 kb
Host smart-9845f6c2-6804-4d92-b893-3d9f9f0b2c1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943181362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2943181362
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1015531847
Short name T658
Test name
Test status
Simulation time 245023783 ps
CPU time 2.2 seconds
Started Mar 24 12:46:26 PM PDT 24
Finished Mar 24 12:46:28 PM PDT 24
Peak memory 198004 kb
Host smart-ee287fc4-5331-4890-92b2-3aa698b7e2e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015531847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1015531847
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.982017455
Short name T603
Test name
Test status
Simulation time 124624181 ps
CPU time 2.64 seconds
Started Mar 24 12:46:22 PM PDT 24
Finished Mar 24 12:46:25 PM PDT 24
Peak memory 195764 kb
Host smart-7c185c80-d8d0-47ac-bcbb-88774b691c8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982017455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
982017455
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2580572325
Short name T589
Test name
Test status
Simulation time 784754623 ps
CPU time 0.93 seconds
Started Mar 24 12:46:22 PM PDT 24
Finished Mar 24 12:46:23 PM PDT 24
Peak memory 195988 kb
Host smart-a6b5e609-01ff-4a6e-b96b-682fdb5dca47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580572325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2580572325
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3875094183
Short name T545
Test name
Test status
Simulation time 28124403 ps
CPU time 0.75 seconds
Started Mar 24 12:46:27 PM PDT 24
Finished Mar 24 12:46:28 PM PDT 24
Peak memory 196084 kb
Host smart-109054ab-6fd7-4fdd-a984-54170dec92d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875094183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3875094183
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2470413732
Short name T8
Test name
Test status
Simulation time 481437017 ps
CPU time 5.93 seconds
Started Mar 24 12:46:25 PM PDT 24
Finished Mar 24 12:46:31 PM PDT 24
Peak memory 197932 kb
Host smart-7b3bbee7-f0d2-4a3d-abfd-0f6268ed997e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470413732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2470413732
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3786957505
Short name T528
Test name
Test status
Simulation time 39029534 ps
CPU time 0.92 seconds
Started Mar 24 12:46:26 PM PDT 24
Finished Mar 24 12:46:27 PM PDT 24
Peak memory 196552 kb
Host smart-91309ff7-230e-4b27-a819-4b690238c269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786957505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3786957505
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.4111257496
Short name T518
Test name
Test status
Simulation time 373308661 ps
CPU time 1.38 seconds
Started Mar 24 12:46:23 PM PDT 24
Finished Mar 24 12:46:25 PM PDT 24
Peak memory 196784 kb
Host smart-f11f37d5-9385-4974-b394-7ce18df73611
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111257496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.4111257496
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.505393545
Short name T402
Test name
Test status
Simulation time 10252395990 ps
CPU time 27.05 seconds
Started Mar 24 12:46:24 PM PDT 24
Finished Mar 24 12:46:51 PM PDT 24
Peak memory 198212 kb
Host smart-d466658a-e7b0-4344-8396-98a3ec7d936a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505393545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.505393545
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1258416543
Short name T173
Test name
Test status
Simulation time 15777780 ps
CPU time 0.6 seconds
Started Mar 24 12:46:31 PM PDT 24
Finished Mar 24 12:46:32 PM PDT 24
Peak memory 194320 kb
Host smart-6fc64038-044e-4a5e-a2d6-195f418727ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258416543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1258416543
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.539172755
Short name T465
Test name
Test status
Simulation time 113454137 ps
CPU time 0.91 seconds
Started Mar 24 12:46:27 PM PDT 24
Finished Mar 24 12:46:28 PM PDT 24
Peak memory 195676 kb
Host smart-f716d9d2-4d06-4cbb-bab7-f3606987c9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539172755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.539172755
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2558537045
Short name T262
Test name
Test status
Simulation time 2386048345 ps
CPU time 21.75 seconds
Started Mar 24 12:46:32 PM PDT 24
Finished Mar 24 12:46:55 PM PDT 24
Peak memory 196392 kb
Host smart-aa358df0-abc6-4e9d-88c6-5adffda12506
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558537045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2558537045
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.163738827
Short name T157
Test name
Test status
Simulation time 234757626 ps
CPU time 0.89 seconds
Started Mar 24 12:46:28 PM PDT 24
Finished Mar 24 12:46:29 PM PDT 24
Peak memory 196660 kb
Host smart-83e71924-4e18-491b-8e57-f428f3e474ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163738827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.163738827
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.72338756
Short name T646
Test name
Test status
Simulation time 37809371 ps
CPU time 1.17 seconds
Started Mar 24 12:46:30 PM PDT 24
Finished Mar 24 12:46:32 PM PDT 24
Peak memory 196740 kb
Host smart-2abbfd6e-848a-454a-90ca-314a922a0a2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72338756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.72338756
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.408797287
Short name T491
Test name
Test status
Simulation time 75842661 ps
CPU time 3.09 seconds
Started Mar 24 12:46:30 PM PDT 24
Finished Mar 24 12:46:34 PM PDT 24
Peak memory 198100 kb
Host smart-a890d2e4-1159-4907-ae6b-4aab1d4c551e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408797287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.gpio_intr_with_filter_rand_intr_event.408797287
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1534325806
Short name T293
Test name
Test status
Simulation time 475997540 ps
CPU time 3.43 seconds
Started Mar 24 12:46:28 PM PDT 24
Finished Mar 24 12:46:31 PM PDT 24
Peak memory 196516 kb
Host smart-0989d1ef-612d-4074-a77d-86c080cf507c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534325806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1534325806
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1846227293
Short name T171
Test name
Test status
Simulation time 78286522 ps
CPU time 0.74 seconds
Started Mar 24 12:46:24 PM PDT 24
Finished Mar 24 12:46:24 PM PDT 24
Peak memory 195428 kb
Host smart-411db858-80dd-4324-a845-d7a47b9dd69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846227293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1846227293
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1091925748
Short name T234
Test name
Test status
Simulation time 87031659 ps
CPU time 1.26 seconds
Started Mar 24 12:46:23 PM PDT 24
Finished Mar 24 12:46:25 PM PDT 24
Peak memory 198132 kb
Host smart-8ce2890c-44b4-418d-be6c-8e2b57eb1963
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091925748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1091925748
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3515479654
Short name T6
Test name
Test status
Simulation time 340084925 ps
CPU time 4.06 seconds
Started Mar 24 12:46:29 PM PDT 24
Finished Mar 24 12:46:33 PM PDT 24
Peak memory 197932 kb
Host smart-a9593626-9ee3-447e-8768-f01b534618ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515479654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3515479654
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1042586468
Short name T225
Test name
Test status
Simulation time 61641084 ps
CPU time 0.83 seconds
Started Mar 24 12:46:22 PM PDT 24
Finished Mar 24 12:46:23 PM PDT 24
Peak memory 196416 kb
Host smart-c8d79c16-115f-4ae1-99af-967435391a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042586468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1042586468
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3476702937
Short name T599
Test name
Test status
Simulation time 81674232 ps
CPU time 1.31 seconds
Started Mar 24 12:46:24 PM PDT 24
Finished Mar 24 12:46:26 PM PDT 24
Peak memory 197912 kb
Host smart-de3cc719-26a0-40e9-bb7b-ac5b3d4aeb33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476702937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3476702937
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.668171661
Short name T167
Test name
Test status
Simulation time 47578902290 ps
CPU time 101.93 seconds
Started Mar 24 12:46:31 PM PDT 24
Finished Mar 24 12:48:13 PM PDT 24
Peak memory 198136 kb
Host smart-104634b7-59d9-4e31-afc9-d2134f0594e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668171661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.668171661
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2135798225
Short name T303
Test name
Test status
Simulation time 103865624138 ps
CPU time 724.88 seconds
Started Mar 24 12:46:28 PM PDT 24
Finished Mar 24 12:58:33 PM PDT 24
Peak memory 198208 kb
Host smart-9514b98e-3ae9-4370-a692-bb4ec2083731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2135798225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2135798225
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1950840780
Short name T667
Test name
Test status
Simulation time 22387256 ps
CPU time 0.57 seconds
Started Mar 24 12:46:31 PM PDT 24
Finished Mar 24 12:46:33 PM PDT 24
Peak memory 193936 kb
Host smart-32f008a8-c91a-43ae-ac4f-83371b1a723f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950840780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1950840780
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2882069737
Short name T237
Test name
Test status
Simulation time 50250698 ps
CPU time 0.74 seconds
Started Mar 24 12:46:34 PM PDT 24
Finished Mar 24 12:46:36 PM PDT 24
Peak memory 195948 kb
Host smart-9ee4e6fa-82e0-4799-b642-997ad05504d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882069737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2882069737
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2356926026
Short name T505
Test name
Test status
Simulation time 1858822618 ps
CPU time 18.6 seconds
Started Mar 24 12:46:27 PM PDT 24
Finished Mar 24 12:46:45 PM PDT 24
Peak memory 197128 kb
Host smart-ec137693-999b-495d-9021-88d4f3d642f8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356926026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2356926026
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1970591627
Short name T601
Test name
Test status
Simulation time 42603769 ps
CPU time 0.71 seconds
Started Mar 24 12:46:30 PM PDT 24
Finished Mar 24 12:46:31 PM PDT 24
Peak memory 194812 kb
Host smart-55b00f50-a2e1-441a-b1b2-d83e72a131f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970591627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1970591627
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.4180844368
Short name T28
Test name
Test status
Simulation time 325163671 ps
CPU time 1.31 seconds
Started Mar 24 12:46:28 PM PDT 24
Finished Mar 24 12:46:30 PM PDT 24
Peak memory 195836 kb
Host smart-bd47730e-1081-461d-be19-8464216d9157
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180844368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.4180844368
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1815866377
Short name T226
Test name
Test status
Simulation time 90700570 ps
CPU time 3.42 seconds
Started Mar 24 12:46:31 PM PDT 24
Finished Mar 24 12:46:36 PM PDT 24
Peak memory 196456 kb
Host smart-9c5e22ca-1f03-4fb5-ab0b-83097b3def9d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815866377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1815866377
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.4112669416
Short name T466
Test name
Test status
Simulation time 236453422 ps
CPU time 2.34 seconds
Started Mar 24 12:46:34 PM PDT 24
Finished Mar 24 12:46:37 PM PDT 24
Peak memory 197112 kb
Host smart-cbbca406-ec82-4e39-8aaa-3cb9550fdb2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112669416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.4112669416
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.100553224
Short name T708
Test name
Test status
Simulation time 263589407 ps
CPU time 1.13 seconds
Started Mar 24 12:46:28 PM PDT 24
Finished Mar 24 12:46:29 PM PDT 24
Peak memory 196592 kb
Host smart-3f0c3bba-44b6-46d3-a3f6-bf532e93462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100553224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.100553224
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.318506749
Short name T26
Test name
Test status
Simulation time 138645429 ps
CPU time 0.86 seconds
Started Mar 24 12:46:27 PM PDT 24
Finished Mar 24 12:46:28 PM PDT 24
Peak memory 196672 kb
Host smart-6d0cffaa-e02b-4c66-9306-a27285232fbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318506749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.318506749
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1950719641
Short name T164
Test name
Test status
Simulation time 134922366 ps
CPU time 3.31 seconds
Started Mar 24 12:46:28 PM PDT 24
Finished Mar 24 12:46:32 PM PDT 24
Peak memory 197948 kb
Host smart-501ed092-2c09-4b56-a7ef-b0513eba30be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950719641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1950719641
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.371103053
Short name T308
Test name
Test status
Simulation time 39734660 ps
CPU time 1.29 seconds
Started Mar 24 12:46:34 PM PDT 24
Finished Mar 24 12:46:37 PM PDT 24
Peak memory 195512 kb
Host smart-192700b2-ffcb-475b-b53f-e2dee07830a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371103053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.371103053
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.331634208
Short name T536
Test name
Test status
Simulation time 246033782 ps
CPU time 1.17 seconds
Started Mar 24 12:46:31 PM PDT 24
Finished Mar 24 12:46:34 PM PDT 24
Peak memory 195872 kb
Host smart-71d0c89d-ea2b-45cb-b2e6-e0268d07657c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331634208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.331634208
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1339604279
Short name T538
Test name
Test status
Simulation time 3440640359 ps
CPU time 80.58 seconds
Started Mar 24 12:46:28 PM PDT 24
Finished Mar 24 12:47:49 PM PDT 24
Peak memory 198008 kb
Host smart-db38c251-47b8-44c5-877a-4e6d88f60c70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339604279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1339604279
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.1270157407
Short name T480
Test name
Test status
Simulation time 68859797703 ps
CPU time 1298.41 seconds
Started Mar 24 12:46:33 PM PDT 24
Finished Mar 24 01:08:12 PM PDT 24
Peak memory 198132 kb
Host smart-d7e69b01-4a8e-42a8-ad1d-0830ebfd2353
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1270157407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.1270157407
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1591152051
Short name T332
Test name
Test status
Simulation time 16221720 ps
CPU time 0.57 seconds
Started Mar 24 12:46:33 PM PDT 24
Finished Mar 24 12:46:34 PM PDT 24
Peak memory 194028 kb
Host smart-36ca6e2e-73e8-4746-9314-7aaa647ae33b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591152051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1591152051
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2562530145
Short name T487
Test name
Test status
Simulation time 35640907 ps
CPU time 0.87 seconds
Started Mar 24 12:46:33 PM PDT 24
Finished Mar 24 12:46:35 PM PDT 24
Peak memory 195452 kb
Host smart-494f841b-a257-498e-8425-004090791e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562530145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2562530145
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2375641757
Short name T54
Test name
Test status
Simulation time 2201881699 ps
CPU time 13.22 seconds
Started Mar 24 12:46:36 PM PDT 24
Finished Mar 24 12:46:51 PM PDT 24
Peak memory 197144 kb
Host smart-cf4317ce-1734-4e30-b290-b8de15cf6ebc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375641757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2375641757
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.744695760
Short name T271
Test name
Test status
Simulation time 247938571 ps
CPU time 0.89 seconds
Started Mar 24 12:46:34 PM PDT 24
Finished Mar 24 12:46:36 PM PDT 24
Peak memory 197748 kb
Host smart-98c3dad0-52c5-4028-b397-4fe200b718c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744695760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.744695760
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2708978623
Short name T568
Test name
Test status
Simulation time 215755537 ps
CPU time 1.09 seconds
Started Mar 24 12:46:39 PM PDT 24
Finished Mar 24 12:46:40 PM PDT 24
Peak memory 195760 kb
Host smart-47aedd51-3668-4b6d-9ec1-df788cc2892a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708978623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2708978623
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.29501788
Short name T197
Test name
Test status
Simulation time 335363424 ps
CPU time 3.47 seconds
Started Mar 24 12:46:34 PM PDT 24
Finished Mar 24 12:46:38 PM PDT 24
Peak memory 198048 kb
Host smart-4600bb5c-478f-4744-94aa-70845bee053d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29501788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.gpio_intr_with_filter_rand_intr_event.29501788
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2345989193
Short name T154
Test name
Test status
Simulation time 594947994 ps
CPU time 3.44 seconds
Started Mar 24 12:46:37 PM PDT 24
Finished Mar 24 12:46:42 PM PDT 24
Peak memory 197244 kb
Host smart-98e4d003-6e51-4ebc-9cdb-5dc948d0f844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345989193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2345989193
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1237757794
Short name T248
Test name
Test status
Simulation time 228491085 ps
CPU time 0.94 seconds
Started Mar 24 12:46:27 PM PDT 24
Finished Mar 24 12:46:28 PM PDT 24
Peak memory 196724 kb
Host smart-16b012f4-91d0-4687-9eb2-bc45041553ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237757794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1237757794
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3162815726
Short name T549
Test name
Test status
Simulation time 373987983 ps
CPU time 1.34 seconds
Started Mar 24 12:46:28 PM PDT 24
Finished Mar 24 12:46:29 PM PDT 24
Peak memory 198048 kb
Host smart-b357dffd-09cc-4e34-b6b0-9e0f54e94623
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162815726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3162815726
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2144700792
Short name T696
Test name
Test status
Simulation time 283997806 ps
CPU time 3.24 seconds
Started Mar 24 12:46:38 PM PDT 24
Finished Mar 24 12:46:43 PM PDT 24
Peak memory 197984 kb
Host smart-10051af2-5fa0-4496-87ab-1d60871e14de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144700792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2144700792
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3178805147
Short name T513
Test name
Test status
Simulation time 207424485 ps
CPU time 1.21 seconds
Started Mar 24 12:46:27 PM PDT 24
Finished Mar 24 12:46:28 PM PDT 24
Peak memory 195564 kb
Host smart-f64907fc-2a13-4805-92a5-3df4f912d169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178805147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3178805147
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3610161344
Short name T617
Test name
Test status
Simulation time 427515862 ps
CPU time 1.15 seconds
Started Mar 24 12:46:29 PM PDT 24
Finished Mar 24 12:46:31 PM PDT 24
Peak memory 195740 kb
Host smart-ea6480b5-4470-432b-b2c0-dbb122efa391
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610161344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3610161344
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1600812904
Short name T120
Test name
Test status
Simulation time 3158279586 ps
CPU time 83.91 seconds
Started Mar 24 12:46:38 PM PDT 24
Finished Mar 24 12:48:03 PM PDT 24
Peak memory 198064 kb
Host smart-cab8f4e2-4dfa-4a2a-b300-65542aa79462
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600812904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1600812904
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.721688489
Short name T205
Test name
Test status
Simulation time 46783318 ps
CPU time 0.62 seconds
Started Mar 24 12:46:35 PM PDT 24
Finished Mar 24 12:46:37 PM PDT 24
Peak memory 194128 kb
Host smart-ad229c0e-89a7-472f-8060-d4a76ace74be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721688489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.721688489
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3340407150
Short name T127
Test name
Test status
Simulation time 45829234 ps
CPU time 0.74 seconds
Started Mar 24 12:46:35 PM PDT 24
Finished Mar 24 12:46:37 PM PDT 24
Peak memory 195224 kb
Host smart-b8e79c7d-429a-4f67-91b9-cd02d973ef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340407150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3340407150
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.4064859920
Short name T721
Test name
Test status
Simulation time 539431546 ps
CPU time 8.78 seconds
Started Mar 24 12:46:36 PM PDT 24
Finished Mar 24 12:46:45 PM PDT 24
Peak memory 196240 kb
Host smart-735f8453-939e-425f-bb87-dd3f2d5d0c94
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064859920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.4064859920
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2218744928
Short name T573
Test name
Test status
Simulation time 170045214 ps
CPU time 0.94 seconds
Started Mar 24 12:46:38 PM PDT 24
Finished Mar 24 12:46:40 PM PDT 24
Peak memory 197308 kb
Host smart-4379a588-8cf8-4eaa-a2a7-a5ebb9dbcc1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218744928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2218744928
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2759664621
Short name T25
Test name
Test status
Simulation time 100849600 ps
CPU time 1.13 seconds
Started Mar 24 12:46:34 PM PDT 24
Finished Mar 24 12:46:36 PM PDT 24
Peak memory 196584 kb
Host smart-24212c66-a9f1-431c-86c4-f1bed9b1d218
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759664621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2759664621
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3975276654
Short name T711
Test name
Test status
Simulation time 83034505 ps
CPU time 1.04 seconds
Started Mar 24 12:46:39 PM PDT 24
Finished Mar 24 12:46:40 PM PDT 24
Peak memory 196316 kb
Host smart-2aa95566-416f-4f9b-96c1-96f89e7b99d9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975276654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3975276654
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.4148333255
Short name T653
Test name
Test status
Simulation time 78441682 ps
CPU time 1.64 seconds
Started Mar 24 12:46:40 PM PDT 24
Finished Mar 24 12:46:42 PM PDT 24
Peak memory 195848 kb
Host smart-e41c0c6d-79cb-49f6-939e-07a096b79223
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148333255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.4148333255
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.4034320347
Short name T449
Test name
Test status
Simulation time 39974187 ps
CPU time 0.84 seconds
Started Mar 24 12:46:36 PM PDT 24
Finished Mar 24 12:46:38 PM PDT 24
Peak memory 196628 kb
Host smart-9026c89e-ca6e-4985-972a-40b521371fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034320347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.4034320347
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3092158667
Short name T24
Test name
Test status
Simulation time 88963871 ps
CPU time 1.21 seconds
Started Mar 24 12:46:39 PM PDT 24
Finished Mar 24 12:46:41 PM PDT 24
Peak memory 195768 kb
Host smart-6f58e97f-73a9-41fe-9c99-306fedb5f2c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092158667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3092158667
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1131606924
Short name T456
Test name
Test status
Simulation time 69801308 ps
CPU time 2.96 seconds
Started Mar 24 12:46:34 PM PDT 24
Finished Mar 24 12:46:38 PM PDT 24
Peak memory 198064 kb
Host smart-e84482d3-6cd3-4cc1-bd73-09c448ffe463
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131606924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1131606924
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1845348980
Short name T413
Test name
Test status
Simulation time 139668223 ps
CPU time 1.19 seconds
Started Mar 24 12:46:39 PM PDT 24
Finished Mar 24 12:46:40 PM PDT 24
Peak memory 195800 kb
Host smart-021e20db-9278-4694-a3dc-85fd947b13ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845348980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1845348980
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3149315637
Short name T578
Test name
Test status
Simulation time 87152904 ps
CPU time 0.88 seconds
Started Mar 24 12:46:34 PM PDT 24
Finished Mar 24 12:46:36 PM PDT 24
Peak memory 195428 kb
Host smart-449ad58d-6a52-43da-8237-67ec317e933f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149315637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3149315637
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3271273024
Short name T478
Test name
Test status
Simulation time 16444822041 ps
CPU time 204.41 seconds
Started Mar 24 12:46:37 PM PDT 24
Finished Mar 24 12:50:02 PM PDT 24
Peak memory 198164 kb
Host smart-7a3669ea-fefb-48ee-8148-174520b83ccd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271273024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3271273024
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1544056727
Short name T565
Test name
Test status
Simulation time 33422205 ps
CPU time 0.6 seconds
Started Mar 24 12:46:45 PM PDT 24
Finished Mar 24 12:46:46 PM PDT 24
Peak memory 194620 kb
Host smart-77a71606-b34f-49f9-851a-6228dd6990ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544056727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1544056727
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.955809876
Short name T620
Test name
Test status
Simulation time 108527997 ps
CPU time 0.9 seconds
Started Mar 24 12:46:41 PM PDT 24
Finished Mar 24 12:46:42 PM PDT 24
Peak memory 196492 kb
Host smart-58454798-7990-4eb6-afe9-39ccbfca684b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955809876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.955809876
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.52654704
Short name T195
Test name
Test status
Simulation time 581598207 ps
CPU time 15.93 seconds
Started Mar 24 12:46:43 PM PDT 24
Finished Mar 24 12:47:00 PM PDT 24
Peak memory 196628 kb
Host smart-af484952-90c2-491d-aed7-4bd01578bded
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52654704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stress
.52654704
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3554865966
Short name T21
Test name
Test status
Simulation time 54232309 ps
CPU time 0.64 seconds
Started Mar 24 12:46:40 PM PDT 24
Finished Mar 24 12:46:41 PM PDT 24
Peak memory 194512 kb
Host smart-18b95e63-74f4-4ce5-8e37-bf42bcd8862c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554865966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3554865966
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1702228310
Short name T493
Test name
Test status
Simulation time 944897353 ps
CPU time 1.45 seconds
Started Mar 24 12:46:40 PM PDT 24
Finished Mar 24 12:46:41 PM PDT 24
Peak memory 197060 kb
Host smart-d39381f6-7617-4b8d-8665-d357cfe0dc98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702228310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1702228310
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3631425243
Short name T358
Test name
Test status
Simulation time 135109201 ps
CPU time 2.86 seconds
Started Mar 24 12:46:39 PM PDT 24
Finished Mar 24 12:46:42 PM PDT 24
Peak memory 198032 kb
Host smart-ce6272bf-50e6-4b07-ac1b-5826bc04a165
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631425243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3631425243
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3217066671
Short name T486
Test name
Test status
Simulation time 58256747 ps
CPU time 1.71 seconds
Started Mar 24 12:46:40 PM PDT 24
Finished Mar 24 12:46:42 PM PDT 24
Peak memory 195844 kb
Host smart-feddbb99-3b8b-4445-bfd7-a0fe5fd49028
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217066671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3217066671
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3297068266
Short name T461
Test name
Test status
Simulation time 33226831 ps
CPU time 1.2 seconds
Started Mar 24 12:46:44 PM PDT 24
Finished Mar 24 12:46:45 PM PDT 24
Peak memory 197112 kb
Host smart-135aa985-ec7b-4c99-b967-0ba00276d8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297068266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3297068266
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2418588960
Short name T615
Test name
Test status
Simulation time 56181241 ps
CPU time 0.99 seconds
Started Mar 24 12:46:40 PM PDT 24
Finished Mar 24 12:46:42 PM PDT 24
Peak memory 196028 kb
Host smart-afa21ed9-9621-49db-b73b-55f41d43966e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418588960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2418588960
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2552688823
Short name T265
Test name
Test status
Simulation time 937930253 ps
CPU time 4.58 seconds
Started Mar 24 12:46:41 PM PDT 24
Finished Mar 24 12:46:45 PM PDT 24
Peak memory 197972 kb
Host smart-7d29de07-03b4-4d7f-b197-eb14acc14cc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552688823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2552688823
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2389777532
Short name T319
Test name
Test status
Simulation time 104184607 ps
CPU time 0.91 seconds
Started Mar 24 12:46:35 PM PDT 24
Finished Mar 24 12:46:37 PM PDT 24
Peak memory 195680 kb
Host smart-273bada6-4e76-481d-959a-f3cc8fbc1cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389777532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2389777532
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1754643662
Short name T346
Test name
Test status
Simulation time 43310841 ps
CPU time 0.92 seconds
Started Mar 24 12:46:34 PM PDT 24
Finished Mar 24 12:46:36 PM PDT 24
Peak memory 195948 kb
Host smart-84226b24-dc9b-4b29-8630-5ba0811e3479
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754643662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1754643662
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2964148324
Short name T1
Test name
Test status
Simulation time 5067668042 ps
CPU time 52.19 seconds
Started Mar 24 12:46:39 PM PDT 24
Finished Mar 24 12:47:32 PM PDT 24
Peak memory 198144 kb
Host smart-a0899fe5-72e5-4902-870e-e58a51814a74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964148324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2964148324
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.814841537
Short name T41
Test name
Test status
Simulation time 47303635 ps
CPU time 0.57 seconds
Started Mar 24 12:46:46 PM PDT 24
Finished Mar 24 12:46:47 PM PDT 24
Peak memory 194140 kb
Host smart-1a1afdaf-293e-442b-9dc1-ee471f6801bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814841537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.814841537
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.439828308
Short name T317
Test name
Test status
Simulation time 58913454 ps
CPU time 0.73 seconds
Started Mar 24 12:46:40 PM PDT 24
Finished Mar 24 12:46:41 PM PDT 24
Peak memory 195308 kb
Host smart-bea012a2-d411-413b-9de3-0fb6b5299d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439828308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.439828308
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2434493544
Short name T475
Test name
Test status
Simulation time 1192973092 ps
CPU time 21.49 seconds
Started Mar 24 12:46:51 PM PDT 24
Finished Mar 24 12:47:13 PM PDT 24
Peak memory 196776 kb
Host smart-c0414415-8628-4e2a-9017-e00349bb23ac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434493544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2434493544
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1532615145
Short name T659
Test name
Test status
Simulation time 111441351 ps
CPU time 0.8 seconds
Started Mar 24 12:46:46 PM PDT 24
Finished Mar 24 12:46:46 PM PDT 24
Peak memory 196084 kb
Host smart-362abb11-3185-4130-959e-d2a0b7f525c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532615145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1532615145
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2464582361
Short name T338
Test name
Test status
Simulation time 620412720 ps
CPU time 1.21 seconds
Started Mar 24 12:46:52 PM PDT 24
Finished Mar 24 12:46:53 PM PDT 24
Peak memory 195828 kb
Host smart-5cf7d8eb-43e2-49de-8dad-75923f83aaa0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464582361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2464582361
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1307640751
Short name T254
Test name
Test status
Simulation time 159270622 ps
CPU time 3.17 seconds
Started Mar 24 12:46:48 PM PDT 24
Finished Mar 24 12:46:51 PM PDT 24
Peak memory 197976 kb
Host smart-180f03ff-e340-4a24-a58f-be90d004cfa3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307640751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1307640751
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1495685833
Short name T331
Test name
Test status
Simulation time 243952158 ps
CPU time 1.51 seconds
Started Mar 24 12:46:46 PM PDT 24
Finished Mar 24 12:46:48 PM PDT 24
Peak memory 195824 kb
Host smart-938ab725-d203-4cc1-9a4c-4f889be323a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495685833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1495685833
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3204066623
Short name T460
Test name
Test status
Simulation time 51164370 ps
CPU time 1.04 seconds
Started Mar 24 12:46:39 PM PDT 24
Finished Mar 24 12:46:41 PM PDT 24
Peak memory 195740 kb
Host smart-d020627a-da76-421c-9af9-98810caa0b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204066623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3204066623
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2821024409
Short name T143
Test name
Test status
Simulation time 57636165 ps
CPU time 1.05 seconds
Started Mar 24 12:46:38 PM PDT 24
Finished Mar 24 12:46:40 PM PDT 24
Peak memory 195956 kb
Host smart-103709d0-e379-461f-955e-479b0d3c0edc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821024409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2821024409
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3752253543
Short name T608
Test name
Test status
Simulation time 73191754 ps
CPU time 1.38 seconds
Started Mar 24 12:46:46 PM PDT 24
Finished Mar 24 12:46:48 PM PDT 24
Peak memory 197960 kb
Host smart-e6df8aea-e89c-490a-9647-77b3a279f0cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752253543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3752253543
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.738518137
Short name T354
Test name
Test status
Simulation time 316087515 ps
CPU time 1.53 seconds
Started Mar 24 12:46:39 PM PDT 24
Finished Mar 24 12:46:41 PM PDT 24
Peak memory 197988 kb
Host smart-62f5b123-8f4d-4ba6-8a08-206965a60060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738518137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.738518137
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2592442569
Short name T144
Test name
Test status
Simulation time 107618437 ps
CPU time 1.14 seconds
Started Mar 24 12:46:43 PM PDT 24
Finished Mar 24 12:46:44 PM PDT 24
Peak memory 196440 kb
Host smart-ea9728de-2c9c-48aa-a10b-f32baef63126
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592442569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2592442569
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.574668447
Short name T675
Test name
Test status
Simulation time 68293102659 ps
CPU time 201.83 seconds
Started Mar 24 12:46:46 PM PDT 24
Finished Mar 24 12:50:08 PM PDT 24
Peak memory 198152 kb
Host smart-3d451218-deda-4cfc-91a3-9e8a23ff8c80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574668447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.574668447
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3641351844
Short name T563
Test name
Test status
Simulation time 272783568886 ps
CPU time 1850.19 seconds
Started Mar 24 12:46:51 PM PDT 24
Finished Mar 24 01:17:41 PM PDT 24
Peak memory 198288 kb
Host smart-a58c8cf0-9fe4-4170-8e52-96a7782696a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3641351844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3641351844
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3390066112
Short name T198
Test name
Test status
Simulation time 36364503 ps
CPU time 0.56 seconds
Started Mar 24 12:46:46 PM PDT 24
Finished Mar 24 12:46:47 PM PDT 24
Peak memory 193884 kb
Host smart-5e48a9ea-1f67-496f-85c9-7f6e486db0ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390066112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3390066112
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4006317392
Short name T386
Test name
Test status
Simulation time 132793850 ps
CPU time 0.77 seconds
Started Mar 24 12:46:47 PM PDT 24
Finished Mar 24 12:46:48 PM PDT 24
Peak memory 195344 kb
Host smart-dcf8e0fc-716c-417c-a01d-147a71f59ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006317392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4006317392
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3467780542
Short name T455
Test name
Test status
Simulation time 498541160 ps
CPU time 16.7 seconds
Started Mar 24 12:46:46 PM PDT 24
Finished Mar 24 12:47:03 PM PDT 24
Peak memory 195480 kb
Host smart-f1da46aa-204d-4afc-aa32-13b19a5aa9a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467780542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3467780542
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2104404515
Short name T433
Test name
Test status
Simulation time 63436326 ps
CPU time 1.02 seconds
Started Mar 24 12:46:50 PM PDT 24
Finished Mar 24 12:46:51 PM PDT 24
Peak memory 196396 kb
Host smart-e7e54745-c11a-426c-897f-df15c6a8c8f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104404515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2104404515
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3168154865
Short name T14
Test name
Test status
Simulation time 29740760 ps
CPU time 0.7 seconds
Started Mar 24 12:46:46 PM PDT 24
Finished Mar 24 12:46:46 PM PDT 24
Peak memory 195092 kb
Host smart-b1630df2-b972-4f7e-b6a7-54c02d896509
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168154865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3168154865
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3786731816
Short name T264
Test name
Test status
Simulation time 37830509 ps
CPU time 1.59 seconds
Started Mar 24 12:46:46 PM PDT 24
Finished Mar 24 12:46:48 PM PDT 24
Peak memory 198028 kb
Host smart-58e3ae05-a707-404b-b491-bb7853182563
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786731816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3786731816
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2712449231
Short name T230
Test name
Test status
Simulation time 89911487 ps
CPU time 0.9 seconds
Started Mar 24 12:46:44 PM PDT 24
Finished Mar 24 12:46:45 PM PDT 24
Peak memory 195544 kb
Host smart-caf58780-3e74-45fd-9bf9-f7421f2a9e4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712449231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2712449231
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.4289476943
Short name T703
Test name
Test status
Simulation time 65369982 ps
CPU time 1.36 seconds
Started Mar 24 12:46:47 PM PDT 24
Finished Mar 24 12:46:49 PM PDT 24
Peak memory 198036 kb
Host smart-f2fc8f20-836e-4876-bf73-fa24981ead89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289476943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.4289476943
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.978828082
Short name T562
Test name
Test status
Simulation time 17268944 ps
CPU time 0.72 seconds
Started Mar 24 12:46:46 PM PDT 24
Finished Mar 24 12:46:47 PM PDT 24
Peak memory 194280 kb
Host smart-d5181304-d728-492f-9637-609202918236
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978828082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.978828082
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2114988893
Short name T543
Test name
Test status
Simulation time 72651969 ps
CPU time 3.11 seconds
Started Mar 24 12:46:49 PM PDT 24
Finished Mar 24 12:46:52 PM PDT 24
Peak memory 197804 kb
Host smart-b0edabbe-44b7-4a01-83a9-839bb3926ca8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114988893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2114988893
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.771986216
Short name T190
Test name
Test status
Simulation time 59560104 ps
CPU time 1.23 seconds
Started Mar 24 12:46:51 PM PDT 24
Finished Mar 24 12:46:52 PM PDT 24
Peak memory 196776 kb
Host smart-bbb877c5-66fb-496c-9f7b-5a856d4e3329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771986216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.771986216
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3330371654
Short name T622
Test name
Test status
Simulation time 38697488 ps
CPU time 1.19 seconds
Started Mar 24 12:46:51 PM PDT 24
Finished Mar 24 12:46:53 PM PDT 24
Peak memory 195796 kb
Host smart-ac631293-e4b3-4af7-8e96-1762e18008f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330371654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3330371654
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2613380588
Short name T30
Test name
Test status
Simulation time 12812795661 ps
CPU time 155.29 seconds
Started Mar 24 12:46:49 PM PDT 24
Finished Mar 24 12:49:24 PM PDT 24
Peak memory 198156 kb
Host smart-ddfa56da-6917-451e-aaad-641387166073
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613380588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2613380588
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.3681111280
Short name T64
Test name
Test status
Simulation time 354645438276 ps
CPU time 1849.57 seconds
Started Mar 24 12:46:51 PM PDT 24
Finished Mar 24 01:17:41 PM PDT 24
Peak memory 198260 kb
Host smart-2233e525-88fb-4312-b3f1-f0500a6bc621
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3681111280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.3681111280
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1465407548
Short name T170
Test name
Test status
Simulation time 13731295 ps
CPU time 0.55 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:45:13 PM PDT 24
Peak memory 193892 kb
Host smart-e09dc43d-7a15-4a96-8db1-dbcfd460613b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465407548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1465407548
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.922561334
Short name T250
Test name
Test status
Simulation time 42402402 ps
CPU time 0.68 seconds
Started Mar 24 12:45:10 PM PDT 24
Finished Mar 24 12:45:11 PM PDT 24
Peak memory 194052 kb
Host smart-ac3fe591-b132-4e29-bd7e-b063aa413285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922561334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.922561334
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3575137994
Short name T136
Test name
Test status
Simulation time 1863023892 ps
CPU time 17.09 seconds
Started Mar 24 12:45:31 PM PDT 24
Finished Mar 24 12:45:49 PM PDT 24
Peak memory 196884 kb
Host smart-a96b787e-09d7-49e3-b112-f6faebf73396
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575137994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3575137994
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1944967072
Short name T698
Test name
Test status
Simulation time 75689846 ps
CPU time 0.8 seconds
Started Mar 24 12:45:14 PM PDT 24
Finished Mar 24 12:45:15 PM PDT 24
Peak memory 196000 kb
Host smart-e48f8072-5aca-492a-9a28-2a1a42b37d79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944967072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1944967072
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2808668249
Short name T445
Test name
Test status
Simulation time 79903176 ps
CPU time 1.22 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 12:45:10 PM PDT 24
Peak memory 196728 kb
Host smart-81edf5be-7e3e-4752-87f8-fbed66fb45ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808668249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2808668249
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2015966559
Short name T590
Test name
Test status
Simulation time 84550606 ps
CPU time 1.15 seconds
Started Mar 24 12:45:20 PM PDT 24
Finished Mar 24 12:45:21 PM PDT 24
Peak memory 197908 kb
Host smart-a21d02f5-cd61-4119-916c-03aeaf3610f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015966559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2015966559
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2634799627
Short name T606
Test name
Test status
Simulation time 513122522 ps
CPU time 2.57 seconds
Started Mar 24 12:45:34 PM PDT 24
Finished Mar 24 12:45:37 PM PDT 24
Peak memory 197160 kb
Host smart-24c2598d-4634-4a00-a910-add26893c37a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634799627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2634799627
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2760434520
Short name T178
Test name
Test status
Simulation time 44830588 ps
CPU time 0.86 seconds
Started Mar 24 12:45:23 PM PDT 24
Finished Mar 24 12:45:24 PM PDT 24
Peak memory 196528 kb
Host smart-c47c8286-1bd6-4c69-bfe4-df53f92c0019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760434520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2760434520
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2395820249
Short name T348
Test name
Test status
Simulation time 286388411 ps
CPU time 1.2 seconds
Started Mar 24 12:45:19 PM PDT 24
Finished Mar 24 12:45:20 PM PDT 24
Peak memory 197012 kb
Host smart-8b895951-be90-4221-9a33-991053ac639f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395820249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2395820249
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2924596973
Short name T576
Test name
Test status
Simulation time 2463793504 ps
CPU time 5.76 seconds
Started Mar 24 12:45:17 PM PDT 24
Finished Mar 24 12:45:22 PM PDT 24
Peak memory 197980 kb
Host smart-d4571367-48c1-42e5-a84f-654462b4035e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924596973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2924596973
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2423502797
Short name T51
Test name
Test status
Simulation time 726787031 ps
CPU time 0.87 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:45:14 PM PDT 24
Peak memory 213880 kb
Host smart-5beb41b7-251a-4ab6-b243-dbd960f50199
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423502797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2423502797
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.181376883
Short name T588
Test name
Test status
Simulation time 192073179 ps
CPU time 1.1 seconds
Started Mar 24 12:45:13 PM PDT 24
Finished Mar 24 12:45:15 PM PDT 24
Peak memory 195416 kb
Host smart-a33c9d06-dfd4-49a2-a1f1-d6c03599d973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181376883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.181376883
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2267639166
Short name T350
Test name
Test status
Simulation time 32040845 ps
CPU time 0.97 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:45:13 PM PDT 24
Peak memory 196532 kb
Host smart-719c227c-aca8-4d74-b3f0-329ff023e870
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267639166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2267639166
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.708866104
Short name T535
Test name
Test status
Simulation time 4220612008 ps
CPU time 54.2 seconds
Started Mar 24 12:45:22 PM PDT 24
Finished Mar 24 12:46:16 PM PDT 24
Peak memory 198196 kb
Host smart-e5982d5f-2230-4899-96bc-b6945d0f0f57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708866104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.708866104
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.3603962442
Short name T2
Test name
Test status
Simulation time 279609661556 ps
CPU time 774.41 seconds
Started Mar 24 12:45:19 PM PDT 24
Finished Mar 24 12:58:13 PM PDT 24
Peak memory 198276 kb
Host smart-9d679ecb-ee28-4b14-a6a5-81dbf7cfdfdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3603962442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.3603962442
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.728335394
Short name T12
Test name
Test status
Simulation time 19476880 ps
CPU time 0.64 seconds
Started Mar 24 12:46:58 PM PDT 24
Finished Mar 24 12:46:58 PM PDT 24
Peak memory 194652 kb
Host smart-0538b062-5f03-4b50-992d-a8765c7f8761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728335394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.728335394
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3651196868
Short name T425
Test name
Test status
Simulation time 29005386 ps
CPU time 0.86 seconds
Started Mar 24 12:46:45 PM PDT 24
Finished Mar 24 12:46:46 PM PDT 24
Peak memory 195508 kb
Host smart-3cf6701c-e2c3-4e45-8898-05c88e38163f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651196868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3651196868
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2803906792
Short name T357
Test name
Test status
Simulation time 511487571 ps
CPU time 17.45 seconds
Started Mar 24 12:46:51 PM PDT 24
Finished Mar 24 12:47:09 PM PDT 24
Peak memory 197096 kb
Host smart-47cbda8c-7ffe-486a-9609-3b2fd168cdd4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803906792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2803906792
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.4279914574
Short name T385
Test name
Test status
Simulation time 86184752 ps
CPU time 1.04 seconds
Started Mar 24 12:46:53 PM PDT 24
Finished Mar 24 12:46:54 PM PDT 24
Peak memory 196240 kb
Host smart-ff4897cc-e538-467d-af71-653a828f892a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279914574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.4279914574
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.4228849749
Short name T407
Test name
Test status
Simulation time 171061709 ps
CPU time 1.17 seconds
Started Mar 24 12:46:45 PM PDT 24
Finished Mar 24 12:46:46 PM PDT 24
Peak memory 196500 kb
Host smart-b4a1c08d-7639-4ab7-aa94-a61259b89559
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228849749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.4228849749
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3591426693
Short name T648
Test name
Test status
Simulation time 86308765 ps
CPU time 1.87 seconds
Started Mar 24 12:46:47 PM PDT 24
Finished Mar 24 12:46:49 PM PDT 24
Peak memory 198128 kb
Host smart-fe1dba46-ad07-45c6-aa55-a5efc35bf1ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591426693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3591426693
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.302475310
Short name T691
Test name
Test status
Simulation time 73178999 ps
CPU time 1.82 seconds
Started Mar 24 12:46:46 PM PDT 24
Finished Mar 24 12:46:48 PM PDT 24
Peak memory 196012 kb
Host smart-d22b9f2e-8937-46e6-926b-ada788fceb96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302475310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
302475310
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1127565249
Short name T187
Test name
Test status
Simulation time 86260973 ps
CPU time 0.93 seconds
Started Mar 24 12:46:45 PM PDT 24
Finished Mar 24 12:46:46 PM PDT 24
Peak memory 195928 kb
Host smart-0e06c1be-6188-43ec-b45e-c1a5b47f54b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127565249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1127565249
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2450617583
Short name T718
Test name
Test status
Simulation time 155798226 ps
CPU time 1.29 seconds
Started Mar 24 12:46:46 PM PDT 24
Finished Mar 24 12:46:47 PM PDT 24
Peak memory 196860 kb
Host smart-fe291df8-4d8c-47d1-aeca-cfced3145561
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450617583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2450617583
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2319222373
Short name T7
Test name
Test status
Simulation time 112128899 ps
CPU time 1.84 seconds
Started Mar 24 12:46:51 PM PDT 24
Finished Mar 24 12:46:53 PM PDT 24
Peak memory 197956 kb
Host smart-a7836ab2-64e5-4e37-9bc6-25818c08394f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319222373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2319222373
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1435723365
Short name T396
Test name
Test status
Simulation time 32267172 ps
CPU time 0.89 seconds
Started Mar 24 12:46:44 PM PDT 24
Finished Mar 24 12:46:46 PM PDT 24
Peak memory 196600 kb
Host smart-aba867fb-ff61-44dd-820a-69691146d35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435723365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1435723365
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3959826909
Short name T566
Test name
Test status
Simulation time 72701295 ps
CPU time 1.16 seconds
Started Mar 24 12:46:47 PM PDT 24
Finished Mar 24 12:46:48 PM PDT 24
Peak memory 195508 kb
Host smart-87c87324-0214-4e80-b5c9-1cc5b3f9de36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959826909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3959826909
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1503547992
Short name T594
Test name
Test status
Simulation time 64063039682 ps
CPU time 235.56 seconds
Started Mar 24 12:46:52 PM PDT 24
Finished Mar 24 12:50:48 PM PDT 24
Peak memory 198200 kb
Host smart-a0d612e7-df1e-4531-b95c-dda992b185bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503547992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1503547992
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.250535866
Short name T488
Test name
Test status
Simulation time 13716325 ps
CPU time 0.6 seconds
Started Mar 24 12:46:53 PM PDT 24
Finished Mar 24 12:46:54 PM PDT 24
Peak memory 193844 kb
Host smart-3603e049-7816-483b-8561-7ee5ed69dabd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250535866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.250535866
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2773308911
Short name T128
Test name
Test status
Simulation time 94199826 ps
CPU time 0.86 seconds
Started Mar 24 12:46:49 PM PDT 24
Finished Mar 24 12:46:50 PM PDT 24
Peak memory 196584 kb
Host smart-f7d5f0c1-d297-4deb-9056-2dbe62e207be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773308911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2773308911
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.4169377694
Short name T666
Test name
Test status
Simulation time 230174118 ps
CPU time 7.19 seconds
Started Mar 24 12:46:55 PM PDT 24
Finished Mar 24 12:47:02 PM PDT 24
Peak memory 196280 kb
Host smart-8a4493c6-285d-42f1-a6a7-4c59ee95a62e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169377694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.4169377694
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3442653961
Short name T367
Test name
Test status
Simulation time 30823704 ps
CPU time 0.73 seconds
Started Mar 24 12:46:52 PM PDT 24
Finished Mar 24 12:46:53 PM PDT 24
Peak memory 195092 kb
Host smart-6bb283aa-1725-486c-8b30-b31538f48dac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442653961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3442653961
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2162304067
Short name T210
Test name
Test status
Simulation time 238762267 ps
CPU time 0.76 seconds
Started Mar 24 12:46:56 PM PDT 24
Finished Mar 24 12:46:57 PM PDT 24
Peak memory 195556 kb
Host smart-a9305f85-ee01-45c5-b0b3-7da219d449a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162304067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2162304067
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.4062083358
Short name T531
Test name
Test status
Simulation time 89071511 ps
CPU time 3.38 seconds
Started Mar 24 12:46:49 PM PDT 24
Finished Mar 24 12:46:52 PM PDT 24
Peak memory 198008 kb
Host smart-31a56823-2427-4347-935b-dcb8989a6eeb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062083358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.4062083358
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.570311048
Short name T579
Test name
Test status
Simulation time 211844903 ps
CPU time 1.47 seconds
Started Mar 24 12:46:51 PM PDT 24
Finished Mar 24 12:46:52 PM PDT 24
Peak memory 196600 kb
Host smart-2b9e144d-3fbd-45c8-9ffd-f7158fcd0b77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570311048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
570311048
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3366104919
Short name T469
Test name
Test status
Simulation time 28485076 ps
CPU time 1.12 seconds
Started Mar 24 12:46:55 PM PDT 24
Finished Mar 24 12:46:56 PM PDT 24
Peak memory 196576 kb
Host smart-f20f68f2-3bad-4f7a-ae70-ca8ae623d409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366104919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3366104919
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1660677803
Short name T519
Test name
Test status
Simulation time 130126109 ps
CPU time 0.91 seconds
Started Mar 24 12:46:56 PM PDT 24
Finished Mar 24 12:46:57 PM PDT 24
Peak memory 195780 kb
Host smart-09903c60-5513-4291-a851-8934e6ad46a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660677803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1660677803
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1934038459
Short name T377
Test name
Test status
Simulation time 2692434684 ps
CPU time 4.06 seconds
Started Mar 24 12:46:55 PM PDT 24
Finished Mar 24 12:47:00 PM PDT 24
Peak memory 198088 kb
Host smart-92a41c66-8346-48d5-bf25-aa65a2dc49a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934038459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1934038459
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2046928193
Short name T330
Test name
Test status
Simulation time 77511286 ps
CPU time 0.87 seconds
Started Mar 24 12:46:52 PM PDT 24
Finished Mar 24 12:46:53 PM PDT 24
Peak memory 195252 kb
Host smart-80cae91f-afe6-4720-9400-bb34aa50bbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046928193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2046928193
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3923596761
Short name T557
Test name
Test status
Simulation time 65769169 ps
CPU time 0.85 seconds
Started Mar 24 12:46:50 PM PDT 24
Finished Mar 24 12:46:51 PM PDT 24
Peak memory 195360 kb
Host smart-acfecf86-188e-4c3c-b95d-194ca5b7d6f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923596761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3923596761
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.653996575
Short name T124
Test name
Test status
Simulation time 5268923369 ps
CPU time 32.06 seconds
Started Mar 24 12:46:49 PM PDT 24
Finished Mar 24 12:47:21 PM PDT 24
Peak memory 198112 kb
Host smart-7551893f-3647-4774-8474-50fcd6c29bf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653996575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.653996575
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.2215512079
Short name T282
Test name
Test status
Simulation time 18593867382 ps
CPU time 457.39 seconds
Started Mar 24 12:46:51 PM PDT 24
Finished Mar 24 12:54:28 PM PDT 24
Peak memory 198184 kb
Host smart-6e66f643-776f-4bda-afa0-747f7e00f4dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2215512079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.2215512079
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2138130883
Short name T323
Test name
Test status
Simulation time 27603181 ps
CPU time 0.58 seconds
Started Mar 24 12:46:53 PM PDT 24
Finished Mar 24 12:46:53 PM PDT 24
Peak memory 194100 kb
Host smart-a21e2f96-5f9b-4b88-99eb-1173e9dc1a13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138130883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2138130883
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.4158730115
Short name T347
Test name
Test status
Simulation time 129841490 ps
CPU time 0.9 seconds
Started Mar 24 12:46:51 PM PDT 24
Finished Mar 24 12:46:52 PM PDT 24
Peak memory 196532 kb
Host smart-98d2c650-0c2f-4706-ac74-4d32eb7df8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158730115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.4158730115
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.724164745
Short name T206
Test name
Test status
Simulation time 1288619843 ps
CPU time 17.2 seconds
Started Mar 24 12:46:51 PM PDT 24
Finished Mar 24 12:47:08 PM PDT 24
Peak memory 195540 kb
Host smart-5e97a212-27cb-4d5b-a5c2-b0791a797948
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724164745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.724164745
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1718663031
Short name T503
Test name
Test status
Simulation time 22369464 ps
CPU time 0.65 seconds
Started Mar 24 12:46:54 PM PDT 24
Finished Mar 24 12:46:55 PM PDT 24
Peak memory 195200 kb
Host smart-02d5db3d-112f-4004-839c-50a6c82ac9ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718663031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1718663031
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2577603833
Short name T692
Test name
Test status
Simulation time 42033600 ps
CPU time 1.13 seconds
Started Mar 24 12:46:51 PM PDT 24
Finished Mar 24 12:46:52 PM PDT 24
Peak memory 196120 kb
Host smart-1013a2a4-0d5e-40f5-a049-189322cdcd23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577603833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2577603833
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1515588507
Short name T349
Test name
Test status
Simulation time 345129436 ps
CPU time 3.43 seconds
Started Mar 24 12:46:53 PM PDT 24
Finished Mar 24 12:46:57 PM PDT 24
Peak memory 197980 kb
Host smart-effd5c3c-7fec-4c31-a892-5b7a1ef6be9b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515588507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1515588507
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1193671127
Short name T238
Test name
Test status
Simulation time 418983007 ps
CPU time 3.47 seconds
Started Mar 24 12:46:49 PM PDT 24
Finished Mar 24 12:46:53 PM PDT 24
Peak memory 197072 kb
Host smart-679af73f-8376-40bd-a4d8-9d1334ec2f09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193671127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1193671127
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.4114523788
Short name T498
Test name
Test status
Simulation time 42440160 ps
CPU time 0.71 seconds
Started Mar 24 12:46:51 PM PDT 24
Finished Mar 24 12:46:52 PM PDT 24
Peak memory 195348 kb
Host smart-862ca18f-502b-4426-ae2e-ef549459bc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114523788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.4114523788
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1575869954
Short name T56
Test name
Test status
Simulation time 44437841 ps
CPU time 1.37 seconds
Started Mar 24 12:46:53 PM PDT 24
Finished Mar 24 12:46:55 PM PDT 24
Peak memory 198072 kb
Host smart-e5d15df1-4b8b-4cdf-8f50-4a5875b733b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575869954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1575869954
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2673382950
Short name T287
Test name
Test status
Simulation time 91038687 ps
CPU time 1.12 seconds
Started Mar 24 12:46:53 PM PDT 24
Finished Mar 24 12:46:54 PM PDT 24
Peak memory 197956 kb
Host smart-55795119-4513-4c7c-a798-d745a61a71dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673382950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2673382950
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2261821079
Short name T701
Test name
Test status
Simulation time 74794976 ps
CPU time 1.37 seconds
Started Mar 24 12:46:58 PM PDT 24
Finished Mar 24 12:46:59 PM PDT 24
Peak memory 196648 kb
Host smart-82a3316a-e06a-49f0-9ad4-027adb636e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261821079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2261821079
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2510398233
Short name T694
Test name
Test status
Simulation time 107529058 ps
CPU time 1.01 seconds
Started Mar 24 12:46:50 PM PDT 24
Finished Mar 24 12:46:52 PM PDT 24
Peak memory 195688 kb
Host smart-15016755-2748-44dc-99be-c3dbefb14fbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510398233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2510398233
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1851143396
Short name T53
Test name
Test status
Simulation time 5648091949 ps
CPU time 69.01 seconds
Started Mar 24 12:46:53 PM PDT 24
Finished Mar 24 12:48:02 PM PDT 24
Peak memory 197992 kb
Host smart-e2b1eaf7-cb8e-4994-9864-e4722bdfedf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851143396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1851143396
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1529777912
Short name T371
Test name
Test status
Simulation time 41943689 ps
CPU time 0.56 seconds
Started Mar 24 12:47:00 PM PDT 24
Finished Mar 24 12:47:01 PM PDT 24
Peak memory 193924 kb
Host smart-594a1681-90a8-4db8-a9e7-8bc0e46f64d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529777912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1529777912
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3994445545
Short name T650
Test name
Test status
Simulation time 30912977 ps
CPU time 0.68 seconds
Started Mar 24 12:46:52 PM PDT 24
Finished Mar 24 12:46:53 PM PDT 24
Peak memory 194124 kb
Host smart-89ed9e5e-8604-447a-b557-532c3435ddc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994445545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3994445545
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2386456802
Short name T315
Test name
Test status
Simulation time 731033894 ps
CPU time 10.95 seconds
Started Mar 24 12:46:57 PM PDT 24
Finished Mar 24 12:47:08 PM PDT 24
Peak memory 196720 kb
Host smart-e341e96b-74a4-4661-8cb7-ce45bbea33cc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386456802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2386456802
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.560515842
Short name T468
Test name
Test status
Simulation time 67630231 ps
CPU time 0.98 seconds
Started Mar 24 12:46:57 PM PDT 24
Finished Mar 24 12:46:58 PM PDT 24
Peak memory 196496 kb
Host smart-457cb5b0-22fc-42ea-bf1c-d414992df328
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560515842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.560515842
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2065438114
Short name T239
Test name
Test status
Simulation time 49463433 ps
CPU time 0.84 seconds
Started Mar 24 12:46:50 PM PDT 24
Finished Mar 24 12:46:51 PM PDT 24
Peak memory 196780 kb
Host smart-b9b35572-da08-4dc3-8a6d-c72f4cb39bb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065438114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2065438114
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2883850787
Short name T577
Test name
Test status
Simulation time 347824137 ps
CPU time 2.79 seconds
Started Mar 24 12:46:56 PM PDT 24
Finished Mar 24 12:46:59 PM PDT 24
Peak memory 197936 kb
Host smart-f442538a-69aa-40eb-9bea-6e9ad47c52c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883850787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2883850787
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1573837632
Short name T360
Test name
Test status
Simulation time 104807110 ps
CPU time 1.87 seconds
Started Mar 24 12:46:58 PM PDT 24
Finished Mar 24 12:47:00 PM PDT 24
Peak memory 195812 kb
Host smart-591e0ddf-c865-40ae-b2ac-b543d60ed4be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573837632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1573837632
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.589653397
Short name T560
Test name
Test status
Simulation time 239158162 ps
CPU time 1.23 seconds
Started Mar 24 12:46:53 PM PDT 24
Finished Mar 24 12:46:55 PM PDT 24
Peak memory 197044 kb
Host smart-a209dd44-c83b-4a97-b342-df04ee3f2024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589653397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.589653397
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3511050965
Short name T295
Test name
Test status
Simulation time 126110159 ps
CPU time 0.71 seconds
Started Mar 24 12:46:51 PM PDT 24
Finished Mar 24 12:46:52 PM PDT 24
Peak memory 196184 kb
Host smart-54c8680c-fb09-47b1-b8c9-2c2c2a190f87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511050965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3511050965
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3494488975
Short name T697
Test name
Test status
Simulation time 629445303 ps
CPU time 2.4 seconds
Started Mar 24 12:46:57 PM PDT 24
Finished Mar 24 12:46:59 PM PDT 24
Peak memory 197804 kb
Host smart-9663bceb-e6a0-4ef9-a3d2-dd5383993402
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494488975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3494488975
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2856167749
Short name T647
Test name
Test status
Simulation time 36010351 ps
CPU time 1.01 seconds
Started Mar 24 12:46:56 PM PDT 24
Finished Mar 24 12:46:58 PM PDT 24
Peak memory 195548 kb
Host smart-ac6944dd-6a99-476f-9913-13269f979c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856167749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2856167749
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1907791419
Short name T221
Test name
Test status
Simulation time 36337369 ps
CPU time 1.21 seconds
Started Mar 24 12:46:53 PM PDT 24
Finished Mar 24 12:46:54 PM PDT 24
Peak memory 196508 kb
Host smart-3f04b573-1c32-46f3-a5ea-5378e79fd457
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907791419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1907791419
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1514638216
Short name T353
Test name
Test status
Simulation time 8258857153 ps
CPU time 228.75 seconds
Started Mar 24 12:47:02 PM PDT 24
Finished Mar 24 12:50:51 PM PDT 24
Peak memory 198180 kb
Host smart-d79ba256-d7a5-4f05-b4f7-b0e5ec0b18d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514638216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1514638216
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.4102911694
Short name T676
Test name
Test status
Simulation time 61055312163 ps
CPU time 1557.97 seconds
Started Mar 24 12:46:57 PM PDT 24
Finished Mar 24 01:12:55 PM PDT 24
Peak memory 198284 kb
Host smart-e42fed4a-dad2-4591-a10a-c4722394944e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4102911694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.4102911694
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3167831265
Short name T247
Test name
Test status
Simulation time 20720200 ps
CPU time 0.59 seconds
Started Mar 24 12:46:57 PM PDT 24
Finished Mar 24 12:46:58 PM PDT 24
Peak memory 194940 kb
Host smart-b2c4b1d7-14de-4a0f-bf6d-50117252265b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167831265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3167831265
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3165181734
Short name T548
Test name
Test status
Simulation time 87765379 ps
CPU time 0.64 seconds
Started Mar 24 12:46:57 PM PDT 24
Finished Mar 24 12:46:57 PM PDT 24
Peak memory 194224 kb
Host smart-970af00d-d0e6-4314-872b-a426854ebadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165181734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3165181734
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2929997699
Short name T640
Test name
Test status
Simulation time 4800818180 ps
CPU time 26.3 seconds
Started Mar 24 12:46:56 PM PDT 24
Finished Mar 24 12:47:23 PM PDT 24
Peak memory 197576 kb
Host smart-e9eccf76-6289-46c9-80bf-17ddacf2a74e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929997699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2929997699
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2203677286
Short name T207
Test name
Test status
Simulation time 220093927 ps
CPU time 0.92 seconds
Started Mar 24 12:46:58 PM PDT 24
Finished Mar 24 12:46:59 PM PDT 24
Peak memory 197172 kb
Host smart-642b1b91-649c-43a5-bb28-0a9a4cd0cb38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203677286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2203677286
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3971277976
Short name T341
Test name
Test status
Simulation time 298679119 ps
CPU time 1.28 seconds
Started Mar 24 12:46:59 PM PDT 24
Finished Mar 24 12:47:01 PM PDT 24
Peak memory 195888 kb
Host smart-23968922-6b3b-4853-9430-7a992567402b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971277976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3971277976
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3215238835
Short name T186
Test name
Test status
Simulation time 112920130 ps
CPU time 1.36 seconds
Started Mar 24 12:46:56 PM PDT 24
Finished Mar 24 12:46:57 PM PDT 24
Peak memory 196256 kb
Host smart-e3dbb790-677a-41d3-8b26-072c805ac67a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215238835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3215238835
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3388839384
Short name T352
Test name
Test status
Simulation time 168905050 ps
CPU time 1.43 seconds
Started Mar 24 12:46:57 PM PDT 24
Finished Mar 24 12:46:58 PM PDT 24
Peak memory 196188 kb
Host smart-01042e29-9ed2-4b80-aaca-cc6e72eaf3ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388839384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3388839384
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.4165337690
Short name T66
Test name
Test status
Simulation time 68682297 ps
CPU time 1.09 seconds
Started Mar 24 12:46:55 PM PDT 24
Finished Mar 24 12:46:57 PM PDT 24
Peak memory 196980 kb
Host smart-3bd5fd9b-5553-4a53-b84a-fb56a2b5a258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165337690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.4165337690
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2722604454
Short name T95
Test name
Test status
Simulation time 51372999 ps
CPU time 1.18 seconds
Started Mar 24 12:46:58 PM PDT 24
Finished Mar 24 12:46:59 PM PDT 24
Peak memory 195760 kb
Host smart-c592fbc0-2459-4afc-860d-c27f43bccc4a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722604454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2722604454
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3743644732
Short name T260
Test name
Test status
Simulation time 100733607 ps
CPU time 1.43 seconds
Started Mar 24 12:46:59 PM PDT 24
Finished Mar 24 12:47:01 PM PDT 24
Peak memory 198060 kb
Host smart-a50de630-fa0f-477e-930f-e5a4d5da7c92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743644732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3743644732
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3361013932
Short name T179
Test name
Test status
Simulation time 395548905 ps
CPU time 1.57 seconds
Started Mar 24 12:46:56 PM PDT 24
Finished Mar 24 12:46:57 PM PDT 24
Peak memory 195528 kb
Host smart-c4b349e9-409f-4032-b1d6-6b595b4ceb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361013932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3361013932
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3475019700
Short name T447
Test name
Test status
Simulation time 542479348 ps
CPU time 1.21 seconds
Started Mar 24 12:46:58 PM PDT 24
Finished Mar 24 12:47:00 PM PDT 24
Peak memory 195540 kb
Host smart-6ea2eb8d-f5b0-4d21-9d95-a8f0117110cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475019700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3475019700
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1922288987
Short name T657
Test name
Test status
Simulation time 38430110001 ps
CPU time 111.35 seconds
Started Mar 24 12:47:02 PM PDT 24
Finished Mar 24 12:48:54 PM PDT 24
Peak memory 198252 kb
Host smart-e1fe152a-ba97-4fc8-8885-1a35127f24c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922288987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1922288987
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3211725336
Short name T479
Test name
Test status
Simulation time 57603712 ps
CPU time 0.58 seconds
Started Mar 24 12:47:00 PM PDT 24
Finished Mar 24 12:47:01 PM PDT 24
Peak memory 194112 kb
Host smart-0744b845-5ff1-419a-b5d1-fecaac7d2fc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211725336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3211725336
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1339441705
Short name T183
Test name
Test status
Simulation time 268527943 ps
CPU time 0.87 seconds
Started Mar 24 12:47:02 PM PDT 24
Finished Mar 24 12:47:03 PM PDT 24
Peak memory 195500 kb
Host smart-07ef2487-3a1d-4229-99a8-3de9c8618dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339441705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1339441705
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2005196805
Short name T291
Test name
Test status
Simulation time 1699187961 ps
CPU time 10.73 seconds
Started Mar 24 12:46:56 PM PDT 24
Finished Mar 24 12:47:07 PM PDT 24
Peak memory 196852 kb
Host smart-9d62e789-ac50-47f4-8681-22522a182855
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005196805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2005196805
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2002922217
Short name T390
Test name
Test status
Simulation time 26164799 ps
CPU time 0.63 seconds
Started Mar 24 12:46:58 PM PDT 24
Finished Mar 24 12:46:59 PM PDT 24
Peak memory 194468 kb
Host smart-5ab2c6ae-c08b-422b-9f19-2c0395d04b6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002922217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2002922217
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3585529623
Short name T450
Test name
Test status
Simulation time 200602149 ps
CPU time 0.71 seconds
Started Mar 24 12:46:57 PM PDT 24
Finished Mar 24 12:46:57 PM PDT 24
Peak memory 194476 kb
Host smart-911c1aab-3ab6-421f-90bc-043de6a3dadf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585529623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3585529623
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3424050292
Short name T699
Test name
Test status
Simulation time 61514198 ps
CPU time 1.27 seconds
Started Mar 24 12:46:57 PM PDT 24
Finished Mar 24 12:46:58 PM PDT 24
Peak memory 196456 kb
Host smart-82c8426f-1526-43ed-90ee-ca30784cf258
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424050292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3424050292
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2673168012
Short name T218
Test name
Test status
Simulation time 450580577 ps
CPU time 1 seconds
Started Mar 24 12:46:59 PM PDT 24
Finished Mar 24 12:47:00 PM PDT 24
Peak memory 195452 kb
Host smart-a9779976-fea5-4351-a63e-2df98f7bf09b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673168012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2673168012
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3105101043
Short name T494
Test name
Test status
Simulation time 37360070 ps
CPU time 1.16 seconds
Started Mar 24 12:46:59 PM PDT 24
Finished Mar 24 12:47:01 PM PDT 24
Peak memory 198032 kb
Host smart-28a3e5d9-e2ae-4a98-8165-1c4ceef8d29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105101043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3105101043
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3098346303
Short name T473
Test name
Test status
Simulation time 61981085 ps
CPU time 0.69 seconds
Started Mar 24 12:47:02 PM PDT 24
Finished Mar 24 12:47:03 PM PDT 24
Peak memory 195168 kb
Host smart-3f54f1cc-662f-464c-aab5-66f1044b26b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098346303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3098346303
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.777703293
Short name T652
Test name
Test status
Simulation time 1081124395 ps
CPU time 6.52 seconds
Started Mar 24 12:47:00 PM PDT 24
Finished Mar 24 12:47:06 PM PDT 24
Peak memory 197948 kb
Host smart-82ed8d90-4dfa-4434-9221-acc65378479d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777703293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.777703293
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3902304863
Short name T249
Test name
Test status
Simulation time 67302105 ps
CPU time 1.4 seconds
Started Mar 24 12:47:02 PM PDT 24
Finished Mar 24 12:47:04 PM PDT 24
Peak memory 197128 kb
Host smart-9a463a5e-2a62-4b58-a300-dd9ccb4c1d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902304863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3902304863
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3358046601
Short name T477
Test name
Test status
Simulation time 210006225 ps
CPU time 1.12 seconds
Started Mar 24 12:46:58 PM PDT 24
Finished Mar 24 12:46:59 PM PDT 24
Peak memory 195812 kb
Host smart-2785443e-cd49-4ae8-b8ae-145f0d479ce4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358046601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3358046601
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1241201378
Short name T453
Test name
Test status
Simulation time 6053048692 ps
CPU time 35.59 seconds
Started Mar 24 12:46:59 PM PDT 24
Finished Mar 24 12:47:35 PM PDT 24
Peak memory 198136 kb
Host smart-4e277167-7e79-425f-840a-e22e5af6fe94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241201378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1241201378
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.978234855
Short name T42
Test name
Test status
Simulation time 95599085 ps
CPU time 0.62 seconds
Started Mar 24 12:47:02 PM PDT 24
Finished Mar 24 12:47:03 PM PDT 24
Peak memory 194120 kb
Host smart-b672bee9-784e-4993-bc78-b75024cd0b2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978234855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.978234855
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1540543102
Short name T724
Test name
Test status
Simulation time 111165707 ps
CPU time 0.77 seconds
Started Mar 24 12:47:01 PM PDT 24
Finished Mar 24 12:47:02 PM PDT 24
Peak memory 195900 kb
Host smart-6d2acbcc-fe20-47bd-adf6-242090fce321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540543102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1540543102
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3238006845
Short name T232
Test name
Test status
Simulation time 754642501 ps
CPU time 19.63 seconds
Started Mar 24 12:47:00 PM PDT 24
Finished Mar 24 12:47:19 PM PDT 24
Peak memory 197036 kb
Host smart-24a37992-3725-4948-83da-0b9b69ccec1e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238006845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3238006845
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2617433246
Short name T444
Test name
Test status
Simulation time 278282315 ps
CPU time 1.12 seconds
Started Mar 24 12:47:06 PM PDT 24
Finished Mar 24 12:47:07 PM PDT 24
Peak memory 197680 kb
Host smart-f9f2f9a7-a0fb-4b28-b79f-36febce26898
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617433246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2617433246
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2301619791
Short name T343
Test name
Test status
Simulation time 49432118 ps
CPU time 1.39 seconds
Started Mar 24 12:47:06 PM PDT 24
Finished Mar 24 12:47:07 PM PDT 24
Peak memory 197184 kb
Host smart-0a3ac423-8fd3-4ed7-bf2e-3dac35a7d685
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301619791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2301619791
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1764368596
Short name T320
Test name
Test status
Simulation time 75755999 ps
CPU time 2.9 seconds
Started Mar 24 12:46:59 PM PDT 24
Finished Mar 24 12:47:02 PM PDT 24
Peak memory 196436 kb
Host smart-3050e235-34bf-47e4-9c1e-e6b7bc0cca79
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764368596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1764368596
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3815835546
Short name T459
Test name
Test status
Simulation time 557772644 ps
CPU time 3 seconds
Started Mar 24 12:47:00 PM PDT 24
Finished Mar 24 12:47:03 PM PDT 24
Peak memory 197984 kb
Host smart-fb2d450e-3754-46eb-ae37-5d777d199bcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815835546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3815835546
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.4139782337
Short name T432
Test name
Test status
Simulation time 75987160 ps
CPU time 0.64 seconds
Started Mar 24 12:47:02 PM PDT 24
Finished Mar 24 12:47:03 PM PDT 24
Peak memory 194292 kb
Host smart-3d41be39-c281-44e3-b41b-69aaaa0d9c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139782337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.4139782337
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.785087948
Short name T15
Test name
Test status
Simulation time 47865566 ps
CPU time 1.14 seconds
Started Mar 24 12:47:01 PM PDT 24
Finished Mar 24 12:47:02 PM PDT 24
Peak memory 195856 kb
Host smart-78da7e4b-4f4e-4b0d-9142-949218576067
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785087948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.785087948
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3578142406
Short name T686
Test name
Test status
Simulation time 163255400 ps
CPU time 2.88 seconds
Started Mar 24 12:47:01 PM PDT 24
Finished Mar 24 12:47:04 PM PDT 24
Peak memory 197932 kb
Host smart-e94e72da-5c76-48d6-bc59-995d15fe70ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578142406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3578142406
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2488102100
Short name T383
Test name
Test status
Simulation time 349383845 ps
CPU time 1.25 seconds
Started Mar 24 12:47:03 PM PDT 24
Finished Mar 24 12:47:05 PM PDT 24
Peak memory 196408 kb
Host smart-d5e7afe6-aa2b-485c-b622-00e0dfc8944f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488102100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2488102100
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2344403774
Short name T243
Test name
Test status
Simulation time 95525567 ps
CPU time 0.91 seconds
Started Mar 24 12:47:02 PM PDT 24
Finished Mar 24 12:47:03 PM PDT 24
Peak memory 196436 kb
Host smart-08d44a71-5f6a-4882-8711-38fe7cbeb3be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344403774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2344403774
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1986366438
Short name T514
Test name
Test status
Simulation time 11507752480 ps
CPU time 158.39 seconds
Started Mar 24 12:47:02 PM PDT 24
Finished Mar 24 12:49:40 PM PDT 24
Peak memory 198192 kb
Host smart-7e4a6654-9faf-41ef-874c-4289cd54a5f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986366438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1986366438
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.1354694592
Short name T269
Test name
Test status
Simulation time 19654355321 ps
CPU time 409.41 seconds
Started Mar 24 12:47:01 PM PDT 24
Finished Mar 24 12:53:50 PM PDT 24
Peak memory 198204 kb
Host smart-bd8a5463-4c32-4c31-9b91-dbec14839314
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1354694592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.1354694592
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2232516980
Short name T139
Test name
Test status
Simulation time 47511243 ps
CPU time 0.61 seconds
Started Mar 24 12:47:02 PM PDT 24
Finished Mar 24 12:47:03 PM PDT 24
Peak memory 194096 kb
Host smart-57f48259-7005-4a73-90fa-1bee042244ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232516980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2232516980
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2842390844
Short name T643
Test name
Test status
Simulation time 67770569 ps
CPU time 0.86 seconds
Started Mar 24 12:47:12 PM PDT 24
Finished Mar 24 12:47:13 PM PDT 24
Peak memory 196096 kb
Host smart-63609dec-67e1-4873-aea1-0fda9825729a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842390844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2842390844
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.452511513
Short name T634
Test name
Test status
Simulation time 1140471851 ps
CPU time 28.19 seconds
Started Mar 24 12:47:12 PM PDT 24
Finished Mar 24 12:47:40 PM PDT 24
Peak memory 198052 kb
Host smart-0636b03e-d075-4b1f-82bf-427f9ce4c247
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452511513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.452511513
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3067947685
Short name T375
Test name
Test status
Simulation time 84170928 ps
CPU time 1.12 seconds
Started Mar 24 12:47:12 PM PDT 24
Finished Mar 24 12:47:13 PM PDT 24
Peak memory 197824 kb
Host smart-2bdf0e93-fd71-402f-bfff-64a671fb5bee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067947685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3067947685
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3470537855
Short name T618
Test name
Test status
Simulation time 172657272 ps
CPU time 0.65 seconds
Started Mar 24 12:47:02 PM PDT 24
Finished Mar 24 12:47:02 PM PDT 24
Peak memory 195112 kb
Host smart-a646149c-d594-46ad-8a59-7d8b58f8619b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470537855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3470537855
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1101117987
Short name T184
Test name
Test status
Simulation time 88220779 ps
CPU time 2.09 seconds
Started Mar 24 12:47:03 PM PDT 24
Finished Mar 24 12:47:05 PM PDT 24
Peak memory 198068 kb
Host smart-33ce4001-0086-4164-b2a2-9367585941ca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101117987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1101117987
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2776744773
Short name T96
Test name
Test status
Simulation time 65983933 ps
CPU time 2.04 seconds
Started Mar 24 12:47:12 PM PDT 24
Finished Mar 24 12:47:14 PM PDT 24
Peak memory 195832 kb
Host smart-513f3461-9987-49c3-a80f-285c6a70a280
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776744773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2776744773
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.510171093
Short name T687
Test name
Test status
Simulation time 38709448 ps
CPU time 1.04 seconds
Started Mar 24 12:47:06 PM PDT 24
Finished Mar 24 12:47:07 PM PDT 24
Peak memory 195840 kb
Host smart-26d17b73-2bbe-4754-966d-9d3aa8b825cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510171093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.510171093
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3008612557
Short name T717
Test name
Test status
Simulation time 51099052 ps
CPU time 1.19 seconds
Started Mar 24 12:47:12 PM PDT 24
Finished Mar 24 12:47:13 PM PDT 24
Peak memory 196780 kb
Host smart-ac98fe8b-da83-47ae-a187-d37ab97a6cab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008612557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3008612557
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1368886776
Short name T630
Test name
Test status
Simulation time 106675536 ps
CPU time 4.9 seconds
Started Mar 24 12:47:01 PM PDT 24
Finished Mar 24 12:47:06 PM PDT 24
Peak memory 198008 kb
Host smart-e1c42c12-780e-40e4-a752-c4ec24783d35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368886776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1368886776
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2212462106
Short name T702
Test name
Test status
Simulation time 47411881 ps
CPU time 1.08 seconds
Started Mar 24 12:47:02 PM PDT 24
Finished Mar 24 12:47:03 PM PDT 24
Peak memory 195780 kb
Host smart-decc70a3-8712-49f8-9deb-9b850d8ef761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212462106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2212462106
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2694093973
Short name T200
Test name
Test status
Simulation time 64992871 ps
CPU time 1.13 seconds
Started Mar 24 12:47:02 PM PDT 24
Finished Mar 24 12:47:03 PM PDT 24
Peak memory 195724 kb
Host smart-6342cc2b-ac0a-4d4a-9fd1-555dd270409e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694093973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2694093973
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1832423858
Short name T587
Test name
Test status
Simulation time 9396073548 ps
CPU time 106.09 seconds
Started Mar 24 12:47:00 PM PDT 24
Finished Mar 24 12:48:46 PM PDT 24
Peak memory 198252 kb
Host smart-a4955da2-183c-449c-bb98-1673c53633aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832423858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1832423858
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.1969873155
Short name T101
Test name
Test status
Simulation time 120291745655 ps
CPU time 2688.5 seconds
Started Mar 24 12:47:04 PM PDT 24
Finished Mar 24 01:31:53 PM PDT 24
Peak memory 198244 kb
Host smart-997f1c67-7613-410e-ac43-22c1ee6d6719
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1969873155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.1969873155
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2790990819
Short name T540
Test name
Test status
Simulation time 72892511 ps
CPU time 0.58 seconds
Started Mar 24 12:47:09 PM PDT 24
Finished Mar 24 12:47:10 PM PDT 24
Peak memory 194108 kb
Host smart-0a1050e5-2f17-4b9b-a604-2b10161cd77a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790990819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2790990819
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2402471846
Short name T661
Test name
Test status
Simulation time 28535862 ps
CPU time 0.87 seconds
Started Mar 24 12:47:08 PM PDT 24
Finished Mar 24 12:47:09 PM PDT 24
Peak memory 197084 kb
Host smart-e702d8ce-0992-4c03-916d-062177d7ff9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402471846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2402471846
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.4236142182
Short name T683
Test name
Test status
Simulation time 195727866 ps
CPU time 6.56 seconds
Started Mar 24 12:47:07 PM PDT 24
Finished Mar 24 12:47:14 PM PDT 24
Peak memory 196808 kb
Host smart-98e1ae8a-f5f8-4ab9-934c-abc97fe03477
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236142182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.4236142182
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.145490388
Short name T194
Test name
Test status
Simulation time 151146081 ps
CPU time 1.07 seconds
Started Mar 24 12:47:13 PM PDT 24
Finished Mar 24 12:47:14 PM PDT 24
Peak memory 196480 kb
Host smart-41ced5c9-6e5a-44e2-92f2-bf3c51bae32e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145490388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.145490388
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3840074139
Short name T419
Test name
Test status
Simulation time 81162530 ps
CPU time 0.84 seconds
Started Mar 24 12:47:05 PM PDT 24
Finished Mar 24 12:47:06 PM PDT 24
Peak memory 195568 kb
Host smart-996da883-6a0a-4de6-a13e-f07680e3512f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840074139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3840074139
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3198657544
Short name T321
Test name
Test status
Simulation time 111468287 ps
CPU time 1.48 seconds
Started Mar 24 12:47:06 PM PDT 24
Finished Mar 24 12:47:08 PM PDT 24
Peak memory 196756 kb
Host smart-418d7435-af83-4c09-bfde-302d66b32f8e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198657544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3198657544
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3098443645
Short name T29
Test name
Test status
Simulation time 340571010 ps
CPU time 2.02 seconds
Started Mar 24 12:47:08 PM PDT 24
Finished Mar 24 12:47:11 PM PDT 24
Peak memory 196200 kb
Host smart-baa50f25-df82-4223-b950-def01a5ea761
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098443645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3098443645
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.997548071
Short name T482
Test name
Test status
Simulation time 32047302 ps
CPU time 1.31 seconds
Started Mar 24 12:47:08 PM PDT 24
Finished Mar 24 12:47:09 PM PDT 24
Peak memory 197964 kb
Host smart-b84950e3-45be-4683-882b-f8b0df62b74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997548071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.997548071
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1478308822
Short name T689
Test name
Test status
Simulation time 465128925 ps
CPU time 1.01 seconds
Started Mar 24 12:47:07 PM PDT 24
Finished Mar 24 12:47:08 PM PDT 24
Peak memory 196672 kb
Host smart-fc84d774-f7e0-4e1f-8821-6677a6913cac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478308822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1478308822
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1415546393
Short name T680
Test name
Test status
Simulation time 57509963 ps
CPU time 2.7 seconds
Started Mar 24 12:47:08 PM PDT 24
Finished Mar 24 12:47:11 PM PDT 24
Peak memory 197988 kb
Host smart-43a0ce45-f730-458f-a8be-fbddd6a43fb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415546393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1415546393
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1152321827
Short name T440
Test name
Test status
Simulation time 29737347 ps
CPU time 0.98 seconds
Started Mar 24 12:47:08 PM PDT 24
Finished Mar 24 12:47:09 PM PDT 24
Peak memory 195632 kb
Host smart-62db6756-4452-4ba8-81df-94464b20aaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152321827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1152321827
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1956004771
Short name T550
Test name
Test status
Simulation time 66942062 ps
CPU time 1.16 seconds
Started Mar 24 12:47:07 PM PDT 24
Finished Mar 24 12:47:08 PM PDT 24
Peak memory 195696 kb
Host smart-fdb4c795-bc3e-4a36-ac71-84d0c44aa12b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956004771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1956004771
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1618168534
Short name T448
Test name
Test status
Simulation time 10685439319 ps
CPU time 130.01 seconds
Started Mar 24 12:47:07 PM PDT 24
Finished Mar 24 12:49:17 PM PDT 24
Peak memory 198236 kb
Host smart-acd996cb-3038-44a9-9d53-520b306a44b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618168534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1618168534
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.952091240
Short name T33
Test name
Test status
Simulation time 127971071035 ps
CPU time 839.93 seconds
Started Mar 24 12:47:09 PM PDT 24
Finished Mar 24 01:01:09 PM PDT 24
Peak memory 198136 kb
Host smart-f009a153-395c-4836-8231-fabedf78c07c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=952091240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.952091240
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.233120799
Short name T431
Test name
Test status
Simulation time 13199390 ps
CPU time 0.57 seconds
Started Mar 24 12:47:21 PM PDT 24
Finished Mar 24 12:47:22 PM PDT 24
Peak memory 194592 kb
Host smart-b18532bb-fe81-47b7-81ff-7b6f1dcc3aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233120799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.233120799
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1842048827
Short name T185
Test name
Test status
Simulation time 18054582 ps
CPU time 0.67 seconds
Started Mar 24 12:47:09 PM PDT 24
Finished Mar 24 12:47:10 PM PDT 24
Peak memory 194048 kb
Host smart-76b473aa-7e2a-4d12-b3aa-ab6a6d512159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842048827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1842048827
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2157454148
Short name T381
Test name
Test status
Simulation time 971704220 ps
CPU time 24.91 seconds
Started Mar 24 12:47:07 PM PDT 24
Finished Mar 24 12:47:32 PM PDT 24
Peak memory 197944 kb
Host smart-8a472794-da84-4cd6-8fd9-6aeb3df0c6ed
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157454148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2157454148
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3732632254
Short name T442
Test name
Test status
Simulation time 151236191 ps
CPU time 1.03 seconds
Started Mar 24 12:47:21 PM PDT 24
Finished Mar 24 12:47:22 PM PDT 24
Peak memory 196556 kb
Host smart-07f2f804-4668-4807-81de-7e28e72ee1f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732632254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3732632254
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2415397363
Short name T467
Test name
Test status
Simulation time 62629152 ps
CPU time 0.81 seconds
Started Mar 24 12:47:11 PM PDT 24
Finished Mar 24 12:47:12 PM PDT 24
Peak memory 195680 kb
Host smart-ef734aed-9a78-47b6-8572-ee952cd78feb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415397363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2415397363
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3693052430
Short name T11
Test name
Test status
Simulation time 80936075 ps
CPU time 3.32 seconds
Started Mar 24 12:47:09 PM PDT 24
Finished Mar 24 12:47:12 PM PDT 24
Peak memory 198044 kb
Host smart-d7a88fda-c8e7-42e7-8751-4c7d12d10b8d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693052430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3693052430
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.598492770
Short name T669
Test name
Test status
Simulation time 170532306 ps
CPU time 2.55 seconds
Started Mar 24 12:47:08 PM PDT 24
Finished Mar 24 12:47:10 PM PDT 24
Peak memory 197964 kb
Host smart-4e22f691-279e-4528-a13e-25f4c5e166e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598492770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
598492770
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.33191933
Short name T263
Test name
Test status
Simulation time 113091510 ps
CPU time 0.85 seconds
Started Mar 24 12:47:09 PM PDT 24
Finished Mar 24 12:47:10 PM PDT 24
Peak memory 195852 kb
Host smart-233b7f1f-ec82-4641-bb9e-9c23d783dca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33191933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.33191933
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2142829673
Short name T169
Test name
Test status
Simulation time 267332761 ps
CPU time 1.39 seconds
Started Mar 24 12:47:12 PM PDT 24
Finished Mar 24 12:47:14 PM PDT 24
Peak memory 197004 kb
Host smart-91c84d2b-4301-437d-80f0-61527a2c299f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142829673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2142829673
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1803471736
Short name T163
Test name
Test status
Simulation time 97009695 ps
CPU time 2.35 seconds
Started Mar 24 12:47:07 PM PDT 24
Finished Mar 24 12:47:09 PM PDT 24
Peak memory 197960 kb
Host smart-5f6b70ea-5505-42a0-ac7a-1b03048876e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803471736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1803471736
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1804573941
Short name T196
Test name
Test status
Simulation time 93986348 ps
CPU time 0.83 seconds
Started Mar 24 12:47:07 PM PDT 24
Finished Mar 24 12:47:08 PM PDT 24
Peak memory 196384 kb
Host smart-8ca77197-91f1-40c9-9f23-234785214bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804573941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1804573941
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2456277968
Short name T115
Test name
Test status
Simulation time 139709304 ps
CPU time 0.87 seconds
Started Mar 24 12:47:09 PM PDT 24
Finished Mar 24 12:47:10 PM PDT 24
Peak memory 196508 kb
Host smart-aa4b266e-7c91-4d43-80c6-3a3b5d3e64e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456277968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2456277968
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3469650194
Short name T316
Test name
Test status
Simulation time 45693114858 ps
CPU time 215.71 seconds
Started Mar 24 12:47:15 PM PDT 24
Finished Mar 24 12:50:51 PM PDT 24
Peak memory 198180 kb
Host smart-a780ce7b-263a-4756-838c-df3586f33c23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469650194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3469650194
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.384699130
Short name T387
Test name
Test status
Simulation time 26672244163 ps
CPU time 376.13 seconds
Started Mar 24 12:47:15 PM PDT 24
Finished Mar 24 12:53:32 PM PDT 24
Peak memory 198232 kb
Host smart-95f09c3c-c519-4e1b-9a73-33ea9642a6d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=384699130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.384699130
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3004274408
Short name T223
Test name
Test status
Simulation time 49667984 ps
CPU time 0.56 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:45:13 PM PDT 24
Peak memory 194120 kb
Host smart-d37eb28c-9593-45b8-95fc-50948b05c041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004274408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3004274408
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.4086399899
Short name T111
Test name
Test status
Simulation time 53678777 ps
CPU time 0.69 seconds
Started Mar 24 12:45:25 PM PDT 24
Finished Mar 24 12:45:26 PM PDT 24
Peak memory 194152 kb
Host smart-f34cbc0f-aa64-4f40-a98c-33450d9bed08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086399899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.4086399899
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2267008380
Short name T368
Test name
Test status
Simulation time 3678913737 ps
CPU time 23.75 seconds
Started Mar 24 12:45:08 PM PDT 24
Finished Mar 24 12:45:32 PM PDT 24
Peak memory 198340 kb
Host smart-d99a103f-c958-4aea-852c-2b85e56aa10d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267008380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2267008380
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1898430606
Short name T259
Test name
Test status
Simulation time 56422883 ps
CPU time 0.83 seconds
Started Mar 24 12:45:14 PM PDT 24
Finished Mar 24 12:45:15 PM PDT 24
Peak memory 196004 kb
Host smart-033938a3-db45-44f9-8add-2119e46fe03f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898430606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1898430606
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2423762682
Short name T201
Test name
Test status
Simulation time 49047912 ps
CPU time 0.95 seconds
Started Mar 24 12:45:14 PM PDT 24
Finished Mar 24 12:45:15 PM PDT 24
Peak memory 196232 kb
Host smart-09090221-448b-4904-a093-c0cde1aa7913
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423762682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2423762682
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2055542411
Short name T155
Test name
Test status
Simulation time 51551762 ps
CPU time 1.91 seconds
Started Mar 24 12:45:28 PM PDT 24
Finished Mar 24 12:45:30 PM PDT 24
Peak memory 196696 kb
Host smart-84886d5c-bd16-488d-9014-5aa0c5420f62
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055542411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2055542411
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.824503676
Short name T472
Test name
Test status
Simulation time 89150373 ps
CPU time 2.58 seconds
Started Mar 24 12:45:25 PM PDT 24
Finished Mar 24 12:45:28 PM PDT 24
Peak memory 197204 kb
Host smart-0e37aa28-dd41-4d86-8629-4282d7424464
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824503676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.824503676
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.555701186
Short name T395
Test name
Test status
Simulation time 193242441 ps
CPU time 0.89 seconds
Started Mar 24 12:45:28 PM PDT 24
Finished Mar 24 12:45:29 PM PDT 24
Peak memory 197164 kb
Host smart-5fc465d5-039f-4508-b6c1-380e139f017b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555701186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.555701186
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3839458350
Short name T660
Test name
Test status
Simulation time 54136126 ps
CPU time 0.94 seconds
Started Mar 24 12:45:16 PM PDT 24
Finished Mar 24 12:45:17 PM PDT 24
Peak memory 196508 kb
Host smart-3abb67ed-792f-4a74-9b1a-81f1df78797a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839458350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3839458350
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3486798208
Short name T500
Test name
Test status
Simulation time 355446297 ps
CPU time 4.29 seconds
Started Mar 24 12:45:32 PM PDT 24
Finished Mar 24 12:45:36 PM PDT 24
Peak memory 197852 kb
Host smart-b8e569e8-77e9-4e0a-895e-a1e63c18ff91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486798208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3486798208
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2263485568
Short name T50
Test name
Test status
Simulation time 216589939 ps
CPU time 0.86 seconds
Started Mar 24 12:45:28 PM PDT 24
Finished Mar 24 12:45:30 PM PDT 24
Peak memory 213844 kb
Host smart-e40966fc-6083-4590-b7a8-7f5d355a5630
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263485568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2263485568
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2866988415
Short name T600
Test name
Test status
Simulation time 294335360 ps
CPU time 1.21 seconds
Started Mar 24 12:45:12 PM PDT 24
Finished Mar 24 12:45:13 PM PDT 24
Peak memory 197864 kb
Host smart-0004b7ea-3f2c-454b-b5c3-040733171918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866988415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2866988415
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.617826156
Short name T416
Test name
Test status
Simulation time 157285944 ps
CPU time 0.89 seconds
Started Mar 24 12:45:27 PM PDT 24
Finished Mar 24 12:45:28 PM PDT 24
Peak memory 195992 kb
Host smart-e58bcce0-f63a-4e44-b31e-0ac1f8f11f91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617826156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.617826156
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2670273484
Short name T5
Test name
Test status
Simulation time 104051824650 ps
CPU time 233.11 seconds
Started Mar 24 12:45:15 PM PDT 24
Finished Mar 24 12:49:09 PM PDT 24
Peak memory 198116 kb
Host smart-ebff87fe-48ee-4a66-a728-695580ae92b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670273484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2670273484
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.770414216
Short name T63
Test name
Test status
Simulation time 211331078219 ps
CPU time 1410.7 seconds
Started Mar 24 12:45:22 PM PDT 24
Finished Mar 24 01:08:53 PM PDT 24
Peak memory 198224 kb
Host smart-2a35dd8e-d3b7-4d5b-b9a0-04a8727fbbb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=770414216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.770414216
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1612011157
Short name T635
Test name
Test status
Simulation time 16901017 ps
CPU time 0.62 seconds
Started Mar 24 12:47:17 PM PDT 24
Finished Mar 24 12:47:17 PM PDT 24
Peak memory 194864 kb
Host smart-9a6826d5-412e-4c0b-9ea7-f2e1abaf1c80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612011157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1612011157
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2888728650
Short name T118
Test name
Test status
Simulation time 399391558 ps
CPU time 0.89 seconds
Started Mar 24 12:47:13 PM PDT 24
Finished Mar 24 12:47:13 PM PDT 24
Peak memory 196596 kb
Host smart-233fe325-511f-4867-97cc-893bcd37d3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888728650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2888728650
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2329798543
Short name T571
Test name
Test status
Simulation time 1793176001 ps
CPU time 12.63 seconds
Started Mar 24 12:47:14 PM PDT 24
Finished Mar 24 12:47:27 PM PDT 24
Peak memory 196800 kb
Host smart-77181e7a-076d-4a6a-a905-e7a339e87c16
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329798543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2329798543
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1741952049
Short name T158
Test name
Test status
Simulation time 276189725 ps
CPU time 1 seconds
Started Mar 24 12:47:17 PM PDT 24
Finished Mar 24 12:47:18 PM PDT 24
Peak memory 198020 kb
Host smart-d1c7baa0-5adc-4aa2-9a27-b79ac683f024
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741952049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1741952049
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1135634709
Short name T655
Test name
Test status
Simulation time 590636442 ps
CPU time 1.52 seconds
Started Mar 24 12:47:19 PM PDT 24
Finished Mar 24 12:47:20 PM PDT 24
Peak memory 198080 kb
Host smart-03c88ae8-2252-4f34-aa4a-8eaaaa2953ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135634709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1135634709
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.319485028
Short name T99
Test name
Test status
Simulation time 349317814 ps
CPU time 3.39 seconds
Started Mar 24 12:47:13 PM PDT 24
Finished Mar 24 12:47:16 PM PDT 24
Peak memory 198112 kb
Host smart-a10e36f5-a375-4f05-a179-717726e613b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319485028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.319485028
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.992859241
Short name T418
Test name
Test status
Simulation time 70787169 ps
CPU time 2.19 seconds
Started Mar 24 12:47:11 PM PDT 24
Finished Mar 24 12:47:14 PM PDT 24
Peak memory 196752 kb
Host smart-3ec0a62d-412d-4e25-843e-c200cfdba5bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992859241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
992859241
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.4246722395
Short name T130
Test name
Test status
Simulation time 35692411 ps
CPU time 0.72 seconds
Started Mar 24 12:47:16 PM PDT 24
Finished Mar 24 12:47:17 PM PDT 24
Peak memory 194640 kb
Host smart-6eedd765-d57f-4ef2-a8e3-cc52128a0b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246722395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.4246722395
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.457061761
Short name T614
Test name
Test status
Simulation time 171672132 ps
CPU time 1.19 seconds
Started Mar 24 12:47:18 PM PDT 24
Finished Mar 24 12:47:19 PM PDT 24
Peak memory 196100 kb
Host smart-d6e80bc1-e101-4c92-a856-a3c5007308c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457061761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.457061761
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2713736864
Short name T313
Test name
Test status
Simulation time 521099042 ps
CPU time 4.47 seconds
Started Mar 24 12:47:13 PM PDT 24
Finished Mar 24 12:47:17 PM PDT 24
Peak memory 197968 kb
Host smart-9596708e-4889-442c-98b3-31e4e75e9218
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713736864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2713736864
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3001130300
Short name T611
Test name
Test status
Simulation time 141109798 ps
CPU time 0.97 seconds
Started Mar 24 12:47:12 PM PDT 24
Finished Mar 24 12:47:13 PM PDT 24
Peak memory 195676 kb
Host smart-6f946179-5deb-49e7-a8e7-ad8846aeebe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001130300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3001130300
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1224288910
Short name T714
Test name
Test status
Simulation time 21653653 ps
CPU time 0.7 seconds
Started Mar 24 12:47:17 PM PDT 24
Finished Mar 24 12:47:18 PM PDT 24
Peak memory 194800 kb
Host smart-bde10579-ad9d-45c3-a9dc-a8f78521bf7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224288910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1224288910
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1104940160
Short name T527
Test name
Test status
Simulation time 5250280836 ps
CPU time 137.51 seconds
Started Mar 24 12:47:13 PM PDT 24
Finished Mar 24 12:49:30 PM PDT 24
Peak memory 198160 kb
Host smart-d5f45024-67a2-4283-95c9-83b42f5de99a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104940160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1104940160
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.4075066318
Short name T515
Test name
Test status
Simulation time 42420703958 ps
CPU time 1112.48 seconds
Started Mar 24 12:47:14 PM PDT 24
Finished Mar 24 01:05:47 PM PDT 24
Peak memory 198264 kb
Host smart-ee44288b-cf34-4531-b651-c22fd8e5ffa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4075066318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.4075066318
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.4103796842
Short name T434
Test name
Test status
Simulation time 69850513 ps
CPU time 0.59 seconds
Started Mar 24 12:47:16 PM PDT 24
Finished Mar 24 12:47:17 PM PDT 24
Peak memory 193888 kb
Host smart-1af9e987-4ae9-44ad-9900-818dfe9f2f3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103796842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.4103796842
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.793058403
Short name T681
Test name
Test status
Simulation time 49362475 ps
CPU time 0.6 seconds
Started Mar 24 12:47:15 PM PDT 24
Finished Mar 24 12:47:16 PM PDT 24
Peak memory 194788 kb
Host smart-346e7ed0-5adb-45f9-98a7-7516a2a5f5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793058403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.793058403
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2613982262
Short name T283
Test name
Test status
Simulation time 7988651580 ps
CPU time 17.47 seconds
Started Mar 24 12:47:21 PM PDT 24
Finished Mar 24 12:47:38 PM PDT 24
Peak memory 197020 kb
Host smart-fd65b6b0-09e0-44a6-8f46-c1ffdde7ad04
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613982262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2613982262
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1259077231
Short name T605
Test name
Test status
Simulation time 64284683 ps
CPU time 0.92 seconds
Started Mar 24 12:47:13 PM PDT 24
Finished Mar 24 12:47:14 PM PDT 24
Peak memory 197380 kb
Host smart-85a38b69-b959-4731-872e-fdd42e0efbf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259077231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1259077231
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2874983943
Short name T722
Test name
Test status
Simulation time 93326082 ps
CPU time 1.12 seconds
Started Mar 24 12:47:17 PM PDT 24
Finished Mar 24 12:47:18 PM PDT 24
Peak memory 196080 kb
Host smart-7084a839-7bad-43e0-b877-e3b6d2b5248d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874983943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2874983943
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.4006027449
Short name T107
Test name
Test status
Simulation time 267871890 ps
CPU time 2.74 seconds
Started Mar 24 12:47:15 PM PDT 24
Finished Mar 24 12:47:18 PM PDT 24
Peak memory 198028 kb
Host smart-7086d7df-9613-4fc5-b4d9-067a4aa67c03
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006027449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.4006027449
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3628536426
Short name T268
Test name
Test status
Simulation time 121909821 ps
CPU time 2.33 seconds
Started Mar 24 12:47:12 PM PDT 24
Finished Mar 24 12:47:14 PM PDT 24
Peak memory 195796 kb
Host smart-5a8c7e3c-937c-45a6-a595-2713850bb689
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628536426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3628536426
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3078316951
Short name T451
Test name
Test status
Simulation time 78039876 ps
CPU time 1.2 seconds
Started Mar 24 12:47:18 PM PDT 24
Finished Mar 24 12:47:19 PM PDT 24
Peak memory 197124 kb
Host smart-cd5ff0d9-736d-431d-9d48-714879a71d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078316951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3078316951
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1799278132
Short name T583
Test name
Test status
Simulation time 27611918 ps
CPU time 1.05 seconds
Started Mar 24 12:47:14 PM PDT 24
Finished Mar 24 12:47:15 PM PDT 24
Peak memory 196776 kb
Host smart-5c166561-36d9-48e6-aff8-81a72aa1b09f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799278132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1799278132
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.246003918
Short name T693
Test name
Test status
Simulation time 218710191 ps
CPU time 3.88 seconds
Started Mar 24 12:47:13 PM PDT 24
Finished Mar 24 12:47:17 PM PDT 24
Peak memory 197972 kb
Host smart-1d93e5c2-41c9-483c-b423-43989e69d6f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246003918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.246003918
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3094299021
Short name T220
Test name
Test status
Simulation time 124300223 ps
CPU time 0.98 seconds
Started Mar 24 12:47:15 PM PDT 24
Finished Mar 24 12:47:16 PM PDT 24
Peak memory 196616 kb
Host smart-6e0e388b-13e6-48b5-8e1a-3c21a801151e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094299021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3094299021
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2148223061
Short name T13
Test name
Test status
Simulation time 62531415 ps
CPU time 1.11 seconds
Started Mar 24 12:47:22 PM PDT 24
Finished Mar 24 12:47:23 PM PDT 24
Peak memory 196476 kb
Host smart-84f51a74-9dd3-4dc1-b66e-1b6a0c11407f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148223061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2148223061
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.249287101
Short name T476
Test name
Test status
Simulation time 34829480903 ps
CPU time 95.96 seconds
Started Mar 24 12:47:13 PM PDT 24
Finished Mar 24 12:48:49 PM PDT 24
Peak memory 198172 kb
Host smart-802fe63e-a357-4221-afc5-1cf274e85016
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249287101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.249287101
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2835915606
Short name T369
Test name
Test status
Simulation time 95080513 ps
CPU time 0.57 seconds
Started Mar 24 12:47:22 PM PDT 24
Finished Mar 24 12:47:23 PM PDT 24
Peak memory 193924 kb
Host smart-3adcfef6-6a52-4dd8-823a-15905e7101af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835915606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2835915606
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.610139072
Short name T485
Test name
Test status
Simulation time 208254652 ps
CPU time 0.77 seconds
Started Mar 24 12:47:22 PM PDT 24
Finished Mar 24 12:47:23 PM PDT 24
Peak memory 194140 kb
Host smart-2ebb5cd5-34f4-404d-8005-69b6d7fbffb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610139072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.610139072
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2578556887
Short name T539
Test name
Test status
Simulation time 1071808056 ps
CPU time 14.22 seconds
Started Mar 24 12:47:20 PM PDT 24
Finished Mar 24 12:47:34 PM PDT 24
Peak memory 195416 kb
Host smart-2a22b319-9508-400c-b68a-387f307545d3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578556887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2578556887
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.4227411711
Short name T252
Test name
Test status
Simulation time 59056622 ps
CPU time 0.72 seconds
Started Mar 24 12:47:20 PM PDT 24
Finished Mar 24 12:47:21 PM PDT 24
Peak memory 194764 kb
Host smart-dd73369f-da8b-4ee1-8159-4b08531ee7a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227411711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.4227411711
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2603423124
Short name T222
Test name
Test status
Simulation time 177188059 ps
CPU time 0.91 seconds
Started Mar 24 12:47:21 PM PDT 24
Finished Mar 24 12:47:22 PM PDT 24
Peak memory 195708 kb
Host smart-c493a760-a54a-46e0-bb24-1a25ed4a2abb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603423124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2603423124
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2831599135
Short name T106
Test name
Test status
Simulation time 282512557 ps
CPU time 2.89 seconds
Started Mar 24 12:47:18 PM PDT 24
Finished Mar 24 12:47:21 PM PDT 24
Peak memory 197936 kb
Host smart-d41c89a9-36e7-4884-8284-d4de7a0603e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831599135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2831599135
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.979447522
Short name T517
Test name
Test status
Simulation time 119851498 ps
CPU time 2.05 seconds
Started Mar 24 12:47:21 PM PDT 24
Finished Mar 24 12:47:23 PM PDT 24
Peak memory 196560 kb
Host smart-74cfb306-3409-47f7-ab4f-455326ce7e16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979447522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
979447522
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2441741755
Short name T302
Test name
Test status
Simulation time 35059224 ps
CPU time 0.93 seconds
Started Mar 24 12:47:24 PM PDT 24
Finished Mar 24 12:47:26 PM PDT 24
Peak memory 195512 kb
Host smart-f5944810-01a2-48ef-8370-6bebb56da036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441741755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2441741755
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2019625115
Short name T597
Test name
Test status
Simulation time 93035825 ps
CPU time 1.12 seconds
Started Mar 24 12:47:18 PM PDT 24
Finished Mar 24 12:47:20 PM PDT 24
Peak memory 196124 kb
Host smart-c64e022d-765f-4440-96d7-2de10c801ba8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019625115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2019625115
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3195100279
Short name T613
Test name
Test status
Simulation time 1182314411 ps
CPU time 1.56 seconds
Started Mar 24 12:47:19 PM PDT 24
Finished Mar 24 12:47:20 PM PDT 24
Peak memory 198044 kb
Host smart-0d633f40-818d-4a8e-8a17-bf29f723cd53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195100279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3195100279
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2056271159
Short name T204
Test name
Test status
Simulation time 93192962 ps
CPU time 1.47 seconds
Started Mar 24 12:47:20 PM PDT 24
Finished Mar 24 12:47:21 PM PDT 24
Peak memory 196800 kb
Host smart-a6fbfab5-c02f-4960-96bb-57386704d1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056271159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2056271159
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1883650141
Short name T288
Test name
Test status
Simulation time 285711171 ps
CPU time 1.17 seconds
Started Mar 24 12:47:20 PM PDT 24
Finished Mar 24 12:47:21 PM PDT 24
Peak memory 196132 kb
Host smart-cda41df3-69af-4067-b2ea-3124e9c529a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883650141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1883650141
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1576990733
Short name T530
Test name
Test status
Simulation time 7433445046 ps
CPU time 47.87 seconds
Started Mar 24 12:47:21 PM PDT 24
Finished Mar 24 12:48:09 PM PDT 24
Peak memory 198180 kb
Host smart-50a0955b-4457-4bd5-9937-81c19b6547f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576990733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1576990733
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.515524163
Short name T281
Test name
Test status
Simulation time 18296868971 ps
CPU time 421.62 seconds
Started Mar 24 12:47:22 PM PDT 24
Finished Mar 24 12:54:24 PM PDT 24
Peak memory 198288 kb
Host smart-daee67ba-80f7-4735-9348-79dd13ef1624
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=515524163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.515524163
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.40316165
Short name T607
Test name
Test status
Simulation time 14867720 ps
CPU time 0.56 seconds
Started Mar 24 12:47:18 PM PDT 24
Finished Mar 24 12:47:18 PM PDT 24
Peak memory 194732 kb
Host smart-3a0ca947-7e72-467f-88a7-89328f2d172b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40316165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.40316165
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1991390095
Short name T394
Test name
Test status
Simulation time 187473655 ps
CPU time 0.7 seconds
Started Mar 24 12:47:18 PM PDT 24
Finished Mar 24 12:47:19 PM PDT 24
Peak memory 195284 kb
Host smart-c07e9a70-a27c-4fdd-8a03-9cb63d8983a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991390095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1991390095
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.4030205136
Short name T126
Test name
Test status
Simulation time 986334192 ps
CPU time 25 seconds
Started Mar 24 12:47:18 PM PDT 24
Finished Mar 24 12:47:43 PM PDT 24
Peak memory 196904 kb
Host smart-87c05de4-2b53-4fa6-bd2a-24d9b472c451
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030205136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.4030205136
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3701733920
Short name T452
Test name
Test status
Simulation time 59543304 ps
CPU time 0.88 seconds
Started Mar 24 12:47:20 PM PDT 24
Finished Mar 24 12:47:21 PM PDT 24
Peak memory 196636 kb
Host smart-164721c8-d867-4987-9381-8e258d7e4db9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701733920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3701733920
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1411082209
Short name T175
Test name
Test status
Simulation time 72465499 ps
CPU time 1.08 seconds
Started Mar 24 12:47:19 PM PDT 24
Finished Mar 24 12:47:20 PM PDT 24
Peak memory 195996 kb
Host smart-c0d9e097-2c25-4ad1-a073-8ab510f6d4a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411082209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1411082209
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.4175187733
Short name T435
Test name
Test status
Simulation time 25154558 ps
CPU time 1.06 seconds
Started Mar 24 12:47:22 PM PDT 24
Finished Mar 24 12:47:24 PM PDT 24
Peak memory 196132 kb
Host smart-783056c9-9dfb-4e52-ae09-1fb7f6636c3f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175187733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.4175187733
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3278909278
Short name T415
Test name
Test status
Simulation time 420141150 ps
CPU time 2.19 seconds
Started Mar 24 12:47:24 PM PDT 24
Finished Mar 24 12:47:26 PM PDT 24
Peak memory 196540 kb
Host smart-c099917b-f234-4e7f-91ad-78b15859e374
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278909278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3278909278
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3453041378
Short name T193
Test name
Test status
Simulation time 107462992 ps
CPU time 0.87 seconds
Started Mar 24 12:47:19 PM PDT 24
Finished Mar 24 12:47:20 PM PDT 24
Peak memory 197544 kb
Host smart-63816bc6-f199-4712-bfd4-caf6c440c852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453041378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3453041378
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1697479915
Short name T312
Test name
Test status
Simulation time 110296773 ps
CPU time 1.11 seconds
Started Mar 24 12:47:24 PM PDT 24
Finished Mar 24 12:47:26 PM PDT 24
Peak memory 195704 kb
Host smart-17c78474-d814-4c1a-aa2f-ce69a4775684
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697479915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1697479915
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2304792377
Short name T474
Test name
Test status
Simulation time 52259485 ps
CPU time 2.59 seconds
Started Mar 24 12:47:19 PM PDT 24
Finished Mar 24 12:47:21 PM PDT 24
Peak memory 197948 kb
Host smart-c9c6fe9b-fe55-4fc2-beab-152bb237288c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304792377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2304792377
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1969941945
Short name T684
Test name
Test status
Simulation time 81748491 ps
CPU time 1.5 seconds
Started Mar 24 12:47:19 PM PDT 24
Finished Mar 24 12:47:21 PM PDT 24
Peak memory 196740 kb
Host smart-22ca8374-8bed-4230-b6ed-caeed5b9997e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969941945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1969941945
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.4287068848
Short name T229
Test name
Test status
Simulation time 224067137 ps
CPU time 1.23 seconds
Started Mar 24 12:47:18 PM PDT 24
Finished Mar 24 12:47:20 PM PDT 24
Peak memory 196468 kb
Host smart-378e63ad-04a4-4bbf-9f65-48f33fa0a968
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287068848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.4287068848
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1588175383
Short name T3
Test name
Test status
Simulation time 3485520966 ps
CPU time 43.11 seconds
Started Mar 24 12:47:18 PM PDT 24
Finished Mar 24 12:48:01 PM PDT 24
Peak memory 198148 kb
Host smart-721e9c1b-4736-49ba-ba65-dcc3252d5fad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588175383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1588175383
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1914742432
Short name T570
Test name
Test status
Simulation time 21899653 ps
CPU time 0.61 seconds
Started Mar 24 12:47:24 PM PDT 24
Finished Mar 24 12:47:25 PM PDT 24
Peak memory 194636 kb
Host smart-f6358608-19bb-47c4-ad91-6f837c289b2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914742432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1914742432
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.401421493
Short name T299
Test name
Test status
Simulation time 49836045 ps
CPU time 0.99 seconds
Started Mar 24 12:47:26 PM PDT 24
Finished Mar 24 12:47:27 PM PDT 24
Peak memory 195872 kb
Host smart-b253ca6a-be87-46eb-bda0-1767fcabecff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401421493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.401421493
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2942982181
Short name T59
Test name
Test status
Simulation time 1008483497 ps
CPU time 27.36 seconds
Started Mar 24 12:47:24 PM PDT 24
Finished Mar 24 12:47:52 PM PDT 24
Peak memory 197068 kb
Host smart-e868ba27-0dd0-46d0-a550-f7703594b2e1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942982181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2942982181
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1780805383
Short name T213
Test name
Test status
Simulation time 235356823 ps
CPU time 1.04 seconds
Started Mar 24 12:47:26 PM PDT 24
Finished Mar 24 12:47:28 PM PDT 24
Peak memory 196380 kb
Host smart-1eb9c7e8-58d0-4aab-89fd-364739f1636b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780805383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1780805383
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1248771129
Short name T575
Test name
Test status
Simulation time 135734598 ps
CPU time 1.57 seconds
Started Mar 24 12:47:26 PM PDT 24
Finished Mar 24 12:47:27 PM PDT 24
Peak memory 198096 kb
Host smart-afb67027-d999-49bd-a25f-e067466749d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248771129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1248771129
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1688070260
Short name T544
Test name
Test status
Simulation time 83201123 ps
CPU time 3.17 seconds
Started Mar 24 12:47:27 PM PDT 24
Finished Mar 24 12:47:31 PM PDT 24
Peak memory 198092 kb
Host smart-ab271b56-c04f-4628-b83e-bafae6bec69b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688070260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1688070260
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.106416630
Short name T228
Test name
Test status
Simulation time 79407847 ps
CPU time 2.36 seconds
Started Mar 24 12:47:27 PM PDT 24
Finished Mar 24 12:47:29 PM PDT 24
Peak memory 197228 kb
Host smart-48a463c5-08f3-446b-ae19-3b71f0b252e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106416630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
106416630
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.313845702
Short name T712
Test name
Test status
Simulation time 32137084 ps
CPU time 1.28 seconds
Started Mar 24 12:47:27 PM PDT 24
Finished Mar 24 12:47:28 PM PDT 24
Peak memory 197028 kb
Host smart-be8b7992-52ad-4f9b-8675-a9ed6de07efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313845702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.313845702
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.907706775
Short name T121
Test name
Test status
Simulation time 21013143 ps
CPU time 0.68 seconds
Started Mar 24 12:47:25 PM PDT 24
Finished Mar 24 12:47:26 PM PDT 24
Peak memory 194316 kb
Host smart-6f93f0f8-7c19-4b17-8513-dae08b826eaf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907706775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.907706775
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2076886404
Short name T595
Test name
Test status
Simulation time 233446903 ps
CPU time 3.39 seconds
Started Mar 24 12:47:29 PM PDT 24
Finished Mar 24 12:47:33 PM PDT 24
Peak memory 198188 kb
Host smart-5bf03d02-48b7-4578-a11c-13aef5085dcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076886404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2076886404
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1657277340
Short name T202
Test name
Test status
Simulation time 44271475 ps
CPU time 1.18 seconds
Started Mar 24 12:47:18 PM PDT 24
Finished Mar 24 12:47:20 PM PDT 24
Peak memory 197072 kb
Host smart-ffdf8bbd-86c3-4754-8f5e-2511663e9267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657277340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1657277340
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2964307403
Short name T322
Test name
Test status
Simulation time 68601141 ps
CPU time 1.13 seconds
Started Mar 24 12:47:20 PM PDT 24
Finished Mar 24 12:47:22 PM PDT 24
Peak memory 195816 kb
Host smart-34fa5726-96d3-4290-bf3d-e93e2e1f79e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964307403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2964307403
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2801573616
Short name T362
Test name
Test status
Simulation time 43220609325 ps
CPU time 141.4 seconds
Started Mar 24 12:47:25 PM PDT 24
Finished Mar 24 12:49:46 PM PDT 24
Peak memory 198152 kb
Host smart-ffb9c8a7-4e24-4262-ad0c-40cc04fb178f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801573616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2801573616
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2562898600
Short name T495
Test name
Test status
Simulation time 107727606181 ps
CPU time 686 seconds
Started Mar 24 12:47:28 PM PDT 24
Finished Mar 24 12:58:54 PM PDT 24
Peak memory 198236 kb
Host smart-273eb8c7-9265-4d49-8f03-f9cd0ad56c60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2562898600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2562898600
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2750591054
Short name T292
Test name
Test status
Simulation time 24224658 ps
CPU time 0.56 seconds
Started Mar 24 12:47:25 PM PDT 24
Finished Mar 24 12:47:26 PM PDT 24
Peak memory 194552 kb
Host smart-0da956ec-b103-44e3-9d0c-cad327128206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750591054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2750591054
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1595656153
Short name T116
Test name
Test status
Simulation time 78841896 ps
CPU time 0.67 seconds
Started Mar 24 12:47:25 PM PDT 24
Finished Mar 24 12:47:26 PM PDT 24
Peak memory 194824 kb
Host smart-be283b14-593f-47af-ae18-6655c127c5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595656153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1595656153
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2479768748
Short name T149
Test name
Test status
Simulation time 733648192 ps
CPU time 6.2 seconds
Started Mar 24 12:47:28 PM PDT 24
Finished Mar 24 12:47:34 PM PDT 24
Peak memory 196856 kb
Host smart-50f36a04-e9b3-4e75-81ce-bbb59f0679d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479768748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2479768748
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1330008834
Short name T700
Test name
Test status
Simulation time 153009827 ps
CPU time 0.75 seconds
Started Mar 24 12:47:26 PM PDT 24
Finished Mar 24 12:47:27 PM PDT 24
Peak memory 194796 kb
Host smart-8c68530d-f42c-4819-95f6-47eae7031c44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330008834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1330008834
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1239486059
Short name T619
Test name
Test status
Simulation time 18807279 ps
CPU time 0.7 seconds
Started Mar 24 12:47:25 PM PDT 24
Finished Mar 24 12:47:26 PM PDT 24
Peak memory 195548 kb
Host smart-fbbf76ad-6dac-4cf8-8ed4-92a8d61913ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239486059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1239486059
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2263439819
Short name T327
Test name
Test status
Simulation time 199387940 ps
CPU time 2.19 seconds
Started Mar 24 12:47:30 PM PDT 24
Finished Mar 24 12:47:32 PM PDT 24
Peak memory 198052 kb
Host smart-d87c91b2-cfea-468c-a09d-b5280a94fb8e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263439819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2263439819
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1068171734
Short name T337
Test name
Test status
Simulation time 571231620 ps
CPU time 3.19 seconds
Started Mar 24 12:47:31 PM PDT 24
Finished Mar 24 12:47:35 PM PDT 24
Peak memory 197072 kb
Host smart-22dddea2-7f0e-42af-992d-75d97b6a65f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068171734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1068171734
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2843116028
Short name T191
Test name
Test status
Simulation time 42526500 ps
CPU time 1.22 seconds
Started Mar 24 12:47:24 PM PDT 24
Finished Mar 24 12:47:26 PM PDT 24
Peak memory 195840 kb
Host smart-27dd7236-bac9-4ebe-84ea-ec13f79029a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843116028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2843116028
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.630538878
Short name T564
Test name
Test status
Simulation time 63680581 ps
CPU time 1.12 seconds
Started Mar 24 12:47:25 PM PDT 24
Finished Mar 24 12:47:26 PM PDT 24
Peak memory 196552 kb
Host smart-22ea991c-5973-45c0-a461-11df40953d77
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630538878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.630538878
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3464652551
Short name T10
Test name
Test status
Simulation time 383575672 ps
CPU time 5.03 seconds
Started Mar 24 12:47:26 PM PDT 24
Finished Mar 24 12:47:31 PM PDT 24
Peak memory 198012 kb
Host smart-a78ac56e-184a-4e14-8ac9-b7f99a7184e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464652551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3464652551
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2250219937
Short name T670
Test name
Test status
Simulation time 81310046 ps
CPU time 1.29 seconds
Started Mar 24 12:47:26 PM PDT 24
Finished Mar 24 12:47:27 PM PDT 24
Peak memory 196740 kb
Host smart-4100f19b-964d-4223-a8e7-045b0232c38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250219937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2250219937
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2242409819
Short name T399
Test name
Test status
Simulation time 38365495 ps
CPU time 0.75 seconds
Started Mar 24 12:47:25 PM PDT 24
Finished Mar 24 12:47:26 PM PDT 24
Peak memory 195156 kb
Host smart-b808d19c-8ad6-472c-8dcf-c7bb7f593bc0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242409819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2242409819
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2723196841
Short name T117
Test name
Test status
Simulation time 5850710134 ps
CPU time 36.9 seconds
Started Mar 24 12:47:26 PM PDT 24
Finished Mar 24 12:48:03 PM PDT 24
Peak memory 198144 kb
Host smart-c6b71dd9-e1fa-404e-a11b-eae713386fe6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723196841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2723196841
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.1084592088
Short name T61
Test name
Test status
Simulation time 118021280069 ps
CPU time 1473.27 seconds
Started Mar 24 12:47:27 PM PDT 24
Finished Mar 24 01:12:00 PM PDT 24
Peak memory 198244 kb
Host smart-6ef8946b-6c05-40a9-9a36-427497222fd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1084592088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.1084592088
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1772293480
Short name T458
Test name
Test status
Simulation time 12525439 ps
CPU time 0.58 seconds
Started Mar 24 12:47:31 PM PDT 24
Finished Mar 24 12:47:33 PM PDT 24
Peak memory 194628 kb
Host smart-f35829e9-5dda-4ca1-89ee-d47584ea6668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772293480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1772293480
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2116109753
Short name T437
Test name
Test status
Simulation time 36844898 ps
CPU time 0.7 seconds
Started Mar 24 12:47:28 PM PDT 24
Finished Mar 24 12:47:29 PM PDT 24
Peak memory 194104 kb
Host smart-8615362b-bc53-497b-8004-124333541f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116109753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2116109753
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.365918168
Short name T114
Test name
Test status
Simulation time 1782059461 ps
CPU time 22.1 seconds
Started Mar 24 12:47:32 PM PDT 24
Finished Mar 24 12:47:55 PM PDT 24
Peak memory 196428 kb
Host smart-b80025b7-dbdf-4615-b873-c9c448b4e1ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365918168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.365918168
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3372700784
Short name T298
Test name
Test status
Simulation time 159820655 ps
CPU time 0.74 seconds
Started Mar 24 12:47:33 PM PDT 24
Finished Mar 24 12:47:34 PM PDT 24
Peak memory 196416 kb
Host smart-0635c9e6-59de-45ea-87c4-3c6f3b66a152
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372700784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3372700784
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3868318554
Short name T253
Test name
Test status
Simulation time 81015497 ps
CPU time 1.29 seconds
Started Mar 24 12:47:24 PM PDT 24
Finished Mar 24 12:47:25 PM PDT 24
Peak memory 196096 kb
Host smart-332c8698-6967-42a2-be3e-04c881c3fd01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868318554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3868318554
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3576057635
Short name T211
Test name
Test status
Simulation time 79104514 ps
CPU time 3.19 seconds
Started Mar 24 12:47:27 PM PDT 24
Finished Mar 24 12:47:30 PM PDT 24
Peak memory 198108 kb
Host smart-335cbe58-0715-498e-8c56-968d56c206fa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576057635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3576057635
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3050308873
Short name T663
Test name
Test status
Simulation time 120172325 ps
CPU time 1.33 seconds
Started Mar 24 12:47:27 PM PDT 24
Finished Mar 24 12:47:28 PM PDT 24
Peak memory 196820 kb
Host smart-a52345ef-e3a0-4d0f-94f9-0f6cf5801a72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050308873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3050308873
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2477054290
Short name T307
Test name
Test status
Simulation time 98401234 ps
CPU time 1.02 seconds
Started Mar 24 12:47:25 PM PDT 24
Finished Mar 24 12:47:27 PM PDT 24
Peak memory 195936 kb
Host smart-bb217491-440b-4e09-93d6-28292a1db5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477054290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2477054290
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2533412574
Short name T716
Test name
Test status
Simulation time 36523894 ps
CPU time 0.94 seconds
Started Mar 24 12:47:30 PM PDT 24
Finished Mar 24 12:47:31 PM PDT 24
Peak memory 195952 kb
Host smart-13ccc0f8-d0fc-466f-98ba-7a49307af696
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533412574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2533412574
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.624268942
Short name T420
Test name
Test status
Simulation time 550210452 ps
CPU time 3.33 seconds
Started Mar 24 12:47:33 PM PDT 24
Finished Mar 24 12:47:37 PM PDT 24
Peak memory 197988 kb
Host smart-05e538c0-66a0-40f4-84fc-26dd946b3d9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624268942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.624268942
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1882136440
Short name T203
Test name
Test status
Simulation time 163816408 ps
CPU time 0.99 seconds
Started Mar 24 12:47:26 PM PDT 24
Finished Mar 24 12:47:27 PM PDT 24
Peak memory 195828 kb
Host smart-e54c62a7-6a9b-4823-b2c9-ac2480a547e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882136440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1882136440
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1459047968
Short name T626
Test name
Test status
Simulation time 104508195 ps
CPU time 1.1 seconds
Started Mar 24 12:47:28 PM PDT 24
Finished Mar 24 12:47:29 PM PDT 24
Peak memory 195800 kb
Host smart-55d50799-4eb3-4a21-90b4-9ce7a81ab5de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459047968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1459047968
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.715984652
Short name T373
Test name
Test status
Simulation time 4064876749 ps
CPU time 46.83 seconds
Started Mar 24 12:47:33 PM PDT 24
Finished Mar 24 12:48:20 PM PDT 24
Peak memory 198168 kb
Host smart-18167c75-800e-47a5-925f-61a6e578b10e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715984652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.715984652
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3864119907
Short name T215
Test name
Test status
Simulation time 60471726 ps
CPU time 0.65 seconds
Started Mar 24 12:47:31 PM PDT 24
Finished Mar 24 12:47:32 PM PDT 24
Peak memory 194840 kb
Host smart-c7a02723-fe9e-4efc-892f-f203fd7774cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864119907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3864119907
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1735322685
Short name T638
Test name
Test status
Simulation time 56174044 ps
CPU time 0.64 seconds
Started Mar 24 12:47:33 PM PDT 24
Finished Mar 24 12:47:34 PM PDT 24
Peak memory 194600 kb
Host smart-60efa234-6b90-4009-9ec5-f30b2623f94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735322685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1735322685
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2720105532
Short name T507
Test name
Test status
Simulation time 281913810 ps
CPU time 8.81 seconds
Started Mar 24 12:47:31 PM PDT 24
Finished Mar 24 12:47:42 PM PDT 24
Peak memory 198000 kb
Host smart-ce0c0718-d770-4b16-b706-65d72068d5fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720105532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2720105532
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1058158414
Short name T581
Test name
Test status
Simulation time 115191826 ps
CPU time 1.03 seconds
Started Mar 24 12:47:34 PM PDT 24
Finished Mar 24 12:47:35 PM PDT 24
Peak memory 196832 kb
Host smart-3feb404e-7a3c-45cc-8eca-9468e6bba59f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058158414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1058158414
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3891631601
Short name T438
Test name
Test status
Simulation time 92576631 ps
CPU time 3.41 seconds
Started Mar 24 12:47:31 PM PDT 24
Finished Mar 24 12:47:36 PM PDT 24
Peak memory 198044 kb
Host smart-3df10ae1-8e6b-4b6c-b0f8-111e68bc4bd6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891631601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3891631601
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2343790915
Short name T533
Test name
Test status
Simulation time 585280229 ps
CPU time 3.05 seconds
Started Mar 24 12:47:34 PM PDT 24
Finished Mar 24 12:47:38 PM PDT 24
Peak memory 197972 kb
Host smart-d90ae714-405a-4622-9495-78ce67496f54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343790915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2343790915
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.808556624
Short name T393
Test name
Test status
Simulation time 70000497 ps
CPU time 0.9 seconds
Started Mar 24 12:47:32 PM PDT 24
Finished Mar 24 12:47:34 PM PDT 24
Peak memory 196632 kb
Host smart-d2d104c6-beaf-4820-816d-c55121edf50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808556624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.808556624
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1494287685
Short name T665
Test name
Test status
Simulation time 115816686 ps
CPU time 1.07 seconds
Started Mar 24 12:47:37 PM PDT 24
Finished Mar 24 12:47:38 PM PDT 24
Peak memory 196524 kb
Host smart-933d79a2-a888-48f4-ab99-03596417bb03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494287685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1494287685
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.246290277
Short name T280
Test name
Test status
Simulation time 892557794 ps
CPU time 5.05 seconds
Started Mar 24 12:47:33 PM PDT 24
Finished Mar 24 12:47:38 PM PDT 24
Peak memory 198184 kb
Host smart-cd06443f-547d-471c-8c05-2f1a32022f12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246290277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.246290277
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.393413382
Short name T60
Test name
Test status
Simulation time 280039091 ps
CPU time 1.21 seconds
Started Mar 24 12:47:30 PM PDT 24
Finished Mar 24 12:47:32 PM PDT 24
Peak memory 195784 kb
Host smart-6708df0b-14d1-433f-b879-7fb6a95aba8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393413382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.393413382
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2014640844
Short name T16
Test name
Test status
Simulation time 42967996 ps
CPU time 0.89 seconds
Started Mar 24 12:47:33 PM PDT 24
Finished Mar 24 12:47:34 PM PDT 24
Peak memory 196716 kb
Host smart-4ec76a47-6214-4107-b7d9-9edb32b0071a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014640844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2014640844
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.975667790
Short name T406
Test name
Test status
Simulation time 15349022919 ps
CPU time 167.45 seconds
Started Mar 24 12:47:30 PM PDT 24
Finished Mar 24 12:50:18 PM PDT 24
Peak memory 198200 kb
Host smart-d11703eb-b9de-41eb-bed8-42fd5b583285
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975667790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.975667790
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3920721219
Short name T430
Test name
Test status
Simulation time 42011001 ps
CPU time 0.61 seconds
Started Mar 24 12:47:32 PM PDT 24
Finished Mar 24 12:47:34 PM PDT 24
Peak memory 193912 kb
Host smart-9d6d4835-b958-47a4-9d9c-9ed947249aa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920721219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3920721219
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.476822832
Short name T52
Test name
Test status
Simulation time 129295131 ps
CPU time 0.77 seconds
Started Mar 24 12:47:32 PM PDT 24
Finished Mar 24 12:47:34 PM PDT 24
Peak memory 195196 kb
Host smart-cd667fba-140c-43b2-82f5-383e9614350d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476822832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.476822832
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.507562498
Short name T409
Test name
Test status
Simulation time 464273945 ps
CPU time 25.09 seconds
Started Mar 24 12:47:30 PM PDT 24
Finished Mar 24 12:47:56 PM PDT 24
Peak memory 196992 kb
Host smart-cc3a5c06-69c2-4c46-9ffb-c68ed3dc673c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507562498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.507562498
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.392120616
Short name T499
Test name
Test status
Simulation time 90579567 ps
CPU time 0.62 seconds
Started Mar 24 12:47:34 PM PDT 24
Finished Mar 24 12:47:35 PM PDT 24
Peak memory 194416 kb
Host smart-ff680165-8918-482d-b028-e76a0bb65709
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392120616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.392120616
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.219565081
Short name T125
Test name
Test status
Simulation time 73519330 ps
CPU time 1.21 seconds
Started Mar 24 12:47:32 PM PDT 24
Finished Mar 24 12:47:35 PM PDT 24
Peak memory 196556 kb
Host smart-6bcba6e9-cf58-44aa-a4d1-0cde4ccd37ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219565081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.219565081
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3898766648
Short name T715
Test name
Test status
Simulation time 325406560 ps
CPU time 2.84 seconds
Started Mar 24 12:47:31 PM PDT 24
Finished Mar 24 12:47:35 PM PDT 24
Peak memory 198084 kb
Host smart-76ca50dd-1358-4a70-be09-9601ff7d1b33
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898766648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3898766648
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2502208093
Short name T275
Test name
Test status
Simulation time 158432344 ps
CPU time 2.85 seconds
Started Mar 24 12:47:32 PM PDT 24
Finished Mar 24 12:47:36 PM PDT 24
Peak memory 195892 kb
Host smart-be4927ae-def2-4b56-8df9-4b4a84131776
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502208093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2502208093
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1407598472
Short name T412
Test name
Test status
Simulation time 59020231 ps
CPU time 0.85 seconds
Started Mar 24 12:47:33 PM PDT 24
Finished Mar 24 12:47:34 PM PDT 24
Peak memory 197424 kb
Host smart-4cb76cd9-d8ad-4738-ab80-52e286b406e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407598472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1407598472
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3270134728
Short name T379
Test name
Test status
Simulation time 44984786 ps
CPU time 0.77 seconds
Started Mar 24 12:47:34 PM PDT 24
Finished Mar 24 12:47:36 PM PDT 24
Peak memory 195444 kb
Host smart-e7ab95b4-9bee-44d9-be97-5de814893563
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270134728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3270134728
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.4260893203
Short name T642
Test name
Test status
Simulation time 47689880 ps
CPU time 2.17 seconds
Started Mar 24 12:47:32 PM PDT 24
Finished Mar 24 12:47:35 PM PDT 24
Peak memory 198012 kb
Host smart-08c45732-0e7b-4c32-aef1-759be6061d3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260893203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.4260893203
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1098667331
Short name T148
Test name
Test status
Simulation time 63467867 ps
CPU time 0.96 seconds
Started Mar 24 12:47:30 PM PDT 24
Finished Mar 24 12:47:32 PM PDT 24
Peak memory 195720 kb
Host smart-b90d9884-664b-4447-a379-b7879ff9e8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098667331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1098667331
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3824019817
Short name T108
Test name
Test status
Simulation time 280240617 ps
CPU time 1.4 seconds
Started Mar 24 12:47:34 PM PDT 24
Finished Mar 24 12:47:35 PM PDT 24
Peak memory 198020 kb
Host smart-5076429b-b8a0-48db-a28d-3c7a042ecb45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824019817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3824019817
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.818820668
Short name T138
Test name
Test status
Simulation time 4873211621 ps
CPU time 65.46 seconds
Started Mar 24 12:47:33 PM PDT 24
Finished Mar 24 12:48:39 PM PDT 24
Peak memory 198136 kb
Host smart-025fb961-6f25-4b6d-bdbb-56814a196a66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818820668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.818820668
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3691326794
Short name T439
Test name
Test status
Simulation time 44073593 ps
CPU time 0.57 seconds
Started Mar 24 12:47:39 PM PDT 24
Finished Mar 24 12:47:40 PM PDT 24
Peak memory 194152 kb
Host smart-4b75fbd5-06f8-4ab7-b2d0-f85695a8f9cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691326794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3691326794
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.373114106
Short name T521
Test name
Test status
Simulation time 120970857 ps
CPU time 0.78 seconds
Started Mar 24 12:47:38 PM PDT 24
Finished Mar 24 12:47:39 PM PDT 24
Peak memory 195448 kb
Host smart-33d6b729-3761-483f-bb3c-92fe65a2c0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373114106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.373114106
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3897576686
Short name T523
Test name
Test status
Simulation time 708706232 ps
CPU time 7.38 seconds
Started Mar 24 12:47:37 PM PDT 24
Finished Mar 24 12:47:44 PM PDT 24
Peak memory 197920 kb
Host smart-9c05a53a-fdfa-4c07-bed9-2a1b868b5a92
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897576686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3897576686
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3407556398
Short name T501
Test name
Test status
Simulation time 326781962 ps
CPU time 1.06 seconds
Started Mar 24 12:47:39 PM PDT 24
Finished Mar 24 12:47:40 PM PDT 24
Peak memory 196596 kb
Host smart-c1aa093a-987b-4a93-b806-68e08d3130f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407556398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3407556398
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3961858786
Short name T389
Test name
Test status
Simulation time 117963879 ps
CPU time 0.82 seconds
Started Mar 24 12:47:39 PM PDT 24
Finished Mar 24 12:47:39 PM PDT 24
Peak memory 195760 kb
Host smart-5ce94d07-2651-41cd-86f6-9a9991ee56b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961858786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3961858786
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2332261289
Short name T598
Test name
Test status
Simulation time 203426029 ps
CPU time 1.53 seconds
Started Mar 24 12:47:43 PM PDT 24
Finished Mar 24 12:47:45 PM PDT 24
Peak memory 196768 kb
Host smart-35951493-9392-4535-afea-787091ee9628
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332261289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2332261289
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3199317137
Short name T244
Test name
Test status
Simulation time 505931688 ps
CPU time 2.46 seconds
Started Mar 24 12:47:37 PM PDT 24
Finished Mar 24 12:47:39 PM PDT 24
Peak memory 196960 kb
Host smart-223fe2bf-e9de-4856-8576-15d62764fcd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199317137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3199317137
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.4203748263
Short name T398
Test name
Test status
Simulation time 399386448 ps
CPU time 1.19 seconds
Started Mar 24 12:47:37 PM PDT 24
Finished Mar 24 12:47:38 PM PDT 24
Peak memory 196580 kb
Host smart-948b0f4b-3be7-4213-af55-61b5095e72ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203748263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.4203748263
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2181059710
Short name T113
Test name
Test status
Simulation time 72263537 ps
CPU time 0.72 seconds
Started Mar 24 12:47:31 PM PDT 24
Finished Mar 24 12:47:33 PM PDT 24
Peak memory 195364 kb
Host smart-4ee837e6-cecc-4a7d-b545-6269a76ad6bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181059710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2181059710
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1290852608
Short name T710
Test name
Test status
Simulation time 45123358 ps
CPU time 1.99 seconds
Started Mar 24 12:47:39 PM PDT 24
Finished Mar 24 12:47:41 PM PDT 24
Peak memory 197868 kb
Host smart-07f874e2-412a-4f17-a726-6206e0411082
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290852608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1290852608
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.278538648
Short name T403
Test name
Test status
Simulation time 84448072 ps
CPU time 1.29 seconds
Started Mar 24 12:47:30 PM PDT 24
Finished Mar 24 12:47:32 PM PDT 24
Peak memory 196720 kb
Host smart-a9261617-da3a-409d-b27d-87ceaff10f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278538648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.278538648
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3956351938
Short name T17
Test name
Test status
Simulation time 171872058 ps
CPU time 1 seconds
Started Mar 24 12:47:32 PM PDT 24
Finished Mar 24 12:47:34 PM PDT 24
Peak memory 195756 kb
Host smart-ede7bcc9-2133-4577-b66a-db6f9fca805e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956351938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3956351938
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1408148743
Short name T537
Test name
Test status
Simulation time 46182513208 ps
CPU time 64.42 seconds
Started Mar 24 12:47:38 PM PDT 24
Finished Mar 24 12:48:43 PM PDT 24
Peak memory 198136 kb
Host smart-1c6542c0-69d4-434c-ad2e-5dbf61e9588e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408148743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1408148743
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.2814945901
Short name T340
Test name
Test status
Simulation time 46527363107 ps
CPU time 904.67 seconds
Started Mar 24 12:47:38 PM PDT 24
Finished Mar 24 01:02:42 PM PDT 24
Peak memory 198268 kb
Host smart-a199d421-5eaf-4682-931f-7c82ed6167d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2814945901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.2814945901
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1370283362
Short name T305
Test name
Test status
Simulation time 28428697 ps
CPU time 0.59 seconds
Started Mar 24 12:45:31 PM PDT 24
Finished Mar 24 12:45:31 PM PDT 24
Peak memory 193940 kb
Host smart-d8d75676-d44a-454b-be45-bf777af77b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370283362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1370283362
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2081707091
Short name T504
Test name
Test status
Simulation time 92725931 ps
CPU time 0.72 seconds
Started Mar 24 12:45:30 PM PDT 24
Finished Mar 24 12:45:31 PM PDT 24
Peak memory 194160 kb
Host smart-b61c8ea1-9dae-4eb4-827d-e24db1a78a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081707091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2081707091
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.4250462330
Short name T146
Test name
Test status
Simulation time 724568819 ps
CPU time 26.07 seconds
Started Mar 24 12:45:35 PM PDT 24
Finished Mar 24 12:46:02 PM PDT 24
Peak memory 196892 kb
Host smart-b58b69c4-54f0-4db3-988f-a74132e76630
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250462330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.4250462330
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1449966586
Short name T392
Test name
Test status
Simulation time 322998338 ps
CPU time 0.96 seconds
Started Mar 24 12:45:32 PM PDT 24
Finished Mar 24 12:45:33 PM PDT 24
Peak memory 196532 kb
Host smart-96c0bce6-d79c-4720-9704-81e5368da7ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449966586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1449966586
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3577764570
Short name T342
Test name
Test status
Simulation time 662294804 ps
CPU time 1.22 seconds
Started Mar 24 12:45:30 PM PDT 24
Finished Mar 24 12:45:31 PM PDT 24
Peak memory 196060 kb
Host smart-a5ab695f-6241-46db-aeae-f18fb6c13bbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577764570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3577764570
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.439157590
Short name T272
Test name
Test status
Simulation time 304092689 ps
CPU time 3.23 seconds
Started Mar 24 12:45:22 PM PDT 24
Finished Mar 24 12:45:26 PM PDT 24
Peak memory 197924 kb
Host smart-2fdbc564-b895-4d92-8454-1f9c23b6b751
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439157590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.439157590
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.4112030445
Short name T623
Test name
Test status
Simulation time 54524576 ps
CPU time 1.16 seconds
Started Mar 24 12:45:20 PM PDT 24
Finished Mar 24 12:45:22 PM PDT 24
Peak memory 196584 kb
Host smart-f6237be9-5d3a-4f18-83d2-1b94d8e14a40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112030445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
4112030445
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1467329229
Short name T524
Test name
Test status
Simulation time 45189776 ps
CPU time 0.74 seconds
Started Mar 24 12:45:24 PM PDT 24
Finished Mar 24 12:45:25 PM PDT 24
Peak memory 195288 kb
Host smart-d2a779cf-45af-4e0e-bc9a-7034396c0558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467329229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1467329229
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1424189377
Short name T424
Test name
Test status
Simulation time 69225879 ps
CPU time 0.91 seconds
Started Mar 24 12:45:15 PM PDT 24
Finished Mar 24 12:45:16 PM PDT 24
Peak memory 196552 kb
Host smart-ec7e4e7c-39ec-4f30-8f95-da2bd350f5d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424189377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1424189377
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3169039315
Short name T490
Test name
Test status
Simulation time 25561857 ps
CPU time 1.24 seconds
Started Mar 24 12:45:25 PM PDT 24
Finished Mar 24 12:45:26 PM PDT 24
Peak memory 197916 kb
Host smart-2866efac-e28d-43b9-9f9f-342b1b2b0fd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169039315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3169039315
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3876641590
Short name T496
Test name
Test status
Simulation time 487397571 ps
CPU time 1.25 seconds
Started Mar 24 12:45:17 PM PDT 24
Finished Mar 24 12:45:18 PM PDT 24
Peak memory 196740 kb
Host smart-5d5671a9-6c77-4724-b263-cf766fa0d801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876641590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3876641590
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1697508351
Short name T656
Test name
Test status
Simulation time 254990444 ps
CPU time 1.13 seconds
Started Mar 24 12:45:27 PM PDT 24
Finished Mar 24 12:45:29 PM PDT 24
Peak memory 196792 kb
Host smart-456e439d-8968-40fe-8df0-544385d2e16a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697508351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1697508351
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3535518713
Short name T509
Test name
Test status
Simulation time 3182833590 ps
CPU time 88.79 seconds
Started Mar 24 12:45:20 PM PDT 24
Finished Mar 24 12:46:49 PM PDT 24
Peak memory 198156 kb
Host smart-41bd5fe9-ddbe-439c-9324-69f4a1d5dd3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535518713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3535518713
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2356235726
Short name T489
Test name
Test status
Simulation time 15652576 ps
CPU time 0.57 seconds
Started Mar 24 12:45:33 PM PDT 24
Finished Mar 24 12:45:34 PM PDT 24
Peak memory 194832 kb
Host smart-47dc66e4-1265-46c6-845b-7cda7cb6d631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356235726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2356235726
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.452187325
Short name T355
Test name
Test status
Simulation time 21203311 ps
CPU time 0.75 seconds
Started Mar 24 12:45:15 PM PDT 24
Finished Mar 24 12:45:16 PM PDT 24
Peak memory 196036 kb
Host smart-4ff1bbaa-72bb-41f5-ab3d-a634cf6109ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452187325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.452187325
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2913137228
Short name T720
Test name
Test status
Simulation time 722229587 ps
CPU time 6.77 seconds
Started Mar 24 12:45:17 PM PDT 24
Finished Mar 24 12:45:25 PM PDT 24
Peak memory 196812 kb
Host smart-612ae3d0-d783-414c-b536-fb5166d9e046
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913137228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2913137228
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1609031087
Short name T685
Test name
Test status
Simulation time 44480113 ps
CPU time 0.75 seconds
Started Mar 24 12:45:33 PM PDT 24
Finished Mar 24 12:45:34 PM PDT 24
Peak memory 196040 kb
Host smart-8fe44acf-5830-4b1f-b0f0-24d45f186815
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609031087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1609031087
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2819684209
Short name T98
Test name
Test status
Simulation time 364846309 ps
CPU time 1.21 seconds
Started Mar 24 12:45:21 PM PDT 24
Finished Mar 24 12:45:23 PM PDT 24
Peak memory 198064 kb
Host smart-f6843d77-74ea-4020-b7cd-511f587fe57c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819684209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2819684209
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.4006152816
Short name T695
Test name
Test status
Simulation time 49597650 ps
CPU time 1.84 seconds
Started Mar 24 12:45:34 PM PDT 24
Finished Mar 24 12:45:35 PM PDT 24
Peak memory 198036 kb
Host smart-f9b19d8c-30af-4a0e-be3f-fe5311330be4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006152816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.4006152816
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1715056835
Short name T270
Test name
Test status
Simulation time 128381241 ps
CPU time 2.14 seconds
Started Mar 24 12:45:17 PM PDT 24
Finished Mar 24 12:45:20 PM PDT 24
Peak memory 197040 kb
Host smart-784a33ee-608e-4382-b326-9aed0d6b351c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715056835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1715056835
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3321396444
Short name T662
Test name
Test status
Simulation time 58084532 ps
CPU time 0.69 seconds
Started Mar 24 12:45:19 PM PDT 24
Finished Mar 24 12:45:20 PM PDT 24
Peak memory 195380 kb
Host smart-ab737138-945a-4984-a32b-1301c0060742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321396444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3321396444
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1500539819
Short name T384
Test name
Test status
Simulation time 28228026 ps
CPU time 0.84 seconds
Started Mar 24 12:45:26 PM PDT 24
Finished Mar 24 12:45:27 PM PDT 24
Peak memory 196212 kb
Host smart-72f4b114-11da-4f7f-aa0b-123cbe027111
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500539819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1500539819
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2951536031
Short name T677
Test name
Test status
Simulation time 3260438837 ps
CPU time 3.4 seconds
Started Mar 24 12:45:33 PM PDT 24
Finished Mar 24 12:45:37 PM PDT 24
Peak memory 198112 kb
Host smart-50d5c9be-35b7-4bd1-a4ce-12203e18e331
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951536031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2951536031
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3828264454
Short name T668
Test name
Test status
Simulation time 127482281 ps
CPU time 1.2 seconds
Started Mar 24 12:45:18 PM PDT 24
Finished Mar 24 12:45:20 PM PDT 24
Peak memory 195484 kb
Host smart-067d512d-4cbe-4a8f-ab78-40ecc55007b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828264454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3828264454
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.642909375
Short name T616
Test name
Test status
Simulation time 114270630 ps
CPU time 1.09 seconds
Started Mar 24 12:45:17 PM PDT 24
Finished Mar 24 12:45:19 PM PDT 24
Peak memory 196468 kb
Host smart-20e431d8-e7bc-4574-887b-7b73e92d1742
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642909375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.642909375
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1067866
Short name T556
Test name
Test status
Simulation time 11576473162 ps
CPU time 62.58 seconds
Started Mar 24 12:45:20 PM PDT 24
Finished Mar 24 12:46:23 PM PDT 24
Peak memory 198144 kb
Host smart-27cbf9d9-f241-4955-8790-58d6a3d441ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TES
T_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio
_stress_all.1067866
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1952093585
Short name T510
Test name
Test status
Simulation time 43920512 ps
CPU time 0.59 seconds
Started Mar 24 12:45:36 PM PDT 24
Finished Mar 24 12:45:37 PM PDT 24
Peak memory 194028 kb
Host smart-5afb2e30-76f8-4e2b-bb4f-b2effa26916a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952093585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1952093585
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1344428722
Short name T192
Test name
Test status
Simulation time 39438574 ps
CPU time 0.6 seconds
Started Mar 24 12:45:24 PM PDT 24
Finished Mar 24 12:45:25 PM PDT 24
Peak memory 193888 kb
Host smart-a9a995d7-293e-4281-8b16-36dcc547912b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344428722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1344428722
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2556818031
Short name T506
Test name
Test status
Simulation time 611541734 ps
CPU time 9.42 seconds
Started Mar 24 12:45:25 PM PDT 24
Finished Mar 24 12:45:35 PM PDT 24
Peak memory 196576 kb
Host smart-7f127271-892e-4e47-b8e2-534a038f159c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556818031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2556818031
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3411896975
Short name T378
Test name
Test status
Simulation time 117505655 ps
CPU time 0.82 seconds
Started Mar 24 12:45:34 PM PDT 24
Finished Mar 24 12:45:35 PM PDT 24
Peak memory 196616 kb
Host smart-d7bfa0f2-1380-4720-aa9d-cf20d8e5ef78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411896975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3411896975
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.3318826501
Short name T112
Test name
Test status
Simulation time 173334808 ps
CPU time 0.97 seconds
Started Mar 24 12:45:20 PM PDT 24
Finished Mar 24 12:45:22 PM PDT 24
Peak memory 196464 kb
Host smart-bbd9743f-3643-4cb7-affd-0e342b9f15c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318826501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.3318826501
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2544493489
Short name T329
Test name
Test status
Simulation time 322173392 ps
CPU time 3.12 seconds
Started Mar 24 12:45:34 PM PDT 24
Finished Mar 24 12:45:37 PM PDT 24
Peak memory 198116 kb
Host smart-ee3e634c-8593-4429-912d-ea6429439f93
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544493489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2544493489
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2876072714
Short name T162
Test name
Test status
Simulation time 511707693 ps
CPU time 2.39 seconds
Started Mar 24 12:45:36 PM PDT 24
Finished Mar 24 12:45:39 PM PDT 24
Peak memory 196888 kb
Host smart-ed605b2d-cf87-4edd-8d24-eac3abc1ad51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876072714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2876072714
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3062859289
Short name T208
Test name
Test status
Simulation time 93415109 ps
CPU time 1.07 seconds
Started Mar 24 12:45:20 PM PDT 24
Finished Mar 24 12:45:21 PM PDT 24
Peak memory 196888 kb
Host smart-6bb29d75-7000-4876-877e-51a750a7d2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062859289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3062859289
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1058309674
Short name T150
Test name
Test status
Simulation time 148689764 ps
CPU time 1.33 seconds
Started Mar 24 12:45:37 PM PDT 24
Finished Mar 24 12:45:38 PM PDT 24
Peak memory 195840 kb
Host smart-68384407-2c2b-46c7-b087-753be318d1b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058309674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1058309674
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2685300537
Short name T585
Test name
Test status
Simulation time 604866990 ps
CPU time 3.8 seconds
Started Mar 24 12:45:38 PM PDT 24
Finished Mar 24 12:45:41 PM PDT 24
Peak memory 197904 kb
Host smart-828556e3-9189-400d-86f4-25d2aaed7b85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685300537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2685300537
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2002814374
Short name T261
Test name
Test status
Simulation time 172511775 ps
CPU time 1.16 seconds
Started Mar 24 12:45:22 PM PDT 24
Finished Mar 24 12:45:23 PM PDT 24
Peak memory 196388 kb
Host smart-12556611-6026-42a4-96f9-bf26713c145d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002814374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2002814374
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.422946438
Short name T160
Test name
Test status
Simulation time 74282733 ps
CPU time 1.24 seconds
Started Mar 24 12:45:34 PM PDT 24
Finished Mar 24 12:45:35 PM PDT 24
Peak memory 196576 kb
Host smart-4e8bcf36-0a71-4c86-bf29-effef8bc4028
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422946438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.422946438
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2678365851
Short name T294
Test name
Test status
Simulation time 11160939722 ps
CPU time 115.87 seconds
Started Mar 24 12:45:29 PM PDT 24
Finished Mar 24 12:47:25 PM PDT 24
Peak memory 198236 kb
Host smart-02eabe50-fce2-4140-8df8-a0c580efad6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678365851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2678365851
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.204810906
Short name T672
Test name
Test status
Simulation time 1008274157060 ps
CPU time 2347.99 seconds
Started Mar 24 12:45:23 PM PDT 24
Finished Mar 24 01:24:32 PM PDT 24
Peak memory 198276 kb
Host smart-90b418fb-bc6f-447a-ad61-60a46e07ebfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=204810906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.204810906
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3023251704
Short name T580
Test name
Test status
Simulation time 91513129 ps
CPU time 0.54 seconds
Started Mar 24 12:45:40 PM PDT 24
Finished Mar 24 12:45:41 PM PDT 24
Peak memory 193944 kb
Host smart-b74828ac-2d7f-4f8b-bf39-d8dd39821057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023251704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3023251704
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.860437621
Short name T529
Test name
Test status
Simulation time 55547015 ps
CPU time 0.63 seconds
Started Mar 24 12:45:38 PM PDT 24
Finished Mar 24 12:45:39 PM PDT 24
Peak memory 194736 kb
Host smart-5bc4ec74-9afa-420f-881f-463a393425d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860437621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.860437621
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.4176900680
Short name T388
Test name
Test status
Simulation time 150113119 ps
CPU time 5.36 seconds
Started Mar 24 12:45:37 PM PDT 24
Finished Mar 24 12:45:43 PM PDT 24
Peak memory 198004 kb
Host smart-e731943c-4dad-46ce-85bb-076688441df7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176900680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.4176900680
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.657597235
Short name T602
Test name
Test status
Simulation time 262291991 ps
CPU time 0.64 seconds
Started Mar 24 12:45:40 PM PDT 24
Finished Mar 24 12:45:41 PM PDT 24
Peak memory 194588 kb
Host smart-cb31a079-02f0-4fa3-89e3-67e5453cb7f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657597235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.657597235
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3485134069
Short name T374
Test name
Test status
Simulation time 129799548 ps
CPU time 1.14 seconds
Started Mar 24 12:45:30 PM PDT 24
Finished Mar 24 12:45:31 PM PDT 24
Peak memory 195792 kb
Host smart-66dfa005-fe0b-4b05-9632-01eb8a36cccf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485134069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3485134069
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3633593743
Short name T351
Test name
Test status
Simulation time 330020974 ps
CPU time 3.55 seconds
Started Mar 24 12:45:34 PM PDT 24
Finished Mar 24 12:45:37 PM PDT 24
Peak memory 198060 kb
Host smart-f7b2300d-8944-4e10-9bd5-bc5fcaf8d2ca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633593743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3633593743
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2027767397
Short name T391
Test name
Test status
Simulation time 114996658 ps
CPU time 3.13 seconds
Started Mar 24 12:45:27 PM PDT 24
Finished Mar 24 12:45:31 PM PDT 24
Peak memory 198020 kb
Host smart-be464627-e713-4cc3-b79a-efaed7f77927
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027767397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2027767397
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2261356527
Short name T664
Test name
Test status
Simulation time 31809876 ps
CPU time 0.82 seconds
Started Mar 24 12:45:29 PM PDT 24
Finished Mar 24 12:45:30 PM PDT 24
Peak memory 196864 kb
Host smart-e18a1ea7-a729-491c-b7c2-7021d9261aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261356527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2261356527
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.634932471
Short name T629
Test name
Test status
Simulation time 76458444 ps
CPU time 0.73 seconds
Started Mar 24 12:45:29 PM PDT 24
Finished Mar 24 12:45:31 PM PDT 24
Peak memory 194384 kb
Host smart-c205d3c5-01f2-41a9-9845-b9c260864ef1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634932471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.634932471
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2651057886
Short name T410
Test name
Test status
Simulation time 384683547 ps
CPU time 5.84 seconds
Started Mar 24 12:45:35 PM PDT 24
Finished Mar 24 12:45:41 PM PDT 24
Peak memory 197976 kb
Host smart-60fd4251-8cf3-4d2c-9fef-5978aad3b662
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651057886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2651057886
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.882782580
Short name T464
Test name
Test status
Simulation time 37623500 ps
CPU time 0.83 seconds
Started Mar 24 12:45:27 PM PDT 24
Finished Mar 24 12:45:28 PM PDT 24
Peak memory 195380 kb
Host smart-36f7bed5-e315-429c-b3ef-45401fc02cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882782580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.882782580
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2863247539
Short name T345
Test name
Test status
Simulation time 169904963 ps
CPU time 1.24 seconds
Started Mar 24 12:45:30 PM PDT 24
Finished Mar 24 12:45:31 PM PDT 24
Peak memory 195520 kb
Host smart-649c590a-ab81-4a32-86dd-c4d786b13883
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863247539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2863247539
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.293536044
Short name T339
Test name
Test status
Simulation time 33570127401 ps
CPU time 220.98 seconds
Started Mar 24 12:45:34 PM PDT 24
Finished Mar 24 12:49:15 PM PDT 24
Peak memory 198128 kb
Host smart-4beac0de-f4a9-45e0-b115-481ee48ce819
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293536044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.293536044
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1621466317
Short name T273
Test name
Test status
Simulation time 71296093 ps
CPU time 0.6 seconds
Started Mar 24 12:45:45 PM PDT 24
Finished Mar 24 12:45:45 PM PDT 24
Peak memory 194068 kb
Host smart-d76eee58-27f2-44fe-aa6f-bd87a7e434fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621466317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1621466317
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3923533709
Short name T512
Test name
Test status
Simulation time 52272914 ps
CPU time 0.66 seconds
Started Mar 24 12:45:43 PM PDT 24
Finished Mar 24 12:45:43 PM PDT 24
Peak memory 193944 kb
Host smart-3a2dadcc-48da-464e-be52-fb937d702b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923533709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3923533709
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1771883374
Short name T219
Test name
Test status
Simulation time 2120128902 ps
CPU time 9.52 seconds
Started Mar 24 12:45:38 PM PDT 24
Finished Mar 24 12:45:48 PM PDT 24
Peak memory 197012 kb
Host smart-7539c7a2-a65a-4efe-bb7b-9a91399c540b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771883374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1771883374
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2503161944
Short name T707
Test name
Test status
Simulation time 305920197 ps
CPU time 1 seconds
Started Mar 24 12:45:40 PM PDT 24
Finished Mar 24 12:45:41 PM PDT 24
Peak memory 196388 kb
Host smart-f29fe2b3-890f-4d5f-ad1e-355525428a4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503161944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2503161944
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2856289398
Short name T679
Test name
Test status
Simulation time 45908462 ps
CPU time 0.87 seconds
Started Mar 24 12:45:40 PM PDT 24
Finished Mar 24 12:45:41 PM PDT 24
Peak memory 195712 kb
Host smart-a7007d90-a734-43f4-9fde-d0643932e0fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856289398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2856289398
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.55216067
Short name T554
Test name
Test status
Simulation time 146968139 ps
CPU time 3.15 seconds
Started Mar 24 12:45:44 PM PDT 24
Finished Mar 24 12:45:47 PM PDT 24
Peak memory 198116 kb
Host smart-221f25f8-71e0-4e10-839d-57c4894184ba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55216067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.gpio_intr_with_filter_rand_intr_event.55216067
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3475866678
Short name T463
Test name
Test status
Simulation time 237169564 ps
CPU time 1.93 seconds
Started Mar 24 12:45:41 PM PDT 24
Finished Mar 24 12:45:43 PM PDT 24
Peak memory 195724 kb
Host smart-f5529817-00d6-413d-91da-edfb005c0d14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475866678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3475866678
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.655239478
Short name T559
Test name
Test status
Simulation time 61247299 ps
CPU time 0.95 seconds
Started Mar 24 12:45:39 PM PDT 24
Finished Mar 24 12:45:40 PM PDT 24
Peak memory 196532 kb
Host smart-db59fdc6-99d6-4b17-9c35-8bfe8f55b2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655239478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.655239478
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3184886754
Short name T326
Test name
Test status
Simulation time 48895495 ps
CPU time 1.12 seconds
Started Mar 24 12:45:40 PM PDT 24
Finished Mar 24 12:45:41 PM PDT 24
Peak memory 196780 kb
Host smart-ed378a4f-d63f-4dfb-b86b-c0b944b4b8be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184886754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3184886754
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3480038574
Short name T132
Test name
Test status
Simulation time 37113142 ps
CPU time 1.82 seconds
Started Mar 24 12:45:39 PM PDT 24
Finished Mar 24 12:45:41 PM PDT 24
Peak memory 198016 kb
Host smart-bc6d7602-0936-477a-a361-5f3f6f78d324
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480038574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3480038574
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2696669908
Short name T246
Test name
Test status
Simulation time 52825588 ps
CPU time 1.3 seconds
Started Mar 24 12:45:35 PM PDT 24
Finished Mar 24 12:45:36 PM PDT 24
Peak memory 198032 kb
Host smart-af21d6a5-2f74-42bb-bed8-db64af28d0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696669908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2696669908
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3175961764
Short name T671
Test name
Test status
Simulation time 235184117 ps
CPU time 1.01 seconds
Started Mar 24 12:45:41 PM PDT 24
Finished Mar 24 12:45:42 PM PDT 24
Peak memory 195744 kb
Host smart-ddff9d90-c8fc-4477-bbf9-6e923a217baf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175961764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3175961764
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.274186605
Short name T55
Test name
Test status
Simulation time 3621050804 ps
CPU time 39.18 seconds
Started Mar 24 12:45:42 PM PDT 24
Finished Mar 24 12:46:21 PM PDT 24
Peak memory 198192 kb
Host smart-a93dc281-7afc-409a-b1a7-c21232657729
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274186605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.274186605
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1762839979
Short name T883
Test name
Test status
Simulation time 56503614 ps
CPU time 0.99 seconds
Started Mar 24 12:33:22 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 192136 kb
Host smart-2ed07b9c-c80d-4fc5-98a4-33570e8c624f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1762839979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1762839979
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2497792208
Short name T927
Test name
Test status
Simulation time 137435416 ps
CPU time 0.94 seconds
Started Mar 24 12:33:17 PM PDT 24
Finished Mar 24 12:33:18 PM PDT 24
Peak memory 191936 kb
Host smart-911d16d7-4b26-4cdc-af1e-5398954fb66f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497792208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2497792208
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1550465243
Short name T861
Test name
Test status
Simulation time 249279739 ps
CPU time 1.09 seconds
Started Mar 24 12:33:07 PM PDT 24
Finished Mar 24 12:33:10 PM PDT 24
Peak memory 191992 kb
Host smart-60e5c5a6-b717-420b-945e-a5e8dfd7116b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1550465243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1550465243
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2906890409
Short name T867
Test name
Test status
Simulation time 37527218 ps
CPU time 0.82 seconds
Started Mar 24 12:33:19 PM PDT 24
Finished Mar 24 12:33:22 PM PDT 24
Peak memory 191960 kb
Host smart-5590bcda-ade8-4e84-8dcc-416d58c17905
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906890409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2906890409
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.4096451067
Short name T923
Test name
Test status
Simulation time 239342912 ps
CPU time 1.14 seconds
Started Mar 24 12:33:05 PM PDT 24
Finished Mar 24 12:33:07 PM PDT 24
Peak memory 192156 kb
Host smart-6507ca49-447e-43de-85f8-a4af3d368f63
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4096451067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.4096451067
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2085183813
Short name T949
Test name
Test status
Simulation time 1746708945 ps
CPU time 1.41 seconds
Started Mar 24 12:33:02 PM PDT 24
Finished Mar 24 12:33:04 PM PDT 24
Peak memory 192144 kb
Host smart-311cfe57-a511-4bae-8d7a-64f125b91371
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085183813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2085183813
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.319015180
Short name T879
Test name
Test status
Simulation time 518797332 ps
CPU time 1.01 seconds
Started Mar 24 12:33:12 PM PDT 24
Finished Mar 24 12:33:13 PM PDT 24
Peak memory 192080 kb
Host smart-50b1303d-d4db-4324-9472-f37bac6f4f35
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=319015180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.319015180
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3122183673
Short name T864
Test name
Test status
Simulation time 248674908 ps
CPU time 1.03 seconds
Started Mar 24 12:33:03 PM PDT 24
Finished Mar 24 12:33:04 PM PDT 24
Peak memory 192128 kb
Host smart-9179811c-840a-46c7-a5aa-235bfbe0206f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122183673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3122183673
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3808159048
Short name T856
Test name
Test status
Simulation time 72095834 ps
CPU time 1.27 seconds
Started Mar 24 12:33:01 PM PDT 24
Finished Mar 24 12:33:04 PM PDT 24
Peak memory 192144 kb
Host smart-00adbd2f-37ee-435d-9090-6ad76bdb7bd1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3808159048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3808159048
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.144960310
Short name T869
Test name
Test status
Simulation time 320881467 ps
CPU time 1.37 seconds
Started Mar 24 12:33:03 PM PDT 24
Finished Mar 24 12:33:04 PM PDT 24
Peak memory 192080 kb
Host smart-afae43e2-be8a-4027-95c3-155aad726fb4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144960310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.144960310
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3267254956
Short name T857
Test name
Test status
Simulation time 44152812 ps
CPU time 0.87 seconds
Started Mar 24 12:33:25 PM PDT 24
Finished Mar 24 12:33:26 PM PDT 24
Peak memory 191928 kb
Host smart-2c8bb45b-38f5-4956-9ced-6707333ab409
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3267254956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3267254956
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.131754169
Short name T932
Test name
Test status
Simulation time 609918744 ps
CPU time 1.01 seconds
Started Mar 24 12:33:13 PM PDT 24
Finished Mar 24 12:33:15 PM PDT 24
Peak memory 196904 kb
Host smart-13f68429-4bb4-49c2-a7c3-e99ac814fd9a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131754169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.131754169
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2552410783
Short name T852
Test name
Test status
Simulation time 53842796 ps
CPU time 1.07 seconds
Started Mar 24 12:33:03 PM PDT 24
Finished Mar 24 12:33:04 PM PDT 24
Peak memory 192116 kb
Host smart-772cf2e9-05b5-4cad-a40c-0ae3d6aa2184
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2552410783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2552410783
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3974762737
Short name T907
Test name
Test status
Simulation time 129685070 ps
CPU time 1.35 seconds
Started Mar 24 12:33:22 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 192128 kb
Host smart-119908e7-6b47-41a8-b3c2-860f6f5cf849
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974762737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3974762737
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2978503254
Short name T877
Test name
Test status
Simulation time 204045574 ps
CPU time 1.2 seconds
Started Mar 24 12:33:23 PM PDT 24
Finished Mar 24 12:33:25 PM PDT 24
Peak memory 192124 kb
Host smart-06d70f29-15b4-453e-b1b3-bd87ad18a3e2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2978503254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2978503254
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1331123023
Short name T943
Test name
Test status
Simulation time 439374315 ps
CPU time 1.48 seconds
Started Mar 24 12:33:18 PM PDT 24
Finished Mar 24 12:33:19 PM PDT 24
Peak memory 198408 kb
Host smart-f40cc973-4688-4714-b984-1034b1205161
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331123023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1331123023
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2588362628
Short name T937
Test name
Test status
Simulation time 138560974 ps
CPU time 1.33 seconds
Started Mar 24 12:33:12 PM PDT 24
Finished Mar 24 12:33:15 PM PDT 24
Peak memory 198380 kb
Host smart-38a3cca3-d13e-4329-b87c-6aaefd96a580
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2588362628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2588362628
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2189956997
Short name T892
Test name
Test status
Simulation time 42134289 ps
CPU time 0.85 seconds
Started Mar 24 12:33:15 PM PDT 24
Finished Mar 24 12:33:16 PM PDT 24
Peak memory 191908 kb
Host smart-dd288c00-f737-4dbf-a5c7-118e7dc04d96
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189956997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2189956997
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1793351042
Short name T904
Test name
Test status
Simulation time 44408745 ps
CPU time 0.77 seconds
Started Mar 24 12:33:06 PM PDT 24
Finished Mar 24 12:33:07 PM PDT 24
Peak memory 191928 kb
Host smart-10f55cf0-8d1f-46b6-a1e4-4cd5ae7dca21
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1793351042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1793351042
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2824699890
Short name T905
Test name
Test status
Simulation time 66785427 ps
CPU time 1.14 seconds
Started Mar 24 12:33:16 PM PDT 24
Finished Mar 24 12:33:17 PM PDT 24
Peak memory 197104 kb
Host smart-a65f2818-ea8a-436b-a50c-7e2a28d1dbe9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824699890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2824699890
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.366749040
Short name T948
Test name
Test status
Simulation time 211440186 ps
CPU time 1.29 seconds
Started Mar 24 12:33:08 PM PDT 24
Finished Mar 24 12:33:10 PM PDT 24
Peak memory 192080 kb
Host smart-d4d535a8-884b-448c-bd41-bb6fdec7669e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=366749040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.366749040
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3892089804
Short name T881
Test name
Test status
Simulation time 98164968 ps
CPU time 1.08 seconds
Started Mar 24 12:33:07 PM PDT 24
Finished Mar 24 12:33:10 PM PDT 24
Peak memory 192116 kb
Host smart-45b8a21d-54d4-461e-984e-abbe8d674f3e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892089804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3892089804
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1691534119
Short name T870
Test name
Test status
Simulation time 87893828 ps
CPU time 0.74 seconds
Started Mar 24 12:33:17 PM PDT 24
Finished Mar 24 12:33:18 PM PDT 24
Peak memory 191928 kb
Host smart-fa127764-d472-4e4d-841a-a50fd5c1fd2e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1691534119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1691534119
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1518614714
Short name T859
Test name
Test status
Simulation time 163414012 ps
CPU time 1.37 seconds
Started Mar 24 12:33:12 PM PDT 24
Finished Mar 24 12:33:13 PM PDT 24
Peak memory 192188 kb
Host smart-342113a4-d46f-413d-af3a-cee564bb9165
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518614714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1518614714
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.8620478
Short name T933
Test name
Test status
Simulation time 48724077 ps
CPU time 0.89 seconds
Started Mar 24 12:33:07 PM PDT 24
Finished Mar 24 12:33:08 PM PDT 24
Peak memory 196712 kb
Host smart-595175d6-4b71-43b5-9605-07745dd3a50d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=8620478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.8620478
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2651369950
Short name T915
Test name
Test status
Simulation time 40683234 ps
CPU time 1.14 seconds
Started Mar 24 12:32:55 PM PDT 24
Finished Mar 24 12:32:56 PM PDT 24
Peak memory 198388 kb
Host smart-7b997e6c-34ac-4d7e-9e81-cbd794ca83b6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651369950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2651369950
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2941354592
Short name T901
Test name
Test status
Simulation time 135777097 ps
CPU time 0.85 seconds
Started Mar 24 12:33:06 PM PDT 24
Finished Mar 24 12:33:07 PM PDT 24
Peak memory 191108 kb
Host smart-6b335ef0-a219-4943-92cd-cd9a35add83a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2941354592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2941354592
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4257546406
Short name T858
Test name
Test status
Simulation time 30520983 ps
CPU time 0.8 seconds
Started Mar 24 12:33:16 PM PDT 24
Finished Mar 24 12:33:17 PM PDT 24
Peak memory 191956 kb
Host smart-6cbf17f7-dd3e-4e58-bbd5-a496f6af91e4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257546406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4257546406
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3071500808
Short name T893
Test name
Test status
Simulation time 371488706 ps
CPU time 1.29 seconds
Started Mar 24 12:33:09 PM PDT 24
Finished Mar 24 12:33:10 PM PDT 24
Peak memory 192596 kb
Host smart-ea3e25e0-3f7a-478d-82f4-09874b429c6c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3071500808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3071500808
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3783912677
Short name T873
Test name
Test status
Simulation time 149987027 ps
CPU time 1.28 seconds
Started Mar 24 12:33:03 PM PDT 24
Finished Mar 24 12:33:04 PM PDT 24
Peak memory 192076 kb
Host smart-7fdeb064-66f6-4c8c-8aa3-db1f856ff8cf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783912677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3783912677
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3766636732
Short name T911
Test name
Test status
Simulation time 91968776 ps
CPU time 0.77 seconds
Started Mar 24 12:33:13 PM PDT 24
Finished Mar 24 12:33:14 PM PDT 24
Peak memory 191936 kb
Host smart-8e9bacec-0ed8-4f7f-a45e-b891493061ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3766636732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3766636732
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1358708293
Short name T866
Test name
Test status
Simulation time 66219700 ps
CPU time 1.2 seconds
Started Mar 24 12:33:11 PM PDT 24
Finished Mar 24 12:33:12 PM PDT 24
Peak memory 192064 kb
Host smart-60811567-7e98-486e-b5bb-aac0aaaa8f80
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358708293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1358708293
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.364297178
Short name T871
Test name
Test status
Simulation time 388935565 ps
CPU time 1.29 seconds
Started Mar 24 12:33:04 PM PDT 24
Finished Mar 24 12:33:06 PM PDT 24
Peak memory 198876 kb
Host smart-dff6d2c7-b39f-44e0-bb72-14a3181acda5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=364297178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.364297178
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.312911679
Short name T896
Test name
Test status
Simulation time 178270949 ps
CPU time 1.32 seconds
Started Mar 24 12:33:11 PM PDT 24
Finished Mar 24 12:33:12 PM PDT 24
Peak memory 192096 kb
Host smart-fd6e7ca4-d06c-465f-ae5f-f33152707f5b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312911679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.312911679
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.735548454
Short name T887
Test name
Test status
Simulation time 245646805 ps
CPU time 1.28 seconds
Started Mar 24 12:33:16 PM PDT 24
Finished Mar 24 12:33:17 PM PDT 24
Peak memory 192100 kb
Host smart-1228fcee-f4d7-4cf6-9558-545648f1008b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=735548454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.735548454
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1476097151
Short name T863
Test name
Test status
Simulation time 537409065 ps
CPU time 1.12 seconds
Started Mar 24 12:33:13 PM PDT 24
Finished Mar 24 12:33:14 PM PDT 24
Peak memory 192088 kb
Host smart-51b80a25-232f-482c-b0a3-9c9ec5a38b4f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476097151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1476097151
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1802918747
Short name T945
Test name
Test status
Simulation time 245828506 ps
CPU time 1.08 seconds
Started Mar 24 12:33:05 PM PDT 24
Finished Mar 24 12:33:07 PM PDT 24
Peak memory 192108 kb
Host smart-26c47c39-3584-4385-886e-ae0638b752fb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1802918747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1802918747
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2577387753
Short name T942
Test name
Test status
Simulation time 47255920 ps
CPU time 0.94 seconds
Started Mar 24 12:33:07 PM PDT 24
Finished Mar 24 12:33:10 PM PDT 24
Peak memory 197800 kb
Host smart-61ae6f7f-f7ef-4571-ae81-a98f6ea98423
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577387753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2577387753
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1154775662
Short name T882
Test name
Test status
Simulation time 418404688 ps
CPU time 1.2 seconds
Started Mar 24 12:33:07 PM PDT 24
Finished Mar 24 12:33:10 PM PDT 24
Peak memory 197320 kb
Host smart-075ec8bd-81c1-4cb7-9e73-96c1f4311a9c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1154775662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1154775662
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.130460483
Short name T909
Test name
Test status
Simulation time 82959456 ps
CPU time 1.25 seconds
Started Mar 24 12:33:13 PM PDT 24
Finished Mar 24 12:33:14 PM PDT 24
Peak memory 192124 kb
Host smart-3049f16b-a273-48c2-a00a-a6763146651c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130460483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.130460483
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1071154004
Short name T944
Test name
Test status
Simulation time 322693391 ps
CPU time 1.04 seconds
Started Mar 24 12:33:10 PM PDT 24
Finished Mar 24 12:33:12 PM PDT 24
Peak memory 198356 kb
Host smart-1c850d68-d70f-4410-b550-69a4405a36e0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1071154004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1071154004
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4049713916
Short name T946
Test name
Test status
Simulation time 201004719 ps
CPU time 1.23 seconds
Started Mar 24 12:33:10 PM PDT 24
Finished Mar 24 12:33:12 PM PDT 24
Peak memory 192112 kb
Host smart-f0f0c2e7-22c3-41f9-ad87-e479d549cb43
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049713916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4049713916
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4034789737
Short name T940
Test name
Test status
Simulation time 259782037 ps
CPU time 1.13 seconds
Started Mar 24 12:33:13 PM PDT 24
Finished Mar 24 12:33:14 PM PDT 24
Peak memory 192120 kb
Host smart-7921df87-ce70-4e39-b751-6ba304c1425e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4034789737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.4034789737
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.526491945
Short name T941
Test name
Test status
Simulation time 254116365 ps
CPU time 1.23 seconds
Started Mar 24 12:33:17 PM PDT 24
Finished Mar 24 12:33:19 PM PDT 24
Peak memory 192160 kb
Host smart-c5135e9e-9989-4401-93e5-dd047525f940
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526491945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.526491945
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1010273568
Short name T899
Test name
Test status
Simulation time 38754947 ps
CPU time 1.05 seconds
Started Mar 24 12:33:15 PM PDT 24
Finished Mar 24 12:33:17 PM PDT 24
Peak memory 192004 kb
Host smart-8b0cc275-0c37-4efb-b5b6-8c2aee5d22a6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1010273568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1010273568
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.367547533
Short name T885
Test name
Test status
Simulation time 229759777 ps
CPU time 1.02 seconds
Started Mar 24 12:33:28 PM PDT 24
Finished Mar 24 12:33:29 PM PDT 24
Peak memory 192144 kb
Host smart-bcedc295-8afc-445b-a030-2f3096828a77
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367547533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.367547533
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.4189760723
Short name T862
Test name
Test status
Simulation time 287610178 ps
CPU time 1.41 seconds
Started Mar 24 12:33:44 PM PDT 24
Finished Mar 24 12:33:46 PM PDT 24
Peak memory 192116 kb
Host smart-d6b11d41-d04b-4d1b-be70-85205b6e3863
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4189760723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.4189760723
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.988579385
Short name T888
Test name
Test status
Simulation time 229852367 ps
CPU time 0.89 seconds
Started Mar 24 12:33:10 PM PDT 24
Finished Mar 24 12:33:11 PM PDT 24
Peak memory 196632 kb
Host smart-d9fb69af-e82b-4413-bc89-28fe135f4fb3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988579385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.988579385
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3596225567
Short name T921
Test name
Test status
Simulation time 57733095 ps
CPU time 1.15 seconds
Started Mar 24 12:33:35 PM PDT 24
Finished Mar 24 12:33:36 PM PDT 24
Peak memory 192076 kb
Host smart-e48f5332-3cc6-4827-a676-370e67496562
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3596225567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3596225567
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2415799936
Short name T929
Test name
Test status
Simulation time 146389677 ps
CPU time 1.3 seconds
Started Mar 24 12:33:10 PM PDT 24
Finished Mar 24 12:33:11 PM PDT 24
Peak memory 198456 kb
Host smart-7023121d-eeba-4572-91f8-736460191390
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415799936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2415799936
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1996630465
Short name T900
Test name
Test status
Simulation time 37015907 ps
CPU time 1.02 seconds
Started Mar 24 12:33:13 PM PDT 24
Finished Mar 24 12:33:15 PM PDT 24
Peak memory 196940 kb
Host smart-9712f5c3-0e71-4794-a1a5-37f635ce8375
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1996630465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1996630465
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3560983879
Short name T931
Test name
Test status
Simulation time 37503951 ps
CPU time 1.07 seconds
Started Mar 24 12:33:23 PM PDT 24
Finished Mar 24 12:33:25 PM PDT 24
Peak memory 196740 kb
Host smart-1782d463-d6d1-4ed5-a72e-fcdf7335a984
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560983879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3560983879
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1054623337
Short name T851
Test name
Test status
Simulation time 71495538 ps
CPU time 1.09 seconds
Started Mar 24 12:33:20 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 192096 kb
Host smart-adc7d0b7-71c9-4181-8eeb-f62627194723
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1054623337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1054623337
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1056747786
Short name T913
Test name
Test status
Simulation time 132196129 ps
CPU time 1.13 seconds
Started Mar 24 12:33:20 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 192020 kb
Host smart-3573d8d4-be3d-4701-b98c-8da08eaec4e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056747786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1056747786
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2699940793
Short name T934
Test name
Test status
Simulation time 58435186 ps
CPU time 0.68 seconds
Started Mar 24 12:33:07 PM PDT 24
Finished Mar 24 12:33:10 PM PDT 24
Peak memory 195432 kb
Host smart-7afcaff0-b1a1-4bc8-9a9a-cda0bdbf80ce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2699940793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2699940793
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2069432124
Short name T925
Test name
Test status
Simulation time 159458390 ps
CPU time 1 seconds
Started Mar 24 12:33:10 PM PDT 24
Finished Mar 24 12:33:12 PM PDT 24
Peak memory 192152 kb
Host smart-c45da024-d3b8-4a2f-93c7-e6a1880f465f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069432124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2069432124
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.568264697
Short name T938
Test name
Test status
Simulation time 212979361 ps
CPU time 1.15 seconds
Started Mar 24 12:33:14 PM PDT 24
Finished Mar 24 12:33:15 PM PDT 24
Peak memory 192080 kb
Host smart-d0b3ac81-2819-4476-87c6-1a148086245e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=568264697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.568264697
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2164464652
Short name T935
Test name
Test status
Simulation time 208397886 ps
CPU time 1.24 seconds
Started Mar 24 12:33:10 PM PDT 24
Finished Mar 24 12:33:11 PM PDT 24
Peak memory 198396 kb
Host smart-f4a2aaab-2eff-4e30-b309-b8b0daab89f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164464652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2164464652
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4063232331
Short name T876
Test name
Test status
Simulation time 197691412 ps
CPU time 0.89 seconds
Started Mar 24 12:33:20 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 191896 kb
Host smart-1bf215b4-1c30-4ec4-81c1-a9d48498e300
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4063232331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.4063232331
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3807480693
Short name T939
Test name
Test status
Simulation time 293946144 ps
CPU time 1.08 seconds
Started Mar 24 12:33:28 PM PDT 24
Finished Mar 24 12:33:30 PM PDT 24
Peak memory 196804 kb
Host smart-e648edd7-7f1f-4430-bc94-45a0026a0a00
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807480693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3807480693
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1247346138
Short name T886
Test name
Test status
Simulation time 109009934 ps
CPU time 0.94 seconds
Started Mar 24 12:33:27 PM PDT 24
Finished Mar 24 12:33:29 PM PDT 24
Peak memory 192144 kb
Host smart-6d844773-95f9-4ba3-92e4-71c55913e795
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1247346138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1247346138
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3336005704
Short name T894
Test name
Test status
Simulation time 132199455 ps
CPU time 0.91 seconds
Started Mar 24 12:33:15 PM PDT 24
Finished Mar 24 12:33:16 PM PDT 24
Peak memory 191936 kb
Host smart-78ee35b2-d24f-4b6b-b7fb-3ff495abd904
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336005704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3336005704
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.4204814889
Short name T947
Test name
Test status
Simulation time 248735884 ps
CPU time 1.3 seconds
Started Mar 24 12:33:15 PM PDT 24
Finished Mar 24 12:33:17 PM PDT 24
Peak memory 198440 kb
Host smart-7e82c6f0-96a5-4d6c-b617-720d9c6e6366
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4204814889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.4204814889
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3122697890
Short name T855
Test name
Test status
Simulation time 86539112 ps
CPU time 1.32 seconds
Started Mar 24 12:33:23 PM PDT 24
Finished Mar 24 12:33:25 PM PDT 24
Peak memory 192116 kb
Host smart-c28037a6-20d7-47b7-80a0-579a2d8b20a8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122697890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3122697890
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1695702372
Short name T917
Test name
Test status
Simulation time 206334671 ps
CPU time 1.31 seconds
Started Mar 24 12:33:22 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 198460 kb
Host smart-56d76d48-fe77-4959-97d5-cfb92c539da0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1695702372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1695702372
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3367453527
Short name T920
Test name
Test status
Simulation time 401019850 ps
CPU time 1.45 seconds
Started Mar 24 12:33:17 PM PDT 24
Finished Mar 24 12:33:19 PM PDT 24
Peak memory 192128 kb
Host smart-3c645a20-1098-436b-a230-2b8591b6c069
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367453527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3367453527
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.872896548
Short name T922
Test name
Test status
Simulation time 114082837 ps
CPU time 1.03 seconds
Started Mar 24 12:33:27 PM PDT 24
Finished Mar 24 12:33:29 PM PDT 24
Peak memory 192096 kb
Host smart-4a0d681e-f4b5-4f19-98e4-c1a6c55049b9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=872896548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.872896548
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4156597814
Short name T908
Test name
Test status
Simulation time 91179510 ps
CPU time 1.25 seconds
Started Mar 24 12:33:11 PM PDT 24
Finished Mar 24 12:33:12 PM PDT 24
Peak memory 198388 kb
Host smart-2779e8e0-7b1a-4eec-9399-b3ffa5354332
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156597814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4156597814
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2830629982
Short name T874
Test name
Test status
Simulation time 69049100 ps
CPU time 1.35 seconds
Started Mar 24 12:33:11 PM PDT 24
Finished Mar 24 12:33:13 PM PDT 24
Peak memory 192124 kb
Host smart-c08c4679-6057-4fd3-acbe-140e7747d8b9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2830629982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2830629982
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3404168692
Short name T880
Test name
Test status
Simulation time 138452022 ps
CPU time 1.27 seconds
Started Mar 24 12:33:06 PM PDT 24
Finished Mar 24 12:33:08 PM PDT 24
Peak memory 198408 kb
Host smart-5260e631-1bd1-4f1d-9f9f-e789c965caa1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404168692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3404168692
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3297113206
Short name T919
Test name
Test status
Simulation time 342323339 ps
CPU time 1.02 seconds
Started Mar 24 12:33:21 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 192068 kb
Host smart-cc2a2798-7c1e-4cc1-bc55-d297754f8558
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3297113206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3297113206
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3714096915
Short name T860
Test name
Test status
Simulation time 68065902 ps
CPU time 1.26 seconds
Started Mar 24 12:33:19 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 196876 kb
Host smart-90cdccab-e6e8-4e0f-a2de-26dbe6ea78af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714096915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3714096915
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2385087465
Short name T898
Test name
Test status
Simulation time 217104480 ps
CPU time 1.11 seconds
Started Mar 24 12:33:08 PM PDT 24
Finished Mar 24 12:33:10 PM PDT 24
Peak memory 192064 kb
Host smart-66257ec1-031b-4ec7-ae57-4bcc15de2ec8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2385087465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2385087465
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3659620410
Short name T895
Test name
Test status
Simulation time 422528596 ps
CPU time 1.45 seconds
Started Mar 24 12:33:13 PM PDT 24
Finished Mar 24 12:33:14 PM PDT 24
Peak memory 192116 kb
Host smart-704877a9-10b8-46d4-9a4b-946d0f8e44bb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659620410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3659620410
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3586087562
Short name T875
Test name
Test status
Simulation time 92754369 ps
CPU time 0.87 seconds
Started Mar 24 12:33:19 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 192004 kb
Host smart-6b457af8-b0e4-49a8-97e9-191433977f66
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3586087562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3586087562
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1229665412
Short name T918
Test name
Test status
Simulation time 101406919 ps
CPU time 0.81 seconds
Started Mar 24 12:33:24 PM PDT 24
Finished Mar 24 12:33:26 PM PDT 24
Peak memory 191908 kb
Host smart-fbf11297-459f-499c-a538-889951f8b305
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229665412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1229665412
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1708704148
Short name T890
Test name
Test status
Simulation time 20930327 ps
CPU time 0.75 seconds
Started Mar 24 12:33:21 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 196544 kb
Host smart-a1f0f84a-d1ae-4832-aa69-0cec981fee70
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1708704148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1708704148
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4152168661
Short name T914
Test name
Test status
Simulation time 127993492 ps
CPU time 0.98 seconds
Started Mar 24 12:33:28 PM PDT 24
Finished Mar 24 12:33:29 PM PDT 24
Peak memory 191956 kb
Host smart-b14fa889-3fa7-4907-b007-045bfbea304a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152168661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4152168661
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.784875310
Short name T902
Test name
Test status
Simulation time 205311785 ps
CPU time 1.09 seconds
Started Mar 24 12:33:12 PM PDT 24
Finished Mar 24 12:33:15 PM PDT 24
Peak memory 192092 kb
Host smart-8328a2ed-6e93-460a-ba77-ea6d2d226891
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=784875310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.784875310
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4268283552
Short name T854
Test name
Test status
Simulation time 66375517 ps
CPU time 1.02 seconds
Started Mar 24 12:33:33 PM PDT 24
Finished Mar 24 12:33:34 PM PDT 24
Peak memory 192136 kb
Host smart-439f2a56-f40d-4dcb-b6ab-720de5bc65d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268283552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4268283552
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4210694688
Short name T930
Test name
Test status
Simulation time 99029838 ps
CPU time 0.98 seconds
Started Mar 24 12:33:19 PM PDT 24
Finished Mar 24 12:33:22 PM PDT 24
Peak memory 192116 kb
Host smart-67dbd167-e490-4246-acff-f0c64007f2aa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4210694688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.4210694688
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3066720166
Short name T906
Test name
Test status
Simulation time 66034368 ps
CPU time 1.21 seconds
Started Mar 24 12:33:07 PM PDT 24
Finished Mar 24 12:33:08 PM PDT 24
Peak memory 198428 kb
Host smart-e85a7b51-e532-4cc6-97bc-72c1ada0ecae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066720166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3066720166
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1116445512
Short name T926
Test name
Test status
Simulation time 67205490 ps
CPU time 1.07 seconds
Started Mar 24 12:33:23 PM PDT 24
Finished Mar 24 12:33:25 PM PDT 24
Peak memory 192136 kb
Host smart-ad716941-e389-4605-b644-6a5d39290fc7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1116445512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1116445512
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1025031079
Short name T912
Test name
Test status
Simulation time 306249015 ps
CPU time 1.14 seconds
Started Mar 24 12:33:21 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 197028 kb
Host smart-39e10298-b096-496b-966f-5cfcb6f090b9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025031079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1025031079
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3278100571
Short name T889
Test name
Test status
Simulation time 56538346 ps
CPU time 1.07 seconds
Started Mar 24 12:33:11 PM PDT 24
Finished Mar 24 12:33:12 PM PDT 24
Peak memory 192120 kb
Host smart-d3bd45eb-5edf-4970-8f3a-12f60b716561
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3278100571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3278100571
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.150026765
Short name T878
Test name
Test status
Simulation time 141231938 ps
CPU time 1.36 seconds
Started Mar 24 12:33:31 PM PDT 24
Finished Mar 24 12:33:37 PM PDT 24
Peak memory 192164 kb
Host smart-7177e684-0dca-4d14-856f-8306bb878664
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150026765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.150026765
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.533292107
Short name T903
Test name
Test status
Simulation time 58635394 ps
CPU time 0.83 seconds
Started Mar 24 12:33:16 PM PDT 24
Finished Mar 24 12:33:17 PM PDT 24
Peak memory 191924 kb
Host smart-b158391d-b896-4d1d-a736-c6252fd221b9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=533292107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.533292107
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.719457167
Short name T865
Test name
Test status
Simulation time 181989705 ps
CPU time 1.19 seconds
Started Mar 24 12:33:35 PM PDT 24
Finished Mar 24 12:33:37 PM PDT 24
Peak memory 192088 kb
Host smart-40703195-d177-45d2-a50a-282bc7919b2f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719457167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.719457167
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4246211703
Short name T910
Test name
Test status
Simulation time 41757478 ps
CPU time 0.8 seconds
Started Mar 24 12:33:06 PM PDT 24
Finished Mar 24 12:33:07 PM PDT 24
Peak memory 191888 kb
Host smart-8989adb0-8a66-459a-a3df-cc08689935f2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4246211703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.4246211703
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1808697766
Short name T891
Test name
Test status
Simulation time 36823452 ps
CPU time 1.12 seconds
Started Mar 24 12:33:06 PM PDT 24
Finished Mar 24 12:33:07 PM PDT 24
Peak memory 192120 kb
Host smart-39def8ba-b058-46de-9023-2e3f0a8e6463
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808697766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1808697766
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1343134199
Short name T850
Test name
Test status
Simulation time 624801243 ps
CPU time 0.99 seconds
Started Mar 24 12:33:13 PM PDT 24
Finished Mar 24 12:33:15 PM PDT 24
Peak memory 192088 kb
Host smart-c25a5b3f-43b4-448c-aa03-b2a736733de2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1343134199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1343134199
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4054507603
Short name T928
Test name
Test status
Simulation time 324032084 ps
CPU time 1.4 seconds
Started Mar 24 12:33:07 PM PDT 24
Finished Mar 24 12:33:08 PM PDT 24
Peak memory 198472 kb
Host smart-da4a5904-ec1f-4d5a-b9a0-327f4f631f17
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054507603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4054507603
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2365363889
Short name T872
Test name
Test status
Simulation time 48472944 ps
CPU time 1.29 seconds
Started Mar 24 12:33:00 PM PDT 24
Finished Mar 24 12:33:03 PM PDT 24
Peak memory 198452 kb
Host smart-6bfe4ba3-de2d-4657-9692-f9097245c9a1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2365363889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2365363889
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2607642386
Short name T924
Test name
Test status
Simulation time 46273507 ps
CPU time 0.92 seconds
Started Mar 24 12:32:59 PM PDT 24
Finished Mar 24 12:33:01 PM PDT 24
Peak memory 197496 kb
Host smart-8826b85f-248a-41f3-80b8-799ead894c0f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607642386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2607642386
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2952763117
Short name T868
Test name
Test status
Simulation time 23709343 ps
CPU time 0.84 seconds
Started Mar 24 12:33:07 PM PDT 24
Finished Mar 24 12:33:10 PM PDT 24
Peak memory 197720 kb
Host smart-e9f4fcc6-ae85-43af-bf7b-1473dc305576
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2952763117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2952763117
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.353357485
Short name T916
Test name
Test status
Simulation time 46127987 ps
CPU time 0.76 seconds
Started Mar 24 12:33:08 PM PDT 24
Finished Mar 24 12:33:10 PM PDT 24
Peak memory 196532 kb
Host smart-45d075e9-f4d6-4363-b870-844df52da9d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353357485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.353357485
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1140413762
Short name T884
Test name
Test status
Simulation time 45893580 ps
CPU time 0.78 seconds
Started Mar 24 12:33:11 PM PDT 24
Finished Mar 24 12:33:12 PM PDT 24
Peak memory 191916 kb
Host smart-296fb78d-986a-438b-b1d6-11f3e371b4a0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1140413762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1140413762
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1435395091
Short name T853
Test name
Test status
Simulation time 64596638 ps
CPU time 0.86 seconds
Started Mar 24 12:33:04 PM PDT 24
Finished Mar 24 12:33:05 PM PDT 24
Peak memory 191860 kb
Host smart-d3f25777-5551-48b3-b8d3-7894b23172d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435395091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1435395091
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1707304384
Short name T897
Test name
Test status
Simulation time 215900721 ps
CPU time 1.17 seconds
Started Mar 24 12:33:19 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 192080 kb
Host smart-e2b2e487-e6bd-4b26-9046-7be54627a917
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1707304384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1707304384
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4139480366
Short name T936
Test name
Test status
Simulation time 100185235 ps
CPU time 0.98 seconds
Started Mar 24 12:33:20 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 192056 kb
Host smart-59799c29-6ab8-491e-a7fd-19d4100262ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139480366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4139480366
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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