Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4310429	1			T22	1		T23	1		T24	33895
all_pins[1]	4310429	1			T22	1		T23	1		T24	33895
all_pins[2]	4310429	1			T22	1		T23	1		T24	33895
all_pins[3]	4310429	1			T22	1		T23	1		T24	33895
all_pins[4]	4310429	1			T22	1		T23	1		T24	33895
all_pins[5]	4310429	1			T22	1		T23	1		T24	33895
all_pins[6]	4310429	1			T22	1		T23	1		T24	33895
all_pins[7]	4310429	1			T22	1		T23	1		T24	33895
all_pins[8]	4310429	1			T22	1		T23	1		T24	33895
all_pins[9]	4310429	1			T22	1		T23	1		T24	33895
all_pins[10]	4310429	1			T22	1		T23	1		T24	33895
all_pins[11]	4310429	1			T22	1		T23	1		T24	33895
all_pins[12]	4310429	1			T22	1		T23	1		T24	33895
all_pins[13]	4310429	1			T22	1		T23	1		T24	33895
all_pins[14]	4310429	1			T22	1		T23	1		T24	33895
all_pins[15]	4310429	1			T22	1		T23	1		T24	33895
all_pins[16]	4310429	1			T22	1		T23	1		T24	33895
all_pins[17]	4310429	1			T22	1		T23	1		T24	33895
all_pins[18]	4310429	1			T22	1		T23	1		T24	33895
all_pins[19]	4310429	1			T22	1		T23	1		T24	33895
all_pins[20]	4310429	1			T22	1		T23	1		T24	33895
all_pins[21]	4310429	1			T22	1		T23	1		T24	33895
all_pins[22]	4310429	1			T22	1		T23	1		T24	33895
all_pins[23]	4310429	1			T22	1		T23	1		T24	33895
all_pins[24]	4310429	1			T22	1		T23	1		T24	33895
all_pins[25]	4310429	1			T22	1		T23	1		T24	33895
all_pins[26]	4310429	1			T22	1		T23	1		T24	33895
all_pins[27]	4310429	1			T22	1		T23	1		T24	33895
all_pins[28]	4310429	1			T22	1		T23	1		T24	33895
all_pins[29]	4310429	1			T22	1		T23	1		T24	33895
all_pins[30]	4310429	1			T22	1		T23	1		T24	33895
all_pins[31]	4310429	1			T22	1		T23	1		T24	33895

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	85667058	1			T22	32		T23	32		T24	673709
values[0x1]	52266670	1			T24	410931		T26	1458		T27	102
transitions[0x0=>0x1]	31312094	1			T24	245771		T26	917		T27	79
transitions[0x1=>0x0]	31311941	1			T24	245771		T26	916		T27	79

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2679248	1			T22	1		T23	1		T24	20998
all_pins[0]	values[0x1]	1631181	1			T24	12897		T26	44		T27	8
all_pins[0]	transitions[0x0=>0x1]	1009057	1			T24	8059		T26	23		T27	6
all_pins[0]	transitions[0x1=>0x0]	1008971	1			T24	7814		T26	51		T29	64917
all_pins[1]	values[0x0]	2675768	1			T22	1		T23	1		T24	21000
all_pins[1]	values[0x1]	1634661	1			T24	12895		T26	48		T29	104530
all_pins[1]	transitions[0x0=>0x1]	981027	1			T24	7703		T26	26		T29	63381
all_pins[1]	transitions[0x1=>0x0]	977547	1			T24	7705		T26	22		T27	8
all_pins[2]	values[0x0]	2677207	1			T22	1		T23	1		T24	20850
all_pins[2]	values[0x1]	1633222	1			T24	13045		T26	31		T29	103586
all_pins[2]	transitions[0x0=>0x1]	976350	1			T24	7803		T26	15		T29	61227
all_pins[2]	transitions[0x1=>0x0]	977789	1			T24	7653		T26	32		T29	62171
all_pins[3]	values[0x0]	2685264	1			T22	1		T23	1		T24	20802
all_pins[3]	values[0x1]	1625165	1			T24	13093		T26	30		T29	103176
all_pins[3]	transitions[0x0=>0x1]	970992	1			T24	7769		T26	22		T29	61701
all_pins[3]	transitions[0x1=>0x0]	979049	1			T24	7721		T26	23		T29	62111
all_pins[4]	values[0x0]	2680650	1			T22	1		T23	1		T24	20856
all_pins[4]	values[0x1]	1629779	1			T24	13039		T26	42		T29	102867
all_pins[4]	transitions[0x0=>0x1]	978473	1			T24	7535		T26	23		T29	61703
all_pins[4]	transitions[0x1=>0x0]	973859	1			T24	7589		T26	11		T29	62012
all_pins[5]	values[0x0]	2679055	1			T22	1		T23	1		T24	20963
all_pins[5]	values[0x1]	1631374	1			T24	12932		T26	60		T27	4
all_pins[5]	transitions[0x0=>0x1]	979047	1			T24	7570		T26	47		T27	4
all_pins[5]	transitions[0x1=>0x0]	977452	1			T24	7677		T26	29		T29	60502
all_pins[6]	values[0x0]	2681325	1			T22	1		T23	1		T24	20649
all_pins[6]	values[0x1]	1629104	1			T24	13246		T26	20		T27	10
all_pins[6]	transitions[0x0=>0x1]	974743	1			T24	7989		T26	9		T27	6
all_pins[6]	transitions[0x1=>0x0]	977013	1			T24	7675		T26	49		T29	62082
all_pins[7]	values[0x0]	2676119	1			T22	1		T23	1		T24	21127
all_pins[7]	values[0x1]	1634310	1			T24	12768		T26	83		T27	5
all_pins[7]	transitions[0x0=>0x1]	977325	1			T24	7517		T26	67		T29	61350
all_pins[7]	transitions[0x1=>0x0]	972119	1			T24	7995		T26	4		T27	5
all_pins[8]	values[0x0]	2674174	1			T22	1		T23	1		T24	20521
all_pins[8]	values[0x1]	1636255	1			T24	13374		T26	52		T29	101831
all_pins[8]	transitions[0x0=>0x1]	976843	1			T24	8093		T26	14		T29	60504
all_pins[8]	transitions[0x1=>0x0]	974898	1			T24	7487		T26	45		T27	5
all_pins[9]	values[0x0]	2675622	1			T22	1		T23	1		T24	20979
all_pins[9]	values[0x1]	1634807	1			T24	12916		T26	40		T27	10
all_pins[9]	transitions[0x0=>0x1]	979827	1			T24	7264		T26	16		T27	10
all_pins[9]	transitions[0x1=>0x0]	981275	1			T24	7722		T26	28		T29	61284
all_pins[10]	values[0x0]	2675444	1			T22	1		T23	1		T24	21175
all_pins[10]	values[0x1]	1634985	1			T24	12720		T26	51		T27	1
all_pins[10]	transitions[0x0=>0x1]	980032	1			T24	7447		T26	38		T29	61854
all_pins[10]	transitions[0x1=>0x0]	979854	1			T24	7643		T26	27		T27	9
all_pins[11]	values[0x0]	2675721	1			T22	1		T23	1		T24	20987
all_pins[11]	values[0x1]	1634708	1			T24	12908		T26	45		T27	2
all_pins[11]	transitions[0x0=>0x1]	975422	1			T24	7609		T26	26		T27	1
all_pins[11]	transitions[0x1=>0x0]	975699	1			T24	7421		T26	32		T29	60714
all_pins[12]	values[0x0]	2672683	1			T22	1		T23	1		T24	21032
all_pins[12]	values[0x1]	1637746	1			T24	12863		T26	20		T29	102778
all_pins[12]	transitions[0x0=>0x1]	979882	1			T24	7752		T26	9		T29	60716
all_pins[12]	transitions[0x1=>0x0]	976844	1			T24	7797		T26	34		T27	2
all_pins[13]	values[0x0]	2674409	1			T22	1		T23	1		T24	21324
all_pins[13]	values[0x1]	1636020	1			T24	12571		T26	59		T27	6
all_pins[13]	transitions[0x0=>0x1]	978329	1			T24	7419		T26	50		T27	6
all_pins[13]	transitions[0x1=>0x0]	980055	1			T24	7711		T26	11		T29	60897
all_pins[14]	values[0x0]	2679389	1			T22	1		T23	1		T24	21465
all_pins[14]	values[0x1]	1631040	1			T24	12430		T26	62		T27	6
all_pins[14]	transitions[0x0=>0x1]	975123	1			T24	7615		T26	30		T27	4
all_pins[14]	transitions[0x1=>0x0]	980103	1			T24	7756		T26	27		T27	4
all_pins[15]	values[0x0]	2678326	1			T22	1		T23	1		T24	21423
all_pins[15]	values[0x1]	1632103	1			T24	12472		T26	62		T27	6
all_pins[15]	transitions[0x0=>0x1]	977761	1			T24	7556		T26	37		T27	4
all_pins[15]	transitions[0x1=>0x0]	976698	1			T24	7514		T26	37		T27	4
all_pins[16]	values[0x0]	2675380	1			T22	1		T23	1		T24	21140
all_pins[16]	values[0x1]	1635049	1			T24	12755		T26	56		T29	102822
all_pins[16]	transitions[0x0=>0x1]	980355	1			T24	7860		T26	25		T29	62124
all_pins[16]	transitions[0x1=>0x0]	977409	1			T24	7577		T26	31		T27	6
all_pins[17]	values[0x0]	2680789	1			T22	1		T23	1		T24	21244
all_pins[17]	values[0x1]	1629640	1			T24	12651		T26	41		T27	2
all_pins[17]	transitions[0x0=>0x1]	976179	1			T24	7585		T26	22		T27	2
all_pins[17]	transitions[0x1=>0x0]	981588	1			T24	7689		T26	37		T29	62676
all_pins[18]	values[0x0]	2672923	1			T22	1		T23	1		T24	20972
all_pins[18]	values[0x1]	1637506	1			T24	12923		T26	49		T27	2
all_pins[18]	transitions[0x0=>0x1]	981806	1			T24	7774		T26	36		T29	61981
all_pins[18]	transitions[0x1=>0x0]	973940	1			T24	7502		T26	28		T29	60632
all_pins[19]	values[0x0]	2677598	1			T22	1		T23	1		T24	20669
all_pins[19]	values[0x1]	1632831	1			T24	13226		T26	32		T29	103485
all_pins[19]	transitions[0x0=>0x1]	974808	1			T24	7891		T26	22		T29	62168
all_pins[19]	transitions[0x1=>0x0]	979483	1			T24	7588		T26	39		T27	2
all_pins[20]	values[0x0]	2679419	1			T22	1		T23	1		T24	21127
all_pins[20]	values[0x1]	1631010	1			T24	12768		T26	39		T27	8
all_pins[20]	transitions[0x0=>0x1]	975861	1			T24	7507		T26	27		T27	8
all_pins[20]	transitions[0x1=>0x0]	977682	1			T24	7965		T26	20		T29	62189
all_pins[21]	values[0x0]	2674840	1			T22	1		T23	1		T24	21470
all_pins[21]	values[0x1]	1635589	1			T24	12425		T26	34		T27	6
all_pins[21]	transitions[0x0=>0x1]	979851	1			T24	7442		T26	14		T27	2
all_pins[21]	transitions[0x1=>0x0]	975272	1			T24	7785		T26	19		T27	4
all_pins[22]	values[0x0]	2681633	1			T22	1		T23	1		T24	21049
all_pins[22]	values[0x1]	1628796	1			T24	12846		T26	38		T29	101319
all_pins[22]	transitions[0x0=>0x1]	972218	1			T24	7900		T26	24		T29	60634
all_pins[22]	transitions[0x1=>0x0]	979011	1			T24	7479		T26	20		T27	6
all_pins[23]	values[0x0]	2677214	1			T22	1		T23	1		T24	21350
all_pins[23]	values[0x1]	1633215	1			T24	12545		T26	48		T29	104066
all_pins[23]	transitions[0x0=>0x1]	978303	1			T24	7461		T26	34		T29	63086
all_pins[23]	transitions[0x1=>0x0]	973884	1			T24	7762		T26	24		T29	60339
all_pins[24]	values[0x0]	2674798	1			T22	1		T23	1		T24	21050
all_pins[24]	values[0x1]	1635631	1			T24	12845		T26	63		T29	102121
all_pins[24]	transitions[0x0=>0x1]	980180	1			T24	7856		T26	46		T29	60728
all_pins[24]	transitions[0x1=>0x0]	977764	1			T24	7556		T26	31		T29	62673
all_pins[25]	values[0x0]	2677649	1			T22	1		T23	1		T24	20902
all_pins[25]	values[0x1]	1632780	1			T24	12993		T26	52		T27	11
all_pins[25]	transitions[0x0=>0x1]	976568	1			T24	7805		T26	28		T27	11
all_pins[25]	transitions[0x1=>0x0]	979419	1			T24	7657		T26	39		T29	61374
all_pins[26]	values[0x0]	2672156	1			T22	1		T23	1		T24	21027
all_pins[26]	values[0x1]	1638273	1			T24	12868		T26	25		T27	1
all_pins[26]	transitions[0x0=>0x1]	981756	1			T24	7725		T26	11		T27	1
all_pins[26]	transitions[0x1=>0x0]	976263	1			T24	7850		T26	38		T27	11
all_pins[27]	values[0x0]	2673770	1			T22	1		T23	1		T24	21197
all_pins[27]	values[0x1]	1636659	1			T24	12698		T26	49		T27	7
all_pins[27]	transitions[0x0=>0x1]	977232	1			T24	7481		T26	42		T27	7
all_pins[27]	transitions[0x1=>0x0]	978846	1			T24	7651		T26	18		T27	1
all_pins[28]	values[0x0]	2680668	1			T22	1		T23	1		T24	20595
all_pins[28]	values[0x1]	1629761	1			T24	13300		T26	43		T27	2
all_pins[28]	transitions[0x0=>0x1]	974470	1			T24	7999		T26	33		T27	2
all_pins[28]	transitions[0x1=>0x0]	981368	1			T24	7397		T26	39		T27	7
all_pins[29]	values[0x0]	2675138	1			T22	1		T23	1		T24	21096
all_pins[29]	values[0x1]	1635291	1			T24	12799		T26	39		T29	101700
all_pins[29]	transitions[0x0=>0x1]	979943	1			T24	7566		T26	28		T29	61328
all_pins[29]	transitions[0x1=>0x0]	974413	1			T24	8067		T26	32		T27	2
all_pins[30]	values[0x0]	2673498	1			T22	1		T23	1		T24	21427
all_pins[30]	values[0x1]	1636931	1			T24	12468		T26	28		T27	3
all_pins[30]	transitions[0x0=>0x1]	977046	1			T24	7436		T26	22		T27	3
all_pins[30]	transitions[0x1=>0x0]	975406	1			T24	7767		T26	33		T29	60588
all_pins[31]	values[0x0]	2679181	1			T22	1		T23	1		T24	21243
all_pins[31]	values[0x1]	1631248	1			T24	12652		T26	73		T27	2
all_pins[31]	transitions[0x0=>0x1]	975285	1			T24	7783		T26	51		T27	2
all_pins[31]	transitions[0x1=>0x0]	980968	1			T24	7599		T26	6		T27	3