Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14549564	1			T22	1		T23	278		T24	109950
all_values[1]	14549564	1			T22	1		T23	278		T24	109950
all_values[2]	14549564	1			T22	1		T23	278		T24	109950
all_values[3]	14549564	1			T22	1		T23	278		T24	109950
all_values[4]	14549564	1			T22	1		T23	278		T24	109950
all_values[5]	14549564	1			T22	1		T23	278		T24	109950
all_values[6]	14549564	1			T22	1		T23	278		T24	109950
all_values[7]	14549564	1			T22	1		T23	278		T24	109950
all_values[8]	14549564	1			T22	1		T23	278		T24	109950
all_values[9]	14549564	1			T22	1		T23	278		T24	109950
all_values[10]	14549564	1			T22	1		T23	278		T24	109950
all_values[11]	14549564	1			T22	1		T23	278		T24	109950
all_values[12]	14549564	1			T22	1		T23	278		T24	109950
all_values[13]	14549564	1			T22	1		T23	278		T24	109950
all_values[14]	14549564	1			T22	1		T23	278		T24	109950
all_values[15]	14549564	1			T22	1		T23	278		T24	109950
all_values[16]	14549564	1			T22	1		T23	278		T24	109950
all_values[17]	14549564	1			T22	1		T23	278		T24	109950
all_values[18]	14549564	1			T22	1		T23	278		T24	109950
all_values[19]	14549564	1			T22	1		T23	278		T24	109950
all_values[20]	14549564	1			T22	1		T23	278		T24	109950
all_values[21]	14549564	1			T22	1		T23	278		T24	109950
all_values[22]	14549564	1			T22	1		T23	278		T24	109950
all_values[23]	14549564	1			T22	1		T23	278		T24	109950
all_values[24]	14549564	1			T22	1		T23	278		T24	109950
all_values[25]	14549564	1			T22	1		T23	278		T24	109950
all_values[26]	14549564	1			T22	1		T23	278		T24	109950
all_values[27]	14549564	1			T22	1		T23	278		T24	109950
all_values[28]	14549564	1			T22	1		T23	278		T24	109950
all_values[29]	14549564	1			T22	1		T23	278		T24	109950
all_values[30]	14549564	1			T22	1		T23	278		T24	109950
all_values[31]	14549564	1			T22	1		T23	278		T24	109950

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

270669804

1

T22

32

T23

8896

T24

200259

auto[1]

194916244

1

T24

151580

T26

3558

T27

228

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112647096

1

T22

32

T23

8896

T24

783500

auto[1]

352938952

1

T24

273490

T26

6598

T27

352

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

460676642

1

T22

32

T23

8896

T24

347316

auto[1]

4909406

1

T24

45239

T27

42

T29

287602

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2935769	1			T22	1		T23	278		T24	19763
all_values[0]	auto[0]	auto[0]	auto[1]	5471648	1			T24	41929		T26	78		T27	2
all_values[0]	auto[0]	auto[1]	auto[0]	594652	1			T24	4453		T26	31		T27	3
all_values[0]	auto[0]	auto[1]	auto[1]	5394021	1			T24	42422		T26	113		T27	8
all_values[0]	auto[1]	auto[0]	auto[1]	77021	1			T24	733		T29	4520		T1	30
all_values[0]	auto[1]	auto[1]	auto[1]	76453	1			T24	650		T27	2		T29	4621
all_values[1]	auto[0]	auto[0]	auto[0]	2929378	1			T22	1		T23	278		T24	19941
all_values[1]	auto[0]	auto[0]	auto[1]	5456822	1			T24	40761		T26	129		T27	10
all_values[1]	auto[0]	auto[1]	auto[0]	591634	1			T24	4896		T26	16		T27	3
all_values[1]	auto[0]	auto[1]	auto[1]	5418568	1			T24	42928		T26	93		T29	347228
all_values[1]	auto[1]	auto[0]	auto[1]	76549	1			T24	729		T27	2		T29	4444
all_values[1]	auto[1]	auto[1]	auto[1]	76613	1			T24	695		T29	4572		T1	45
all_values[2]	auto[0]	auto[0]	auto[0]	2929346	1			T22	1		T23	278		T24	19589
all_values[2]	auto[0]	auto[0]	auto[1]	5467518	1			T24	42184		T26	116		T27	2
all_values[2]	auto[0]	auto[1]	auto[0]	589763	1			T24	4643		T26	7		T27	13
all_values[2]	auto[0]	auto[1]	auto[1]	5409944	1			T24	42091		T26	88		T29	335841
all_values[2]	auto[1]	auto[0]	auto[1]	76243	1			T24	704		T29	4409		T1	47
all_values[2]	auto[1]	auto[1]	auto[1]	76750	1			T24	739		T29	4463		T1	26
all_values[3]	auto[0]	auto[0]	auto[0]	2941945	1			T22	1		T23	278		T24	19797
all_values[3]	auto[0]	auto[0]	auto[1]	5449235	1			T24	39657		T26	156		T27	6
all_values[3]	auto[0]	auto[1]	auto[0]	578429	1			T24	5171		T26	4		T27	4
all_values[3]	auto[0]	auto[1]	auto[1]	5426986	1			T24	43878		T26	60		T29	357960
all_values[3]	auto[1]	auto[0]	auto[1]	76969	1			T24	711		T27	1		T29	4398
all_values[3]	auto[1]	auto[1]	auto[1]	76000	1			T24	736		T29	4597		T1	58
all_values[4]	auto[0]	auto[0]	auto[0]	2926797	1			T22	1		T23	278		T24	19577
all_values[4]	auto[0]	auto[0]	auto[1]	5462851	1			T24	42511		T26	134		T27	14
all_values[4]	auto[0]	auto[1]	auto[0]	587028	1			T24	5072		T26	13		T27	3
all_values[4]	auto[0]	auto[1]	auto[1]	5419261	1			T24	41379		T26	81		T29	352523
all_values[4]	auto[1]	auto[0]	auto[1]	76822	1			T24	661		T27	3		T29	4513
all_values[4]	auto[1]	auto[1]	auto[1]	76805	1			T24	750		T29	4535		T1	42
all_values[5]	auto[0]	auto[0]	auto[0]	2932845	1			T22	1		T23	278		T24	19678
all_values[5]	auto[0]	auto[0]	auto[1]	5478253	1			T24	42354		T26	86		T27	5
all_values[5]	auto[0]	auto[1]	auto[0]	591515	1			T24	5211		T26	15		T27	6
all_values[5]	auto[0]	auto[1]	auto[1]	5393430	1			T24	41280		T26	121		T27	6
all_values[5]	auto[1]	auto[0]	auto[1]	77043	1			T24	697		T27	1		T29	4455
all_values[5]	auto[1]	auto[1]	auto[1]	76478	1			T24	730		T29	4477		T1	46
all_values[6]	auto[0]	auto[0]	auto[0]	2936746	1			T22	1		T23	278		T24	19636
all_values[6]	auto[0]	auto[0]	auto[1]	5471737	1			T24	41848		T26	147		T27	2
all_values[6]	auto[0]	auto[1]	auto[0]	586911	1			T24	4760		T26	12		T27	3
all_values[6]	auto[0]	auto[1]	auto[1]	5400646	1			T24	42277		T26	48		T27	12
all_values[6]	auto[1]	auto[0]	auto[1]	76462	1			T24	674		T29	4575		T1	42
all_values[6]	auto[1]	auto[1]	auto[1]	77062	1			T24	755		T27	1		T29	4460
all_values[7]	auto[0]	auto[0]	auto[0]	2935431	1			T22	1		T23	278		T24	19511
all_values[7]	auto[0]	auto[0]	auto[1]	5433675	1			T24	42774		T26	57		T29	337019
all_values[7]	auto[0]	auto[1]	auto[0]	587063	1			T24	4496		T26	8		T27	12
all_values[7]	auto[0]	auto[1]	auto[1]	5439670	1			T24	41725		T26	162		T27	4
all_values[7]	auto[1]	auto[0]	auto[1]	77039	1			T24	723		T29	4346		T1	44
all_values[7]	auto[1]	auto[1]	auto[1]	76686	1			T24	721		T29	4534		T1	30
all_values[8]	auto[0]	auto[0]	auto[0]	2933892	1			T22	1		T23	278		T24	19630
all_values[8]	auto[0]	auto[0]	auto[1]	5432418	1			T24	39642		T26	116		T27	12
all_values[8]	auto[0]	auto[1]	auto[0]	596668	1			T24	4658		T26	15		T27	3
all_values[8]	auto[0]	auto[1]	auto[1]	5433264	1			T24	44578		T26	97		T29	341632
all_values[8]	auto[1]	auto[0]	auto[1]	76628	1			T24	651		T27	3		T29	4539
all_values[8]	auto[1]	auto[1]	auto[1]	76694	1			T24	791		T29	4453		T1	37
all_values[9]	auto[0]	auto[0]	auto[0]	2927359	1			T22	1		T23	278		T24	19779
all_values[9]	auto[0]	auto[0]	auto[1]	5458139	1			T24	42105		T26	119		T27	3
all_values[9]	auto[0]	auto[1]	auto[0]	586821	1			T24	4218		T26	18		T29	36519
all_values[9]	auto[0]	auto[1]	auto[1]	5424004	1			T24	42414		T26	75		T27	12
all_values[9]	auto[1]	auto[0]	auto[1]	76753	1			T24	707		T29	4636		T1	30
all_values[9]	auto[1]	auto[1]	auto[1]	76488	1			T24	727		T27	1		T29	4399
all_values[10]	auto[0]	auto[0]	auto[0]	2928220	1			T22	1		T23	278		T24	19743
all_values[10]	auto[0]	auto[0]	auto[1]	5454960	1			T24	41774		T26	146		T27	8
all_values[10]	auto[0]	auto[1]	auto[0]	590996	1			T24	4923		T26	5		T27	3
all_values[10]	auto[0]	auto[1]	auto[1]	5422080	1			T24	42092		T26	88		T29	345215
all_values[10]	auto[1]	auto[0]	auto[1]	77083	1			T24	752		T27	2		T29	4482
all_values[10]	auto[1]	auto[1]	auto[1]	76225	1			T24	666		T27	1		T29	4487
all_values[11]	auto[0]	auto[0]	auto[0]	2929689	1			T22	1		T23	278		T24	20001
all_values[11]	auto[0]	auto[0]	auto[1]	5463344	1			T24	42689		T26	92		T27	12
all_values[11]	auto[0]	auto[1]	auto[0]	586293	1			T24	4707		T26	22		T29	39089
all_values[11]	auto[0]	auto[1]	auto[1]	5416429	1			T24	41130		T26	108		T27	4
all_values[11]	auto[1]	auto[0]	auto[1]	76765	1			T24	713		T29	4491		T1	39
all_values[11]	auto[1]	auto[1]	auto[1]	77044	1			T24	710		T29	4523		T1	35
all_values[12]	auto[0]	auto[0]	auto[0]	2933901	1			T22	1		T23	278		T24	20017
all_values[12]	auto[0]	auto[0]	auto[1]	5437918	1			T24	42621		T26	155		T27	2
all_values[12]	auto[0]	auto[1]	auto[0]	583492	1			T24	4506		T26	15		T27	3
all_values[12]	auto[0]	auto[1]	auto[1]	5441195	1			T24	41392		T26	55		T29	354665
all_values[12]	auto[1]	auto[0]	auto[1]	76778	1			T24	720		T27	1		T29	4564
all_values[12]	auto[1]	auto[1]	auto[1]	76280	1			T24	694		T29	4458		T1	37
all_values[13]	auto[0]	auto[0]	auto[0]	2940597	1			T22	1		T23	278		T24	19939
all_values[13]	auto[0]	auto[0]	auto[1]	5417153	1			T24	41208		T26	115		T27	7
all_values[13]	auto[0]	auto[1]	auto[0]	597071	1			T24	4628		T26	20		T27	1
all_values[13]	auto[0]	auto[1]	auto[1]	5441054	1			T24	42780		T26	103		T27	7
all_values[13]	auto[1]	auto[0]	auto[1]	76670	1			T24	712		T29	4548		T1	42
all_values[13]	auto[1]	auto[1]	auto[1]	77019	1			T24	683		T27	1		T29	4545
all_values[14]	auto[0]	auto[0]	auto[0]	2921523	1			T22	1		T23	278		T24	20250
all_values[14]	auto[0]	auto[0]	auto[1]	5449089	1			T24	42800		T26	68		T27	3
all_values[14]	auto[0]	auto[1]	auto[0]	581210	1			T24	4841		T26	29		T27	4
all_values[14]	auto[0]	auto[1]	auto[1]	5443671	1			T24	40669		T26	140		T27	8
all_values[14]	auto[1]	auto[0]	auto[1]	77557	1			T24	737		T29	4437		T1	32
all_values[14]	auto[1]	auto[1]	auto[1]	76514	1			T24	653		T27	1		T29	4534
all_values[15]	auto[0]	auto[0]	auto[0]	2934356	1			T22	1		T23	278		T24	19571
all_values[15]	auto[0]	auto[0]	auto[1]	5462012	1			T24	44870		T26	101		T29	357292
all_values[15]	auto[0]	auto[1]	auto[0]	583686	1			T24	4647		T26	13		T27	1
all_values[15]	auto[0]	auto[1]	auto[1]	5415863	1			T24	39509		T26	121		T27	8
all_values[15]	auto[1]	auto[0]	auto[1]	77091	1			T24	701		T27	1		T29	4692
all_values[15]	auto[1]	auto[1]	auto[1]	76556	1			T24	652		T29	4326		T1	40
all_values[16]	auto[0]	auto[0]	auto[0]	2927063	1			T22	1		T23	278		T24	19697
all_values[16]	auto[0]	auto[0]	auto[1]	5427643	1			T24	41283		T26	125		T29	343217
all_values[16]	auto[0]	auto[1]	auto[0]	588293	1			T24	4786		T26	15		T27	9
all_values[16]	auto[0]	auto[1]	auto[1]	5452818	1			T24	42782		T26	97		T29	352840
all_values[16]	auto[1]	auto[0]	auto[1]	77001	1			T24	733		T27	1		T29	4541
all_values[16]	auto[1]	auto[1]	auto[1]	76746	1			T24	669		T29	4427		T1	39
all_values[17]	auto[0]	auto[0]	auto[0]	2931563	1			T22	1		T23	278		T24	19756
all_values[17]	auto[0]	auto[0]	auto[1]	5468979	1			T24	42652		T26	126		T27	13
all_values[17]	auto[0]	auto[1]	auto[0]	589100	1			T24	4731		T26	12		T29	39015
all_values[17]	auto[0]	auto[1]	auto[1]	5406596	1			T24	41405		T26	77		T27	4
all_values[17]	auto[1]	auto[0]	auto[1]	76789	1			T24	725		T29	4375		T1	43
all_values[17]	auto[1]	auto[1]	auto[1]	76537	1			T24	681		T29	4577		T1	28
all_values[18]	auto[0]	auto[0]	auto[0]	2936547	1			T22	1		T23	278		T24	19227
all_values[18]	auto[0]	auto[0]	auto[1]	5424712	1			T24	43012		T26	117		T27	7
all_values[18]	auto[0]	auto[1]	auto[0]	584438	1			T24	4732		T26	14		T27	3
all_values[18]	auto[0]	auto[1]	auto[1]	5450737	1			T24	41607		T26	81		T27	4
all_values[18]	auto[1]	auto[0]	auto[1]	76563	1			T24	691		T27	1		T29	4503
all_values[18]	auto[1]	auto[1]	auto[1]	76567	1			T24	681		T29	4473		T1	31
all_values[19]	auto[0]	auto[0]	auto[0]	2930091	1			T22	1		T23	278		T24	19651
all_values[19]	auto[0]	auto[0]	auto[1]	5451600	1			T24	39792		T26	160		T27	14
all_values[19]	auto[0]	auto[1]	auto[0]	586350	1			T24	5470		T26	25		T29	34471
all_values[19]	auto[0]	auto[1]	auto[1]	5428344	1			T24	43595		T26	46		T29	348473
all_values[19]	auto[1]	auto[0]	auto[1]	76444	1			T24	720		T27	2		T29	4370
all_values[19]	auto[1]	auto[1]	auto[1]	76735	1			T24	722		T29	4582		T1	34
all_values[20]	auto[0]	auto[0]	auto[0]	2933357	1			T22	1		T23	278		T24	19581
all_values[20]	auto[0]	auto[0]	auto[1]	5449142	1			T24	42245		T26	92		T27	1
all_values[20]	auto[0]	auto[1]	auto[0]	594823	1			T24	5349		T26	5		T29	35314
all_values[20]	auto[0]	auto[1]	auto[1]	5418741	1			T24	41336		T26	93		T27	8
all_values[20]	auto[1]	auto[0]	auto[1]	76960	1			T24	718		T27	1		T29	4591
all_values[20]	auto[1]	auto[1]	auto[1]	76541	1			T24	721		T27	1		T29	4428
all_values[21]	auto[0]	auto[0]	auto[0]	2925815	1			T22	1		T23	278		T24	20105
all_values[21]	auto[0]	auto[0]	auto[1]	5405210	1			T24	42797		T26	143		T27	2
all_values[21]	auto[0]	auto[1]	auto[0]	594488	1			T24	4457		T26	7		T27	3
all_values[21]	auto[0]	auto[1]	auto[1]	5470995	1			T24	41182		T26	74		T27	9
all_values[21]	auto[1]	auto[0]	auto[1]	76757	1			T24	682		T27	1		T29	4507
all_values[21]	auto[1]	auto[1]	auto[1]	76299	1			T24	727		T27	1		T29	4427
all_values[22]	auto[0]	auto[0]	auto[0]	2935352	1			T22	1		T23	278		T24	19444
all_values[22]	auto[0]	auto[0]	auto[1]	5476109	1			T24	41367		T26	125		T27	8
all_values[22]	auto[0]	auto[1]	auto[0]	587638	1			T24	4530		T26	10		T29	36062
all_values[22]	auto[0]	auto[1]	auto[1]	5396881	1			T24	43252		T26	93		T29	336203
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all_values[22]	auto[1]	auto[1]	auto[1]	76262	1			T24	687		T29	4561		T1	29
all_values[23]	auto[0]	auto[0]	auto[0]	2931762	1			T22	1		T23	278		T24	19963
all_values[23]	auto[0]	auto[0]	auto[1]	5447845	1			T24	42944		T26	114		T27	7
all_values[23]	auto[0]	auto[1]	auto[0]	587653	1			T24	4872		T26	16		T27	3
all_values[23]	auto[0]	auto[1]	auto[1]	5429107	1			T24	40802		T26	102		T29	351914
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all_values[23]	auto[1]	auto[1]	auto[1]	76335	1			T24	654		T29	4612		T1	30
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all_values[24]	auto[0]	auto[0]	auto[1]	5441213	1			T24	41719		T26	48		T27	4
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all_values[24]	auto[0]	auto[1]	auto[1]	5439201	1			T24	42137		T26	139		T29	336268
all_values[24]	auto[1]	auto[0]	auto[1]	76553	1			T24	725		T29	4471		T1	47
all_values[24]	auto[1]	auto[1]	auto[1]	76730	1			T24	722		T29	4517		T1	31
all_values[25]	auto[0]	auto[0]	auto[0]	2931093	1			T22	1		T23	278		T24	20064
all_values[25]	auto[0]	auto[0]	auto[1]	5457388	1			T24	44060		T26	115		T29	345664
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all_values[25]	auto[1]	auto[0]	auto[1]	76700	1			T24	696		T27	2		T29	4431
all_values[25]	auto[1]	auto[1]	auto[1]	76647	1			T24	696		T29	4581		T1	41
all_values[26]	auto[0]	auto[0]	auto[0]	2936172	1			T22	1		T23	278		T24	19739
all_values[26]	auto[0]	auto[0]	auto[1]	5426221	1			T24	41399		T26	144		T27	9
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all_values[26]	auto[1]	auto[1]	auto[1]	76869	1			T24	712		T27	1		T29	4491
all_values[27]	auto[0]	auto[0]	auto[0]	2923472	1			T22	1		T23	278		T24	19734
all_values[27]	auto[0]	auto[0]	auto[1]	5453936	1			T24	43158		T26	90		T27	3
all_values[27]	auto[0]	auto[1]	auto[0]	578796	1			T24	4158		T26	20		T27	3
all_values[27]	auto[0]	auto[1]	auto[1]	5439537	1			T24	41505		T26	118		T27	8
all_values[27]	auto[1]	auto[0]	auto[1]	77130	1			T24	692		T27	1		T29	4490
all_values[27]	auto[1]	auto[1]	auto[1]	76693	1			T24	703		T27	1		T29	4536
all_values[28]	auto[0]	auto[0]	auto[0]	2926226	1			T22	1		T23	278		T24	19271
all_values[28]	auto[0]	auto[0]	auto[1]	5485507	1			T24	40305		T26	99		T29	355011
all_values[28]	auto[0]	auto[1]	auto[0]	590041	1			T24	5088		T26	25		T27	1
all_values[28]	auto[0]	auto[1]	auto[1]	5394642	1			T24	43830		T26	95		T27	2
all_values[28]	auto[1]	auto[0]	auto[1]	77190	1			T24	757		T29	4332		T1	41
all_values[28]	auto[1]	auto[1]	auto[1]	75958	1			T24	699		T29	4624		T1	33
all_values[29]	auto[0]	auto[0]	auto[0]	2938625	1			T22	1		T23	278		T24	19687
all_values[29]	auto[0]	auto[0]	auto[1]	5438397	1			T24	43315		T26	91		T27	16
all_values[29]	auto[0]	auto[1]	auto[0]	590957	1			T24	4565		T26	27		T29	36653
all_values[29]	auto[0]	auto[1]	auto[1]	5428405	1			T24	40977		T26	75		T29	345613
all_values[29]	auto[1]	auto[0]	auto[1]	76799	1			T24	732		T29	4501		T1	38
all_values[29]	auto[1]	auto[1]	auto[1]	76381	1			T24	674		T29	4454		T1	42
all_values[30]	auto[0]	auto[0]	auto[0]	2933008	1			T22	1		T23	278		T24	20019
all_values[30]	auto[0]	auto[0]	auto[1]	5420148	1			T24	43217		T26	122		T27	8
all_values[30]	auto[0]	auto[1]	auto[0]	592288	1			T24	4926		T26	44		T27	5
all_values[30]	auto[0]	auto[1]	auto[1]	5450560	1			T24	40386		T26	56		T27	2
all_values[30]	auto[1]	auto[0]	auto[1]	76497	1			T24	687		T27	1		T29	4466
all_values[30]	auto[1]	auto[1]	auto[1]	77063	1			T24	715		T29	4487		T1	32
all_values[31]	auto[0]	auto[0]	auto[0]	2928996	1			T22	1		T23	278		T24	19629
all_values[31]	auto[0]	auto[0]	auto[1]	5454901	1			T24	42941		T26	76		T27	9
all_values[31]	auto[0]	auto[1]	auto[0]	594846	1			T24	4570		T26	24		T29	41294
all_values[31]	auto[0]	auto[1]	auto[1]	5417672	1			T24	41350		T26	139		T27	4
all_values[31]	auto[1]	auto[0]	auto[1]	76914	1			T24	781		T27	1		T29	4504
all_values[31]	auto[1]	auto[1]	auto[1]	76235	1			T24	679		T29	4429		T1	46

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal