Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[1]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[2]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[3]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[4]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[5]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[6]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[7]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[8]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[9]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[10]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[11]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[12]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[13]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[14]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[15]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[16]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[17]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[18]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[19]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[20]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[21]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[22]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[23]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[24]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[25]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[26]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[27]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[28]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[29]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[30]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[31]	14305445	1			T22	1		T23	543		T24	109589

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

273815548

1

T22

32

T23

13928

T24

231408

auto[1]

183958692

1

T23

3448

T24

119276

T25

1843

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

369669646

1

T22

32

T23

13165

T24

269251

auto[1]

88104594

1

T23

4211

T24

814336

T25

164

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

343412804

1

T22

32

T23

8895

T24

246957

auto[1]

114361436

1

T23

8481

T24

103727

T25

1101

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5375947	1			T22	1		T23	169		T24	40434
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3963708	1			T23	23		T24	23548		T25	20
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1384286	1			T23	63		T24	13186		T25	2
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1790610	1			T23	179		T24	18505		T25	2
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	416477	1			T23	23		T24	1278		T25	43
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1374417	1			T23	86		T24	12638		T25	4
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5372217	1			T22	1		T23	162		T24	41253
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3971312	1			T23	12		T24	23225		T25	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1381419	1			T23	21		T24	12739		T27	2
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1787727	1			T23	258		T24	18125		T25	17
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	414192	1			T23	30		T24	1303		T25	54
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1378578	1			T23	60		T24	12944		T25	4
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5370719	1			T22	1		T23	168		T24	41071
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3974616	1			T23	13		T24	23420		T25	35
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1386266	1			T23	80		T24	12976		T25	6
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1785537	1			T23	187		T24	18164		T25	5
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	415261	1			T23	27		T24	1209		T25	19
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1373046	1			T23	68		T24	12749		T25	2
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5384926	1			T22	1		T23	205		T24	40926
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3960891	1			T23	26		T24	23371		T25	40
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1389609	1			T23	34		T24	13102		T27	2
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1784740	1			T23	201		T24	18236		T25	5
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	413368	1			T23	15		T24	1312		T25	19
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1371911	1			T23	62		T24	12642		T25	2
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5388690	1			T22	1		T23	184		T24	41059
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3958222	1			T23	17		T24	23314		T25	35
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1385242	1			T23	42		T24	12716		T27	4
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1782514	1			T23	212		T24	18346		T25	11
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	415432	1			T23	21		T24	1213		T25	13
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1375345	1			T23	67		T24	12941		T25	2
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5378906	1			T22	1		T23	156		T24	41356
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3968728	1			T23	28		T24	23412		T25	39
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1381802	1			T23	51		T24	12436		T25	4
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1787760	1			T23	194		T24	18541		T25	8
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	415193	1			T23	27		T24	1287		T25	18
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1373056	1			T23	87		T24	12557		T29	81777
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5366606	1			T22	1		T23	201		T24	41176
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3971766	1			T23	32		T24	23315		T25	56
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1383626	1			T23	62		T24	12868		T25	8
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1791038	1			T23	168		T24	18497		T29	121707
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	414481	1			T23	13		T24	1256		T29	8588
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1377928	1			T23	67		T24	12477		T29	83255
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5380949	1			T22	1		T23	121		T24	41124
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3966719	1			T23	20		T24	23280		T25	60
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1386052	1			T23	81		T24	12366		T25	6
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1785258	1			T23	219		T24	18450		T29	120513
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	410963	1			T23	22		T24	1213		T29	8735
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1375504	1			T23	80		T24	13156		T29	82872
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5375667	1			T22	1		T23	203		T24	41302
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3972565	1			T23	20		T24	23242		T25	21
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1384844	1			T23	88		T24	12951		T25	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1784900	1			T23	163		T24	17955		T25	11
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	414064	1			T23	25		T24	1216		T25	30
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1373405	1			T23	44		T24	12923		T25	8
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5375175	1			T22	1		T23	239		T24	40388
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3967101	1			T23	33		T24	23462		T25	52
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1388258	1			T23	77		T24	13043		T25	10
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1788036	1			T23	134		T24	18047		T29	122361
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	412226	1			T23	14		T24	1251		T29	8817
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1374649	1			T23	46		T24	13398		T29	82592
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5388314	1			T22	1		T23	178		T24	41057
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3957072	1			T23	31		T24	23359		T25	53
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1390234	1			T23	54		T24	12453		T25	10
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1784760	1			T23	183		T24	18788		T29	121236
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	412926	1			T23	17		T24	1311		T29	8657
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1372139	1			T23	80		T24	12621		T29	82662
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5393743	1			T22	1		T23	148		T24	41210
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3955982	1			T23	18		T24	23179		T25	54
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1384735	1			T23	69		T24	12768		T25	8
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1787166	1			T23	244		T24	18656		T29	122843
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	413451	1			T23	18		T24	1222		T29	8635
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1370368	1			T23	46		T24	12554		T29	81025
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5384477	1			T22	1		T23	158		T24	40922
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3961056	1			T23	14		T24	23565		T25	14
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1386175	1			T23	56		T24	12881		T25	2
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1788459	1			T23	210		T24	18376		T25	14
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	411934	1			T23	28		T24	1214		T25	31
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1373344	1			T23	77		T24	12631		T25	4
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5383593	1			T22	1		T23	231		T24	40777
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3964006	1			T23	26		T24	23423		T25	42
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1382664	1			T23	101		T24	12667		T25	2
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1789671	1			T23	116		T24	18422		T25	8
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	412410	1			T23	19		T24	1212		T25	18
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1373101	1			T23	50		T24	13088		T29	81390
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5380624	1			T22	1		T23	186		T24	40953
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3969126	1			T23	24		T24	23304		T25	54
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1384533	1			T23	69		T24	12880		T25	6
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1783967	1			T23	194		T24	17943		T29	122821
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	412557	1			T23	14		T24	1284		T29	8411
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1374638	1			T23	56		T24	13225		T29	82491
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5392772	1			T22	1		T23	207		T24	41466
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3957957	1			T23	22		T24	23266		T25	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1381722	1			T23	73		T24	13166		T29	84093
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1787137	1			T23	155		T24	18072		T25	17
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	413952	1			T23	16		T24	1296		T25	56
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1371905	1			T23	70		T24	12323		T25	2
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5382159	1			T22	1		T23	189		T24	41419
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3971503	1			T23	23		T24	23256		T25	23
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1375162	1			T23	68		T24	12666		T27	2
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1792886	1			T23	183		T24	18748		T25	11
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	413950	1			T23	18		T24	1263		T25	41
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1369785	1			T23	62		T24	12237		T29	81838
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5379060	1			T22	1		T23	155		T24	40960
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3970811	1			T23	19		T24	23203		T25	26
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1374539	1			T23	69		T24	12422		T25	2
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1795311	1			T23	176		T24	19059		T25	11
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	414540	1			T23	16		T24	1346		T25	20
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1371184	1			T23	108		T24	12599		T25	6
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5391472	1			T22	1		T23	206		T24	41504
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3960591	1			T23	19		T24	23314		T25	10
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1381143	1			T23	77		T24	13018		T27	2
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1789137	1			T23	161		T24	18126		T25	10
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	412225	1			T23	18		T24	1198		T25	50
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1370877	1			T23	62		T24	12429		T29	82082
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5391301	1			T22	1		T23	209		T24	41463
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3964481	1			T23	18		T24	23425		T25	37
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1383194	1			T23	60		T24	12516		T25	8
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1790358	1			T23	167		T24	18298		T25	8
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	412637	1			T23	22		T24	1279		T25	18
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1363474	1			T23	67		T24	12608		T29	81454
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5389083	1			T22	1		T23	240		T24	41210
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3967533	1			T23	36		T24	22990		T25	20
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1379978	1			T23	100		T24	12508		T27	2
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1786213	1			T23	124		T24	18585		T25	9
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	413220	1			T23	10		T24	1248		T25	34
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1369418	1			T23	33		T24	13048		T25	6
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5392199	1			T22	1		T23	161		T24	40875
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3957357	1			T23	16		T24	23298		T25	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1380692	1			T23	65		T24	12626		T27	2
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1793404	1			T23	183		T24	18937		T25	17
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	415560	1			T23	26		T24	1303		T25	50
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1366233	1			T23	92		T24	12550		T25	8
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5377892	1			T22	1		T23	162		T24	41244
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3972161	1			T23	13		T24	23192		T25	2
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1380084	1			T23	90		T24	12600		T29	83115
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1794723	1			T23	182		T24	18539		T25	14
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	414163	1			T23	31		T24	1243		T25	60
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1366422	1			T23	65		T24	12771		T27	4
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5383334	1			T22	1		T23	184		T24	40505
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3966151	1			T23	24		T24	23397		T25	40
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1373240	1			T23	57		T24	12696		T25	2
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1800646	1			T23	170		T24	19171		T25	4
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	415288	1			T23	18		T24	1376		T25	17
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1366786	1			T23	90		T24	12444		T25	2
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5395765	1			T22	1		T23	215		T24	41297
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3960479	1			T23	24		T24	23199		T25	40
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1377083	1			T23	58		T24	12697		T25	6
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1793251	1			T23	177		T24	18509		T25	7
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	414612	1			T23	15		T24	1370		T25	15
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1364255	1			T23	54		T24	12517		T25	2
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5399276	1			T22	1		T23	174		T24	41561
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3955333	1			T23	16		T24	23277		T25	18
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1382490	1			T23	52		T24	12637		T25	2
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1789465	1			T23	229		T24	18392		T25	8
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	410059	1			T23	19		T24	1198		T25	40
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1368822	1			T23	53		T24	12524		T25	4
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5384252	1			T22	1		T23	240		T24	40683
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3961245	1			T23	32		T24	23154		T25	63
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1383055	1			T23	80		T24	13152		T25	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1792352	1			T23	143		T24	18407		T29	123089
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	413476	1			T23	15		T24	1344		T25	3
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1371065	1			T23	33		T24	12849		T29	81325
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5394249	1			T22	1		T23	187		T24	41150
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3964460	1			T23	25		T24	23456		T25	35
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1381177	1			T23	47		T24	12995		T25	6
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1785793	1			T23	186		T24	18372		T25	6
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	413137	1			T23	21		T24	1161		T25	7
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1366629	1			T23	77		T24	12455		T25	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5394854	1			T22	1		T23	271		T24	40764
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3964719	1			T23	35		T24	23316		T25	18
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1382131	1			T23	107		T24	12846		T27	2
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1785193	1			T23	82		T24	18853		T25	5
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	411199	1			T23	12		T24	1292		T25	38
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1367349	1			T23	36		T24	12518		T25	6
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5401447	1			T22	1		T23	218		T24	40930
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3954271	1			T23	27		T24	23216		T25	6
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1382573	1			T23	90		T24	12692		T29	82012
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1788982	1			T23	111		T24	18676		T25	11
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	413989	1			T23	24		T24	1299		T25	47
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1364183	1			T23	73		T24	12776		T25	4
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5382470	1			T22	1		T23	144		T24	41799
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3964517	1			T23	17		T24	23600		T25	25
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1379998	1			T23	66		T24	12249		T25	2
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1792333	1			T23	222		T24	18467		T25	6
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	416777	1			T23	26		T24	1151		T25	34
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1369350	1			T23	68		T24	12323		T27	3
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5394379	1			T22	1		T23	174		T24	40984
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3954840	1			T23	16		T24	23434		T25	36
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1377002	1			T23	24		T24	12819		T29	82178
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1794696	1			T23	239		T24	18664		T25	10
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	414108	1			T23	29		T24	1204		T25	23
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1370420	1			T23	61		T24	12484		T29	82109

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal