Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[1]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[2]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[3]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[4]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[5]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[6]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[7]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[8]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[9]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[10]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[11]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[12]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[13]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[14]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[15]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[16]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[17]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[18]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[19]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[20]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[21]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[22]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[23]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[24]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[25]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[26]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[27]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[28]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[29]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[30]	14305445	1			T22	1		T23	543		T24	109589
bins_for_gpio_bits[31]	14305445	1			T22	1		T23	543		T24	109589

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

273815548

1

T22

32

T23

13928

T24

231408

auto[1]

183958692

1

T23

3448

T24

119276

T25

1843

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

273807276

1

T22

32

T23

13921

T24

231379

auto[1]

183966964

1

T23

3455

T24

119305

T25

1843

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8303337	1			T22	1		T23	395		T24	69835
bins_for_gpio_bits[0]	auto[0]	auto[1]	247251	1			T23	16		T24	2279		T25	1
bins_for_gpio_bits[0]	auto[1]	auto[0]	247506	1			T23	16		T24	2290		T25	1
bins_for_gpio_bits[0]	auto[1]	auto[1]	5507351	1			T23	116		T24	35185		T25	66
bins_for_gpio_bits[1]	auto[0]	auto[0]	8294235	1			T22	1		T23	427		T24	69797
bins_for_gpio_bits[1]	auto[0]	auto[1]	246889	1			T23	14		T24	2312		T29	14930
bins_for_gpio_bits[1]	auto[1]	auto[0]	247128	1			T23	14		T24	2320		T29	14930
bins_for_gpio_bits[1]	auto[1]	auto[1]	5517193	1			T23	88		T24	35160		T25	59
bins_for_gpio_bits[2]	auto[0]	auto[0]	8296229	1			T22	1		T23	425		T24	69937
bins_for_gpio_bits[2]	auto[0]	auto[1]	246030	1			T23	10		T24	2261		T25	2
bins_for_gpio_bits[2]	auto[1]	auto[0]	246293	1			T23	10		T24	2274		T25	2
bins_for_gpio_bits[2]	auto[1]	auto[1]	5516893	1			T23	98		T24	35117		T25	54
bins_for_gpio_bits[3]	auto[0]	auto[0]	8312055	1			T22	1		T23	429		T24	69987
bins_for_gpio_bits[3]	auto[0]	auto[1]	246993	1			T23	11		T24	2265		T29	14980
bins_for_gpio_bits[3]	auto[1]	auto[0]	247220	1			T23	11		T24	2277		T29	14982
bins_for_gpio_bits[3]	auto[1]	auto[1]	5499177	1			T23	92		T24	35060		T25	61
bins_for_gpio_bits[4]	auto[0]	auto[0]	8309718	1			T22	1		T23	426		T24	69787
bins_for_gpio_bits[4]	auto[0]	auto[1]	246451	1			T23	12		T24	2320		T29	14686
bins_for_gpio_bits[4]	auto[1]	auto[0]	246728	1			T23	12		T24	2334		T29	14687
bins_for_gpio_bits[4]	auto[1]	auto[1]	5502548	1			T23	93		T24	35148		T25	50
bins_for_gpio_bits[5]	auto[0]	auto[0]	8302090	1			T22	1		T23	388		T24	70081
bins_for_gpio_bits[5]	auto[0]	auto[1]	246133	1			T23	12		T24	2244		T25	2
bins_for_gpio_bits[5]	auto[1]	auto[0]	246378	1			T23	13		T24	2252		T25	2
bins_for_gpio_bits[5]	auto[1]	auto[1]	5510844	1			T23	130		T24	35012		T25	55
bins_for_gpio_bits[6]	auto[0]	auto[0]	8293904	1			T22	1		T23	421		T24	70254
bins_for_gpio_bits[6]	auto[0]	auto[1]	247094	1			T23	9		T24	2284		T25	3
bins_for_gpio_bits[6]	auto[1]	auto[0]	247366	1			T23	10		T24	2287		T25	3
bins_for_gpio_bits[6]	auto[1]	auto[1]	5517081	1			T23	103		T24	34764		T25	53
bins_for_gpio_bits[7]	auto[0]	auto[0]	8304823	1			T22	1		T23	406		T24	69624
bins_for_gpio_bits[7]	auto[0]	auto[1]	247154	1			T23	14		T24	2307		T25	2
bins_for_gpio_bits[7]	auto[1]	auto[0]	247436	1			T23	15		T24	2316		T25	2
bins_for_gpio_bits[7]	auto[1]	auto[1]	5506032	1			T23	108		T24	35342		T25	58
bins_for_gpio_bits[8]	auto[0]	auto[0]	8298295	1			T22	1		T23	445		T24	69904
bins_for_gpio_bits[8]	auto[0]	auto[1]	246861	1			T23	9		T24	2294		T25	1
bins_for_gpio_bits[8]	auto[1]	auto[0]	247116	1			T23	9		T24	2304		T25	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	5513173	1			T23	80		T24	35087		T25	58
bins_for_gpio_bits[9]	auto[0]	auto[0]	8304426	1			T22	1		T23	442		T24	69097
bins_for_gpio_bits[9]	auto[0]	auto[1]	246796	1			T23	8		T24	2374		T25	3
bins_for_gpio_bits[9]	auto[1]	auto[0]	247043	1			T23	8		T24	2381		T25	3
bins_for_gpio_bits[9]	auto[1]	auto[1]	5507180	1			T23	85		T24	35737		T25	49
bins_for_gpio_bits[10]	auto[0]	auto[0]	8316162	1			T22	1		T23	401		T24	70004
bins_for_gpio_bits[10]	auto[0]	auto[1]	246864	1			T23	14		T24	2286		T25	3
bins_for_gpio_bits[10]	auto[1]	auto[0]	247146	1			T23	14		T24	2294		T25	3
bins_for_gpio_bits[10]	auto[1]	auto[1]	5495273	1			T23	114		T24	35005		T25	50
bins_for_gpio_bits[11]	auto[0]	auto[0]	8318943	1			T22	1		T23	453		T24	70364
bins_for_gpio_bits[11]	auto[0]	auto[1]	246444	1			T23	8		T24	2266		T25	3
bins_for_gpio_bits[11]	auto[1]	auto[0]	246701	1			T23	8		T24	2270		T25	3
bins_for_gpio_bits[11]	auto[1]	auto[1]	5493357	1			T23	74		T24	34689		T25	51
bins_for_gpio_bits[12]	auto[0]	auto[0]	8311678	1			T22	1		T23	412		T24	69925
bins_for_gpio_bits[12]	auto[0]	auto[1]	247190	1			T23	12		T24	2244		T25	1
bins_for_gpio_bits[12]	auto[1]	auto[0]	247433	1			T23	12		T24	2254		T25	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	5499144	1			T23	107		T24	35166		T25	48
bins_for_gpio_bits[13]	auto[0]	auto[0]	8308669	1			T22	1		T23	438		T24	69531
bins_for_gpio_bits[13]	auto[0]	auto[1]	246991	1			T23	10		T24	2327		T25	1
bins_for_gpio_bits[13]	auto[1]	auto[0]	247259	1			T23	10		T24	2335		T25	1
bins_for_gpio_bits[13]	auto[1]	auto[1]	5502526	1			T23	85		T24	35396		T25	59
bins_for_gpio_bits[14]	auto[0]	auto[0]	8302383	1			T22	1		T23	438		T24	69438
bins_for_gpio_bits[14]	auto[0]	auto[1]	246463	1			T23	11		T24	2331		T25	3
bins_for_gpio_bits[14]	auto[1]	auto[0]	246741	1			T23	11		T24	2338		T25	3
bins_for_gpio_bits[14]	auto[1]	auto[1]	5509858	1			T23	83		T24	35482		T25	51
bins_for_gpio_bits[15]	auto[0]	auto[0]	8314940	1			T22	1		T23	423		T24	70436
bins_for_gpio_bits[15]	auto[0]	auto[1]	246444	1			T23	12		T24	2259		T29	14889
bins_for_gpio_bits[15]	auto[1]	auto[0]	246691	1			T23	12		T24	2268		T29	14890
bins_for_gpio_bits[15]	auto[1]	auto[1]	5497370	1			T23	96		T24	34626		T25	59
bins_for_gpio_bits[16]	auto[0]	auto[0]	8302956	1			T22	1		T23	431		T24	70578
bins_for_gpio_bits[16]	auto[0]	auto[1]	246996	1			T23	9		T24	2253		T29	14895
bins_for_gpio_bits[16]	auto[1]	auto[0]	247251	1			T23	9		T24	2255		T29	14895
bins_for_gpio_bits[16]	auto[1]	auto[1]	5508242	1			T23	94		T24	34503		T25	64
bins_for_gpio_bits[17]	auto[0]	auto[0]	8302095	1			T22	1		T23	381		T24	70146
bins_for_gpio_bits[17]	auto[0]	auto[1]	246564	1			T23	19		T24	2287		T25	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	246815	1			T23	19		T24	2295		T25	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	5509971	1			T23	124		T24	34861		T25	51
bins_for_gpio_bits[18]	auto[0]	auto[0]	8314415	1			T22	1		T23	431		T24	70418
bins_for_gpio_bits[18]	auto[0]	auto[1]	247086	1			T23	13		T24	2223		T29	14939
bins_for_gpio_bits[18]	auto[1]	auto[0]	247337	1			T23	13		T24	2230		T29	14941
bins_for_gpio_bits[18]	auto[1]	auto[1]	5496607	1			T23	86		T24	34718		T25	60
bins_for_gpio_bits[19]	auto[0]	auto[0]	8318370	1			T22	1		T23	423		T24	70006
bins_for_gpio_bits[19]	auto[0]	auto[1]	246218	1			T23	13		T24	2257		T25	3
bins_for_gpio_bits[19]	auto[1]	auto[0]	246483	1			T23	13		T24	2271		T25	3
bins_for_gpio_bits[19]	auto[1]	auto[1]	5494374	1			T23	94		T24	35055		T25	52
bins_for_gpio_bits[20]	auto[0]	auto[0]	8308141	1			T22	1		T23	457		T24	69959
bins_for_gpio_bits[20]	auto[0]	auto[1]	246878	1			T23	7		T24	2331		T29	14860
bins_for_gpio_bits[20]	auto[1]	auto[0]	247133	1			T23	7		T24	2344		T29	14861
bins_for_gpio_bits[20]	auto[1]	auto[1]	5503293	1			T23	72		T24	34955		T25	60
bins_for_gpio_bits[21]	auto[0]	auto[0]	8319290	1			T22	1		T23	392		T24	70174
bins_for_gpio_bits[21]	auto[0]	auto[1]	246739	1			T23	17		T24	2261		T29	14725
bins_for_gpio_bits[21]	auto[1]	auto[0]	247005	1			T23	17		T24	2264		T29	14725
bins_for_gpio_bits[21]	auto[1]	auto[1]	5492411	1			T23	117		T24	34890		T25	59
bins_for_gpio_bits[22]	auto[0]	auto[0]	8305052	1			T22	1		T23	420		T24	70042
bins_for_gpio_bits[22]	auto[0]	auto[1]	247419	1			T23	14		T24	2335		T29	15131
bins_for_gpio_bits[22]	auto[1]	auto[0]	247647	1			T23	14		T24	2341		T29	15131
bins_for_gpio_bits[22]	auto[1]	auto[1]	5505327	1			T23	95		T24	34871		T25	62
bins_for_gpio_bits[23]	auto[0]	auto[0]	8310296	1			T22	1		T23	394		T24	70093
bins_for_gpio_bits[23]	auto[0]	auto[1]	246654	1			T23	17		T24	2271		T25	1
bins_for_gpio_bits[23]	auto[1]	auto[0]	246924	1			T23	17		T24	2279		T25	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	5501571	1			T23	115		T24	34946		T25	58
bins_for_gpio_bits[24]	auto[0]	auto[0]	8319088	1			T22	1		T23	439		T24	70214
bins_for_gpio_bits[24]	auto[0]	auto[1]	246764	1			T23	11		T24	2281		T25	2
bins_for_gpio_bits[24]	auto[1]	auto[0]	247011	1			T23	11		T24	2289		T25	2
bins_for_gpio_bits[24]	auto[1]	auto[1]	5492582	1			T23	82		T24	34805		T25	55
bins_for_gpio_bits[25]	auto[0]	auto[0]	8324564	1			T22	1		T23	444		T24	70347
bins_for_gpio_bits[25]	auto[0]	auto[1]	246378	1			T23	10		T24	2232		T25	1
bins_for_gpio_bits[25]	auto[1]	auto[0]	246667	1			T23	11		T24	2243		T25	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	5487836	1			T23	78		T24	34767		T25	61
bins_for_gpio_bits[26]	auto[0]	auto[0]	8311940	1			T22	1		T23	456		T24	69921
bins_for_gpio_bits[26]	auto[0]	auto[1]	247467	1			T23	7		T24	2309		T25	1
bins_for_gpio_bits[26]	auto[1]	auto[0]	247719	1			T23	7		T24	2321		T25	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	5498319	1			T23	73		T24	35038		T25	65
bins_for_gpio_bits[27]	auto[0]	auto[0]	8314088	1			T22	1		T23	405		T24	70230
bins_for_gpio_bits[27]	auto[0]	auto[1]	246854	1			T23	15		T24	2276		T25	2
bins_for_gpio_bits[27]	auto[1]	auto[0]	247131	1			T23	15		T24	2287		T25	2
bins_for_gpio_bits[27]	auto[1]	auto[1]	5497372	1			T23	108		T24	34796		T25	42
bins_for_gpio_bits[28]	auto[0]	auto[0]	8315226	1			T22	1		T23	452		T24	70175
bins_for_gpio_bits[28]	auto[0]	auto[1]	246692	1			T23	7		T24	2278		T29	14978
bins_for_gpio_bits[28]	auto[1]	auto[0]	246952	1			T23	8		T24	2288		T29	14980
bins_for_gpio_bits[28]	auto[1]	auto[1]	5496575	1			T23	76		T24	34848		T25	62
bins_for_gpio_bits[29]	auto[0]	auto[0]	8326744	1			T22	1		T23	409		T24	69955
bins_for_gpio_bits[29]	auto[0]	auto[1]	245987	1			T23	10		T24	2331		T29	14897
bins_for_gpio_bits[29]	auto[1]	auto[0]	246258	1			T23	10		T24	2343		T29	14897
bins_for_gpio_bits[29]	auto[1]	auto[1]	5486456	1			T23	114		T24	34960		T25	57
bins_for_gpio_bits[30]	auto[0]	auto[0]	8306992	1			T22	1		T23	416		T24	70274
bins_for_gpio_bits[30]	auto[0]	auto[1]	247544	1			T23	15		T24	2226		T25	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	247809	1			T23	16		T24	2241		T25	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	5503100	1			T23	96		T24	34848		T25	58
bins_for_gpio_bits[31]	auto[0]	auto[0]	8318967	1			T22	1		T23	425		T24	70206
bins_for_gpio_bits[31]	auto[0]	auto[1]	246877	1			T23	11		T24	2250		T29	14950
bins_for_gpio_bits[31]	auto[1]	auto[0]	247110	1			T23	12		T24	2261		T29	14950
bins_for_gpio_bits[31]	auto[1]	auto[1]	5492491	1			T23	95		T24	34872		T25	59