Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8484438 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62425 |
| auto[1] |
6065126 |
1 |
|
|
T24 |
47525 |
|
T26 |
144 |
|
T27 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13764236 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
103797 |
| auto[1] |
785328 |
1 |
|
|
T24 |
6153 |
|
T26 |
8 |
|
T29 |
50360 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8477853 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
61653 |
| auto[1] |
6071711 |
1 |
|
|
T24 |
48297 |
|
T26 |
154 |
|
T27 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2663619 |
1 |
|
|
T24 |
20932 |
|
T26 |
67 |
|
T27 |
5 |
| auto[1] |
auto[0] |
auto[1] |
396503 |
1 |
|
|
T24 |
3008 |
|
T26 |
4 |
|
T29 |
26119 |
| auto[1] |
auto[1] |
auto[0] |
2622764 |
1 |
|
|
T24 |
21212 |
|
T26 |
79 |
|
T27 |
5 |
| auto[1] |
auto[1] |
auto[1] |
388825 |
1 |
|
|
T24 |
3145 |
|
T26 |
4 |
|
T29 |
24241 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8462749 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
61431 |
| auto[1] |
6086815 |
1 |
|
|
T24 |
48519 |
|
T26 |
109 |
|
T27 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13759853 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104036 |
| auto[1] |
789711 |
1 |
|
|
T24 |
5914 |
|
T26 |
8 |
|
T29 |
51580 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8453001 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63481 |
| auto[1] |
6096563 |
1 |
|
|
T24 |
46469 |
|
T26 |
106 |
|
T27 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2661455 |
1 |
|
|
T24 |
20007 |
|
T26 |
54 |
|
T27 |
18 |
| auto[1] |
auto[0] |
auto[1] |
397443 |
1 |
|
|
T24 |
2926 |
|
T26 |
3 |
|
T29 |
25776 |
| auto[1] |
auto[1] |
auto[0] |
2645397 |
1 |
|
|
T24 |
20548 |
|
T26 |
44 |
|
T29 |
168910 |
| auto[1] |
auto[1] |
auto[1] |
392268 |
1 |
|
|
T24 |
2988 |
|
T26 |
5 |
|
T29 |
25804 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8460263 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62269 |
| auto[1] |
6089301 |
1 |
|
|
T24 |
47681 |
|
T26 |
93 |
|
T27 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13757465 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104075 |
| auto[1] |
792099 |
1 |
|
|
T24 |
5875 |
|
T26 |
10 |
|
T29 |
51851 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8439309 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62580 |
| auto[1] |
6110255 |
1 |
|
|
T24 |
47370 |
|
T26 |
119 |
|
T29 |
389800 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2653996 |
1 |
|
|
T24 |
20407 |
|
T26 |
70 |
|
T29 |
168986 |
| auto[1] |
auto[0] |
auto[1] |
395522 |
1 |
|
|
T24 |
2748 |
|
T26 |
6 |
|
T29 |
25777 |
| auto[1] |
auto[1] |
auto[0] |
2664160 |
1 |
|
|
T24 |
21088 |
|
T26 |
39 |
|
T29 |
168963 |
| auto[1] |
auto[1] |
auto[1] |
396577 |
1 |
|
|
T24 |
3127 |
|
T26 |
4 |
|
T29 |
26074 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8469798 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63403 |
| auto[1] |
6079766 |
1 |
|
|
T24 |
46547 |
|
T26 |
130 |
|
T27 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13761151 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104458 |
| auto[1] |
788413 |
1 |
|
|
T24 |
5492 |
|
T26 |
6 |
|
T29 |
51207 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8454841 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
65120 |
| auto[1] |
6094723 |
1 |
|
|
T24 |
44830 |
|
T26 |
96 |
|
T27 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2665013 |
1 |
|
|
T24 |
19806 |
|
T26 |
23 |
|
T27 |
14 |
| auto[1] |
auto[0] |
auto[1] |
396592 |
1 |
|
|
T24 |
2744 |
|
T26 |
2 |
|
T29 |
26522 |
| auto[1] |
auto[1] |
auto[0] |
2641297 |
1 |
|
|
T24 |
19532 |
|
T26 |
67 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[1] |
391821 |
1 |
|
|
T24 |
2748 |
|
T26 |
4 |
|
T29 |
24685 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8448597 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63358 |
| auto[1] |
6100967 |
1 |
|
|
T24 |
46592 |
|
T26 |
70 |
|
T27 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13755607 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104255 |
| auto[1] |
793957 |
1 |
|
|
T24 |
5695 |
|
T26 |
4 |
|
T29 |
55012 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8427906 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
64444 |
| auto[1] |
6121658 |
1 |
|
|
T24 |
45506 |
|
T26 |
130 |
|
T27 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2651856 |
1 |
|
|
T24 |
20160 |
|
T26 |
91 |
|
T27 |
18 |
| auto[1] |
auto[0] |
auto[1] |
393952 |
1 |
|
|
T24 |
2940 |
|
T26 |
3 |
|
T29 |
26328 |
| auto[1] |
auto[1] |
auto[0] |
2675845 |
1 |
|
|
T24 |
19651 |
|
T26 |
35 |
|
T29 |
183271 |
| auto[1] |
auto[1] |
auto[1] |
400005 |
1 |
|
|
T24 |
2755 |
|
T26 |
1 |
|
T29 |
28684 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8434420 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
61859 |
| auto[1] |
6115144 |
1 |
|
|
T24 |
48091 |
|
T26 |
123 |
|
T27 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13764940 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
103996 |
| auto[1] |
784624 |
1 |
|
|
T24 |
5954 |
|
T26 |
11 |
|
T29 |
49715 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8483347 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62327 |
| auto[1] |
6066217 |
1 |
|
|
T24 |
47623 |
|
T26 |
130 |
|
T29 |
378085 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2623481 |
1 |
|
|
T24 |
20490 |
|
T26 |
68 |
|
T29 |
163965 |
| auto[1] |
auto[0] |
auto[1] |
389899 |
1 |
|
|
T24 |
2815 |
|
T26 |
3 |
|
T29 |
24668 |
| auto[1] |
auto[1] |
auto[0] |
2658112 |
1 |
|
|
T24 |
21179 |
|
T26 |
51 |
|
T29 |
164405 |
| auto[1] |
auto[1] |
auto[1] |
394725 |
1 |
|
|
T24 |
3139 |
|
T26 |
8 |
|
T29 |
25047 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8448169 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63787 |
| auto[1] |
6101395 |
1 |
|
|
T24 |
46163 |
|
T26 |
169 |
|
T27 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13755687 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
103942 |
| auto[1] |
793877 |
1 |
|
|
T24 |
6008 |
|
T26 |
9 |
|
T29 |
51595 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8420186 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62106 |
| auto[1] |
6129378 |
1 |
|
|
T24 |
47844 |
|
T26 |
165 |
|
T27 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2667860 |
1 |
|
|
T24 |
20499 |
|
T26 |
38 |
|
T29 |
167837 |
| auto[1] |
auto[0] |
auto[1] |
397035 |
1 |
|
|
T24 |
2968 |
|
T26 |
3 |
|
T29 |
25470 |
| auto[1] |
auto[1] |
auto[0] |
2667641 |
1 |
|
|
T24 |
21337 |
|
T26 |
118 |
|
T27 |
8 |
| auto[1] |
auto[1] |
auto[1] |
396842 |
1 |
|
|
T24 |
3040 |
|
T26 |
6 |
|
T29 |
26125 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8473459 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
65142 |
| auto[1] |
6076105 |
1 |
|
|
T24 |
44808 |
|
T26 |
134 |
|
T27 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13762883 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104475 |
| auto[1] |
786681 |
1 |
|
|
T24 |
5475 |
|
T26 |
5 |
|
T29 |
50480 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8471587 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
65283 |
| auto[1] |
6077977 |
1 |
|
|
T24 |
44667 |
|
T26 |
113 |
|
T29 |
384786 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2660498 |
1 |
|
|
T24 |
20633 |
|
T26 |
30 |
|
T29 |
168747 |
| auto[1] |
auto[0] |
auto[1] |
395795 |
1 |
|
|
T24 |
2974 |
|
T26 |
2 |
|
T29 |
25513 |
| auto[1] |
auto[1] |
auto[0] |
2630798 |
1 |
|
|
T24 |
18559 |
|
T26 |
78 |
|
T29 |
165559 |
| auto[1] |
auto[1] |
auto[1] |
390886 |
1 |
|
|
T24 |
2501 |
|
T26 |
3 |
|
T29 |
24967 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8431707 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
61713 |
| auto[1] |
6117857 |
1 |
|
|
T24 |
48237 |
|
T26 |
112 |
|
T27 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13762879 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104253 |
| auto[1] |
786685 |
1 |
|
|
T24 |
5697 |
|
T26 |
10 |
|
T29 |
52630 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8475943 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
64155 |
| auto[1] |
6073621 |
1 |
|
|
T24 |
45795 |
|
T26 |
145 |
|
T27 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2631287 |
1 |
|
|
T24 |
19924 |
|
T26 |
61 |
|
T27 |
9 |
| auto[1] |
auto[0] |
auto[1] |
390518 |
1 |
|
|
T24 |
2746 |
|
T26 |
7 |
|
T29 |
25129 |
| auto[1] |
auto[1] |
auto[0] |
2655649 |
1 |
|
|
T24 |
20174 |
|
T26 |
74 |
|
T27 |
1 |
| auto[1] |
auto[1] |
auto[1] |
396167 |
1 |
|
|
T24 |
2951 |
|
T26 |
3 |
|
T29 |
27501 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8477331 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63133 |
| auto[1] |
6072233 |
1 |
|
|
T24 |
46817 |
|
T26 |
89 |
|
T27 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13765217 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104426 |
| auto[1] |
784347 |
1 |
|
|
T24 |
5524 |
|
T26 |
8 |
|
T29 |
52501 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8482365 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
64312 |
| auto[1] |
6067199 |
1 |
|
|
T24 |
45638 |
|
T26 |
116 |
|
T27 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2659234 |
1 |
|
|
T24 |
19906 |
|
T26 |
79 |
|
T27 |
14 |
| auto[1] |
auto[0] |
auto[1] |
395339 |
1 |
|
|
T24 |
2613 |
|
T26 |
5 |
|
T29 |
27191 |
| auto[1] |
auto[1] |
auto[0] |
2623618 |
1 |
|
|
T24 |
20208 |
|
T26 |
29 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[1] |
389008 |
1 |
|
|
T24 |
2911 |
|
T26 |
3 |
|
T29 |
25310 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8437822 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62930 |
| auto[1] |
6111742 |
1 |
|
|
T24 |
47020 |
|
T26 |
95 |
|
T27 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13755166 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
103785 |
| auto[1] |
794398 |
1 |
|
|
T24 |
6165 |
|
T26 |
12 |
|
T29 |
52502 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8427579 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
60347 |
| auto[1] |
6121985 |
1 |
|
|
T24 |
49603 |
|
T26 |
137 |
|
T29 |
394756 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2658876 |
1 |
|
|
T24 |
22228 |
|
T26 |
75 |
|
T29 |
171031 |
| auto[1] |
auto[0] |
auto[1] |
396382 |
1 |
|
|
T24 |
3219 |
|
T26 |
5 |
|
T29 |
26351 |
| auto[1] |
auto[1] |
auto[0] |
2668711 |
1 |
|
|
T24 |
21210 |
|
T26 |
50 |
|
T29 |
171223 |
| auto[1] |
auto[1] |
auto[1] |
398016 |
1 |
|
|
T24 |
2946 |
|
T26 |
7 |
|
T29 |
26151 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8458135 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
60163 |
| auto[1] |
6091429 |
1 |
|
|
T24 |
49787 |
|
T26 |
71 |
|
T29 |
387526 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13757698 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104351 |
| auto[1] |
791866 |
1 |
|
|
T24 |
5599 |
|
T26 |
2 |
|
T29 |
51096 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8441057 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
64503 |
| auto[1] |
6108507 |
1 |
|
|
T24 |
45447 |
|
T26 |
98 |
|
T27 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2663996 |
1 |
|
|
T24 |
19079 |
|
T26 |
73 |
|
T27 |
18 |
| auto[1] |
auto[0] |
auto[1] |
398556 |
1 |
|
|
T24 |
2671 |
|
T26 |
2 |
|
T29 |
26125 |
| auto[1] |
auto[1] |
auto[0] |
2652645 |
1 |
|
|
T24 |
20769 |
|
T26 |
23 |
|
T29 |
164147 |
| auto[1] |
auto[1] |
auto[1] |
393310 |
1 |
|
|
T24 |
2928 |
|
T29 |
24971 |
|
T1 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8473107 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62477 |
| auto[1] |
6076457 |
1 |
|
|
T24 |
47473 |
|
T26 |
95 |
|
T27 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13757299 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
103652 |
| auto[1] |
792265 |
1 |
|
|
T24 |
6298 |
|
T26 |
8 |
|
T29 |
52903 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8438444 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
59737 |
| auto[1] |
6111120 |
1 |
|
|
T24 |
50213 |
|
T26 |
156 |
|
T27 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2670364 |
1 |
|
|
T24 |
21987 |
|
T26 |
109 |
|
T29 |
177395 |
| auto[1] |
auto[0] |
auto[1] |
397684 |
1 |
|
|
T24 |
3174 |
|
T26 |
6 |
|
T29 |
27204 |
| auto[1] |
auto[1] |
auto[0] |
2648491 |
1 |
|
|
T24 |
21928 |
|
T26 |
39 |
|
T27 |
8 |
| auto[1] |
auto[1] |
auto[1] |
394581 |
1 |
|
|
T24 |
3124 |
|
T26 |
2 |
|
T29 |
25699 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8459459 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62544 |
| auto[1] |
6090105 |
1 |
|
|
T24 |
47406 |
|
T26 |
98 |
|
T27 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13761860 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104086 |
| auto[1] |
787704 |
1 |
|
|
T24 |
5864 |
|
T26 |
5 |
|
T29 |
50956 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8465185 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63292 |
| auto[1] |
6084379 |
1 |
|
|
T24 |
46658 |
|
T26 |
105 |
|
T27 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2656030 |
1 |
|
|
T24 |
20068 |
|
T26 |
58 |
|
T29 |
165054 |
| auto[1] |
auto[0] |
auto[1] |
396001 |
1 |
|
|
T24 |
2983 |
|
T26 |
2 |
|
T29 |
24859 |
| auto[1] |
auto[1] |
auto[0] |
2640645 |
1 |
|
|
T24 |
20726 |
|
T26 |
42 |
|
T27 |
8 |
| auto[1] |
auto[1] |
auto[1] |
391703 |
1 |
|
|
T24 |
2881 |
|
T26 |
3 |
|
T29 |
26097 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8407782 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63584 |
| auto[1] |
6141782 |
1 |
|
|
T24 |
46366 |
|
T26 |
81 |
|
T27 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13759346 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104088 |
| auto[1] |
790218 |
1 |
|
|
T24 |
5862 |
|
T26 |
6 |
|
T29 |
52957 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8449311 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62667 |
| auto[1] |
6100253 |
1 |
|
|
T24 |
47283 |
|
T26 |
139 |
|
T27 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2635753 |
1 |
|
|
T24 |
21262 |
|
T26 |
84 |
|
T27 |
5 |
| auto[1] |
auto[0] |
auto[1] |
390682 |
1 |
|
|
T24 |
3045 |
|
T26 |
4 |
|
T29 |
26287 |
| auto[1] |
auto[1] |
auto[0] |
2674282 |
1 |
|
|
T24 |
20159 |
|
T26 |
49 |
|
T27 |
5 |
| auto[1] |
auto[1] |
auto[1] |
399536 |
1 |
|
|
T24 |
2817 |
|
T26 |
2 |
|
T29 |
26670 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8488783 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
61481 |
| auto[1] |
6060781 |
1 |
|
|
T24 |
48469 |
|
T26 |
103 |
|
T29 |
376826 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13757142 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
103862 |
| auto[1] |
792422 |
1 |
|
|
T24 |
6088 |
|
T26 |
7 |
|
T29 |
50714 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8437010 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
61158 |
| auto[1] |
6112554 |
1 |
|
|
T24 |
48792 |
|
T26 |
125 |
|
T27 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2673646 |
1 |
|
|
T24 |
20556 |
|
T26 |
52 |
|
T27 |
18 |
| auto[1] |
auto[0] |
auto[1] |
398691 |
1 |
|
|
T24 |
2866 |
|
T26 |
3 |
|
T29 |
25394 |
| auto[1] |
auto[1] |
auto[0] |
2646486 |
1 |
|
|
T24 |
22148 |
|
T26 |
66 |
|
T29 |
167010 |
| auto[1] |
auto[1] |
auto[1] |
393731 |
1 |
|
|
T24 |
3222 |
|
T26 |
4 |
|
T29 |
25320 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8456469 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63622 |
| auto[1] |
6093095 |
1 |
|
|
T24 |
46328 |
|
T26 |
118 |
|
T27 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13760679 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104114 |
| auto[1] |
788885 |
1 |
|
|
T24 |
5836 |
|
T26 |
9 |
|
T29 |
51802 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8457549 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63154 |
| auto[1] |
6092015 |
1 |
|
|
T24 |
46796 |
|
T26 |
142 |
|
T29 |
392489 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2652996 |
1 |
|
|
T24 |
21450 |
|
T26 |
66 |
|
T29 |
164180 |
| auto[1] |
auto[0] |
auto[1] |
394188 |
1 |
|
|
T24 |
3088 |
|
T26 |
5 |
|
T29 |
24915 |
| auto[1] |
auto[1] |
auto[0] |
2650134 |
1 |
|
|
T24 |
19510 |
|
T26 |
67 |
|
T29 |
176507 |
| auto[1] |
auto[1] |
auto[1] |
394697 |
1 |
|
|
T24 |
2748 |
|
T26 |
4 |
|
T29 |
26887 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8445770 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62373 |
| auto[1] |
6103794 |
1 |
|
|
T24 |
47577 |
|
T26 |
162 |
|
T29 |
378072 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13760666 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104360 |
| auto[1] |
788898 |
1 |
|
|
T24 |
5590 |
|
T26 |
6 |
|
T29 |
51058 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8456295 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
64324 |
| auto[1] |
6093269 |
1 |
|
|
T24 |
45626 |
|
T26 |
75 |
|
T27 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2661020 |
1 |
|
|
T24 |
20042 |
|
T26 |
6 |
|
T27 |
10 |
| auto[1] |
auto[0] |
auto[1] |
395827 |
1 |
|
|
T24 |
2808 |
|
T29 |
27076 |
|
T1 |
22 |
| auto[1] |
auto[1] |
auto[0] |
2643351 |
1 |
|
|
T24 |
19994 |
|
T26 |
63 |
|
T29 |
161049 |
| auto[1] |
auto[1] |
auto[1] |
393071 |
1 |
|
|
T24 |
2782 |
|
T26 |
6 |
|
T29 |
23982 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8465181 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
64820 |
| auto[1] |
6084383 |
1 |
|
|
T24 |
45130 |
|
T26 |
120 |
|
T27 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13760032 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
103994 |
| auto[1] |
789532 |
1 |
|
|
T24 |
5956 |
|
T26 |
11 |
|
T29 |
52767 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8448584 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62182 |
| auto[1] |
6100980 |
1 |
|
|
T24 |
47768 |
|
T26 |
147 |
|
T27 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2667033 |
1 |
|
|
T24 |
21778 |
|
T26 |
56 |
|
T27 |
9 |
| auto[1] |
auto[0] |
auto[1] |
397567 |
1 |
|
|
T24 |
3227 |
|
T26 |
4 |
|
T29 |
25916 |
| auto[1] |
auto[1] |
auto[0] |
2644415 |
1 |
|
|
T24 |
20034 |
|
T26 |
80 |
|
T27 |
1 |
| auto[1] |
auto[1] |
auto[1] |
391965 |
1 |
|
|
T24 |
2729 |
|
T26 |
7 |
|
T29 |
26851 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8439580 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
61834 |
| auto[1] |
6109984 |
1 |
|
|
T24 |
48116 |
|
T26 |
90 |
|
T27 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13761201 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
103948 |
| auto[1] |
788363 |
1 |
|
|
T24 |
6002 |
|
T26 |
10 |
|
T29 |
50905 |