Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8488141 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62729 |
| auto[1] |
6061423 |
1 |
|
|
T24 |
47221 |
|
T26 |
136 |
|
T27 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13759394 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104255 |
| auto[1] |
790170 |
1 |
|
|
T24 |
5695 |
|
T26 |
4 |
|
T29 |
51387 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8449918 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62872 |
| auto[1] |
6099646 |
1 |
|
|
T24 |
47078 |
|
T26 |
99 |
|
T29 |
387678 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2676025 |
1 |
|
|
T24 |
21029 |
|
T26 |
33 |
|
T29 |
169741 |
| auto[1] |
auto[0] |
auto[1] |
399908 |
1 |
|
|
T24 |
2946 |
|
T26 |
1 |
|
T29 |
25911 |
| auto[1] |
auto[1] |
auto[0] |
2633451 |
1 |
|
|
T24 |
20354 |
|
T26 |
62 |
|
T29 |
166550 |
| auto[1] |
auto[1] |
auto[1] |
390262 |
1 |
|
|
T24 |
2749 |
|
T26 |
3 |
|
T29 |
25476 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |