Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8484945 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62158 |
| auto[1] |
6064619 |
1 |
|
|
T24 |
47792 |
|
T26 |
60 |
|
T27 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13754660 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104022 |
| auto[1] |
794904 |
1 |
|
|
T24 |
5928 |
|
T26 |
6 |
|
T29 |
52283 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8423009 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62536 |
| auto[1] |
6126555 |
1 |
|
|
T24 |
47414 |
|
T26 |
82 |
|
T27 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2690903 |
1 |
|
|
T24 |
20496 |
|
T26 |
48 |
|
T27 |
5 |
| auto[1] |
auto[0] |
auto[1] |
403232 |
1 |
|
|
T24 |
3014 |
|
T26 |
3 |
|
T29 |
25961 |
| auto[1] |
auto[1] |
auto[0] |
2640748 |
1 |
|
|
T24 |
20990 |
|
T26 |
28 |
|
T27 |
5 |
| auto[1] |
auto[1] |
auto[1] |
391672 |
1 |
|
|
T24 |
2914 |
|
T26 |
3 |
|
T29 |
26322 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |