Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8446145 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63008 |
| auto[1] |
6103419 |
1 |
|
|
T24 |
46942 |
|
T26 |
170 |
|
T27 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13762277 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104283 |
| auto[1] |
787287 |
1 |
|
|
T24 |
5667 |
|
T26 |
8 |
|
T29 |
51279 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8475186 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
64107 |
| auto[1] |
6074378 |
1 |
|
|
T24 |
45843 |
|
T26 |
93 |
|
T27 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2633497 |
1 |
|
|
T24 |
20455 |
|
T26 |
18 |
|
T29 |
164106 |
| auto[1] |
auto[0] |
auto[1] |
391608 |
1 |
|
|
T24 |
3063 |
|
T26 |
4 |
|
T29 |
24970 |
| auto[1] |
auto[1] |
auto[0] |
2653594 |
1 |
|
|
T24 |
19721 |
|
T26 |
67 |
|
T27 |
8 |
| auto[1] |
auto[1] |
auto[1] |
395679 |
1 |
|
|
T24 |
2604 |
|
T26 |
4 |
|
T29 |
26309 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |