Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8442938 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
59923 |
| auto[1] |
6106626 |
1 |
|
|
T24 |
50027 |
|
T26 |
112 |
|
T27 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13760438 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
103889 |
| auto[1] |
789126 |
1 |
|
|
T24 |
6061 |
|
T26 |
6 |
|
T29 |
51726 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8464450 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
61463 |
| auto[1] |
6085114 |
1 |
|
|
T24 |
48487 |
|
T26 |
99 |
|
T27 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2629102 |
1 |
|
|
T24 |
19667 |
|
T26 |
52 |
|
T27 |
18 |
| auto[1] |
auto[0] |
auto[1] |
390928 |
1 |
|
|
T24 |
2836 |
|
T26 |
4 |
|
T29 |
25605 |
| auto[1] |
auto[1] |
auto[0] |
2666886 |
1 |
|
|
T24 |
22759 |
|
T26 |
41 |
|
T29 |
167742 |
| auto[1] |
auto[1] |
auto[1] |
398198 |
1 |
|
|
T24 |
3225 |
|
T26 |
2 |
|
T29 |
26121 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |