Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8484438 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62425 |
| auto[1] |
6065126 |
1 |
|
|
T24 |
47525 |
|
T26 |
144 |
|
T27 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12037672 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
91822 |
| auto[1] |
2511892 |
1 |
|
|
T24 |
18128 |
|
T26 |
50 |
|
T27 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8453774 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62648 |
| auto[1] |
6095790 |
1 |
|
|
T24 |
47302 |
|
T26 |
111 |
|
T27 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1806535 |
1 |
|
|
T24 |
14643 |
|
T26 |
29 |
|
T29 |
124325 |
| auto[1] |
auto[0] |
auto[1] |
1263713 |
1 |
|
|
T24 |
8970 |
|
T26 |
13 |
|
T29 |
76974 |
| auto[1] |
auto[1] |
auto[0] |
1777363 |
1 |
|
|
T24 |
14531 |
|
T26 |
32 |
|
T29 |
115408 |
| auto[1] |
auto[1] |
auto[1] |
1248179 |
1 |
|
|
T24 |
9158 |
|
T26 |
37 |
|
T27 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |