Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8462749 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
61431 |
| auto[1] |
6086815 |
1 |
|
|
T24 |
48519 |
|
T26 |
109 |
|
T27 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12032263 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
92134 |
| auto[1] |
2517301 |
1 |
|
|
T24 |
17816 |
|
T26 |
53 |
|
T29 |
148602 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8447867 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62465 |
| auto[1] |
6101697 |
1 |
|
|
T24 |
47485 |
|
T26 |
134 |
|
T27 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1798454 |
1 |
|
|
T24 |
13981 |
|
T26 |
48 |
|
T27 |
12 |
| auto[1] |
auto[0] |
auto[1] |
1263698 |
1 |
|
|
T24 |
8354 |
|
T26 |
36 |
|
T29 |
75625 |
| auto[1] |
auto[1] |
auto[0] |
1785942 |
1 |
|
|
T24 |
15688 |
|
T26 |
33 |
|
T29 |
116482 |
| auto[1] |
auto[1] |
auto[1] |
1253603 |
1 |
|
|
T24 |
9462 |
|
T26 |
17 |
|
T29 |
72977 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |