Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8460263 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62269 |
| auto[1] |
6089301 |
1 |
|
|
T24 |
47681 |
|
T26 |
93 |
|
T27 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12040516 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
91770 |
| auto[1] |
2509048 |
1 |
|
|
T24 |
18180 |
|
T26 |
59 |
|
T27 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8462489 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62707 |
| auto[1] |
6087075 |
1 |
|
|
T24 |
47243 |
|
T26 |
122 |
|
T27 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1783233 |
1 |
|
|
T24 |
14939 |
|
T26 |
46 |
|
T29 |
119045 |
| auto[1] |
auto[0] |
auto[1] |
1250158 |
1 |
|
|
T24 |
9217 |
|
T26 |
42 |
|
T27 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1794794 |
1 |
|
|
T24 |
14124 |
|
T26 |
17 |
|
T29 |
120073 |
| auto[1] |
auto[1] |
auto[1] |
1258890 |
1 |
|
|
T24 |
8963 |
|
T26 |
17 |
|
T29 |
74670 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |