Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8469798 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63403 |
| auto[1] |
6079766 |
1 |
|
|
T24 |
46547 |
|
T26 |
130 |
|
T27 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12040932 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
92009 |
| auto[1] |
2508632 |
1 |
|
|
T24 |
17941 |
|
T26 |
49 |
|
T29 |
148788 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8453165 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62708 |
| auto[1] |
6096399 |
1 |
|
|
T24 |
47242 |
|
T26 |
116 |
|
T27 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1795722 |
1 |
|
|
T24 |
14718 |
|
T26 |
27 |
|
T27 |
8 |
| auto[1] |
auto[0] |
auto[1] |
1260301 |
1 |
|
|
T24 |
9086 |
|
T26 |
13 |
|
T29 |
74480 |
| auto[1] |
auto[1] |
auto[0] |
1792045 |
1 |
|
|
T24 |
14583 |
|
T26 |
40 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[1] |
1248331 |
1 |
|
|
T24 |
8855 |
|
T26 |
36 |
|
T29 |
74308 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |