Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8448597 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63358 |
| auto[1] |
6100967 |
1 |
|
|
T24 |
46592 |
|
T26 |
70 |
|
T27 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12033558 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
91699 |
| auto[1] |
2516006 |
1 |
|
|
T24 |
18251 |
|
T26 |
54 |
|
T27 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8435730 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62909 |
| auto[1] |
6113834 |
1 |
|
|
T24 |
47041 |
|
T26 |
105 |
|
T27 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1794968 |
1 |
|
|
T24 |
15193 |
|
T26 |
41 |
|
T29 |
117355 |
| auto[1] |
auto[0] |
auto[1] |
1251807 |
1 |
|
|
T24 |
9435 |
|
T26 |
36 |
|
T27 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1802860 |
1 |
|
|
T24 |
13597 |
|
T26 |
10 |
|
T29 |
117741 |
| auto[1] |
auto[1] |
auto[1] |
1264199 |
1 |
|
|
T24 |
8816 |
|
T26 |
18 |
|
T29 |
74109 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |