Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8462216 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62382 |
| auto[1] |
6087348 |
1 |
|
|
T24 |
47568 |
|
T26 |
128 |
|
T27 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2651807 |
1 |
|
|
T24 |
19686 |
|
T26 |
79 |
|
T27 |
8 |
| auto[1] |
auto[0] |
auto[1] |
393768 |
1 |
|
|
T24 |
2689 |
|
T26 |
8 |
|
T29 |
25538 |
| auto[1] |
auto[1] |
auto[0] |
2647178 |
1 |
|
|
T24 |
21880 |
|
T26 |
39 |
|
T29 |
164659 |
| auto[1] |
auto[1] |
auto[1] |
394595 |
1 |
|
|
T24 |
3313 |
|
T26 |
2 |
|
T29 |
25367 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |