Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8434420 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
61859 |
| auto[1] |
6115144 |
1 |
|
|
T24 |
48091 |
|
T26 |
123 |
|
T27 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12042792 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
91349 |
| auto[1] |
2506772 |
1 |
|
|
T24 |
18601 |
|
T26 |
45 |
|
T29 |
149850 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8460129 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62372 |
| auto[1] |
6089435 |
1 |
|
|
T24 |
47578 |
|
T26 |
119 |
|
T27 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1787125 |
1 |
|
|
T24 |
14037 |
|
T26 |
29 |
|
T29 |
113176 |
| auto[1] |
auto[0] |
auto[1] |
1250990 |
1 |
|
|
T24 |
9022 |
|
T26 |
17 |
|
T29 |
72337 |
| auto[1] |
auto[1] |
auto[0] |
1795538 |
1 |
|
|
T24 |
14940 |
|
T26 |
45 |
|
T27 |
7 |
| auto[1] |
auto[1] |
auto[1] |
1255782 |
1 |
|
|
T24 |
9579 |
|
T26 |
28 |
|
T29 |
77513 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |