Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8448169 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63787 |
| auto[1] |
6101395 |
1 |
|
|
T24 |
46163 |
|
T26 |
169 |
|
T27 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12027963 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
91885 |
| auto[1] |
2521601 |
1 |
|
|
T24 |
18065 |
|
T26 |
55 |
|
T29 |
149062 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8429068 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63274 |
| auto[1] |
6120496 |
1 |
|
|
T24 |
46676 |
|
T26 |
116 |
|
T27 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1800228 |
1 |
|
|
T24 |
14474 |
|
T26 |
9 |
|
T27 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1261855 |
1 |
|
|
T24 |
9452 |
|
T26 |
10 |
|
T29 |
75170 |
| auto[1] |
auto[1] |
auto[0] |
1798667 |
1 |
|
|
T24 |
14137 |
|
T26 |
52 |
|
T27 |
6 |
| auto[1] |
auto[1] |
auto[1] |
1259746 |
1 |
|
|
T24 |
8613 |
|
T26 |
45 |
|
T29 |
73892 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |