Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8431707 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
61713 |
auto[1] |
6117857 |
1 |
|
|
T24 |
48237 |
|
T26 |
112 |
|
T27 |
9 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12031424 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
92125 |
auto[1] |
2518140 |
1 |
|
|
T24 |
17825 |
|
T26 |
31 |
|
T29 |
148320 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8428691 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63365 |
auto[1] |
6120873 |
1 |
|
|
T24 |
46585 |
|
T26 |
85 |
|
T29 |
386324 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1795634 |
1 |
|
|
T24 |
13306 |
|
T26 |
21 |
|
T29 |
118011 |
auto[1] |
auto[0] |
auto[1] |
1255531 |
1 |
|
|
T24 |
8478 |
|
T26 |
17 |
|
T29 |
73578 |
auto[1] |
auto[1] |
auto[0] |
1807099 |
1 |
|
|
T24 |
15454 |
|
T26 |
33 |
|
T29 |
119993 |
auto[1] |
auto[1] |
auto[1] |
1262609 |
1 |
|
|
T24 |
9347 |
|
T26 |
14 |
|
T29 |
74742 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |