Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8477331 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63133 |
| auto[1] |
6072233 |
1 |
|
|
T24 |
46817 |
|
T26 |
89 |
|
T27 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12036927 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
91954 |
| auto[1] |
2512637 |
1 |
|
|
T24 |
17996 |
|
T26 |
72 |
|
T29 |
150036 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8438952 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63265 |
| auto[1] |
6110612 |
1 |
|
|
T24 |
46685 |
|
T26 |
162 |
|
T27 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1792174 |
1 |
|
|
T24 |
14642 |
|
T26 |
75 |
|
T27 |
7 |
| auto[1] |
auto[0] |
auto[1] |
1255742 |
1 |
|
|
T24 |
9037 |
|
T26 |
43 |
|
T29 |
75785 |
| auto[1] |
auto[1] |
auto[0] |
1805801 |
1 |
|
|
T24 |
14047 |
|
T26 |
15 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[1] |
1256895 |
1 |
|
|
T24 |
8959 |
|
T26 |
29 |
|
T29 |
74251 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |