Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8437822 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62930 |
| auto[1] |
6111742 |
1 |
|
|
T24 |
47020 |
|
T26 |
95 |
|
T27 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12046032 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
90578 |
| auto[1] |
2503532 |
1 |
|
|
T24 |
19372 |
|
T26 |
25 |
|
T27 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8462234 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
59816 |
| auto[1] |
6087330 |
1 |
|
|
T24 |
50134 |
|
T26 |
96 |
|
T27 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1783951 |
1 |
|
|
T24 |
15361 |
|
T26 |
43 |
|
T29 |
119022 |
| auto[1] |
auto[0] |
auto[1] |
1251356 |
1 |
|
|
T24 |
10035 |
|
T26 |
10 |
|
T27 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1799847 |
1 |
|
|
T24 |
15401 |
|
T26 |
28 |
|
T29 |
122839 |
| auto[1] |
auto[1] |
auto[1] |
1252176 |
1 |
|
|
T24 |
9337 |
|
T26 |
15 |
|
T27 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |