Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8458135 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
60163 |
| auto[1] |
6091429 |
1 |
|
|
T24 |
49787 |
|
T26 |
71 |
|
T29 |
387526 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12042127 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
92152 |
| auto[1] |
2507437 |
1 |
|
|
T24 |
17798 |
|
T26 |
56 |
|
T29 |
152963 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8439097 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63030 |
| auto[1] |
6110467 |
1 |
|
|
T24 |
46920 |
|
T26 |
111 |
|
T27 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1805754 |
1 |
|
|
T24 |
14223 |
|
T26 |
44 |
|
T27 |
12 |
| auto[1] |
auto[0] |
auto[1] |
1258051 |
1 |
|
|
T24 |
8729 |
|
T26 |
41 |
|
T29 |
76801 |
| auto[1] |
auto[1] |
auto[0] |
1797276 |
1 |
|
|
T24 |
14899 |
|
T26 |
11 |
|
T29 |
120390 |
| auto[1] |
auto[1] |
auto[1] |
1249386 |
1 |
|
|
T24 |
9069 |
|
T26 |
15 |
|
T29 |
76162 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |