Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8473107 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62477 |
| auto[1] |
6076457 |
1 |
|
|
T24 |
47473 |
|
T26 |
95 |
|
T27 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12046278 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
91563 |
| auto[1] |
2503286 |
1 |
|
|
T24 |
18387 |
|
T26 |
50 |
|
T29 |
149659 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8472212 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62351 |
| auto[1] |
6077352 |
1 |
|
|
T24 |
47599 |
|
T26 |
131 |
|
T27 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1793094 |
1 |
|
|
T24 |
14802 |
|
T26 |
53 |
|
T29 |
120234 |
| auto[1] |
auto[0] |
auto[1] |
1254792 |
1 |
|
|
T24 |
9017 |
|
T26 |
26 |
|
T29 |
75317 |
| auto[1] |
auto[1] |
auto[0] |
1780972 |
1 |
|
|
T24 |
14410 |
|
T26 |
28 |
|
T27 |
3 |
| auto[1] |
auto[1] |
auto[1] |
1248494 |
1 |
|
|
T24 |
9370 |
|
T26 |
24 |
|
T29 |
74342 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |