Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8459459 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62544 |
auto[1] |
6090105 |
1 |
|
|
T24 |
47406 |
|
T26 |
98 |
|
T27 |
9 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12053020 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
92196 |
auto[1] |
2496544 |
1 |
|
|
T24 |
17754 |
|
T26 |
39 |
|
T29 |
148409 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8480217 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
64232 |
auto[1] |
6069347 |
1 |
|
|
T24 |
45718 |
|
T26 |
77 |
|
T29 |
386070 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1799494 |
1 |
|
|
T24 |
14072 |
|
T26 |
26 |
|
T29 |
120253 |
auto[1] |
auto[0] |
auto[1] |
1259273 |
1 |
|
|
T24 |
9112 |
|
T26 |
5 |
|
T29 |
73977 |
auto[1] |
auto[1] |
auto[0] |
1773309 |
1 |
|
|
T24 |
13892 |
|
T26 |
12 |
|
T29 |
117408 |
auto[1] |
auto[1] |
auto[1] |
1237271 |
1 |
|
|
T24 |
8642 |
|
T26 |
34 |
|
T29 |
74432 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |